Analog-digital conversion device, successive approximation analog-digital converter, and electronic device

Abstract

The present disclosure relates to an analog-to-digital conversion device, a successive approximation analog-to-digital converter and an electronic device, the device comprising a plurality of sampling switches, a plurality of sampling capacitors, a successive approximation logic (SAR) control module, a charge pump, a voltage boosting module and a cascade of N comparison units, a gate of each zeroth transistor and a gate of each first transistor being configured to receive a sampling signal, the charge pump being configured to boost a power supply voltage based on an N+1th initial sampling signal to obtain a boosted power supply voltage, the voltage boosting module being configured to receive the boosted power supply voltage and boost the N+1 initial sampling signals respectively to obtain N+1 sampling signals, and the SAR control module being configured to control connection states of the switches and obtain the conversion voltage based on a comparison result of a comparator of an Nth unit. The present disclosure improves the conversion speed and conversion accuracy of the analog-to-digital conversion device and improves the working capability of the analog-to-digital conversion device in a low voltage environment.

Description

Technical Field

[0001] This disclosure relates to the field of analog-to-digital conversion technology, and more particularly to an analog-to-digital conversion device, a successive approximation analog-to-digital converter, and an electronic device. Background Technology

[0002] ADCs (Analog-to-Digital Converters) are used to convert analog signals from nature into digital signals that machines can recognize. Among them, SAR ADCs (Successive Approximation Analog-to-Digital Converters) are widely used due to their advantages of low power consumption and small size. However, SAR ADCs have problems with low sampling accuracy and sampling speed under low voltage, making them unsuitable for low-voltage environments. Summary of the Invention

[0003] According to one aspect of this disclosure, an analog-to-digital converter is provided, the converter being used to perform analog-to-digital conversion on an input voltage to obtain a converted voltage. The converter includes multiple sampling switches, multiple sampling capacitors, a successive approximation logic (SAR) control module, a charge pump, a boost module, and N cascaded comparator units.

[0004] Each comparison unit includes a zeroth transistor, a first transistor, and a comparator. The drain of each zeroth transistor and the drain of each first transistor are used to receive a first reference voltage. The source of each zeroth transistor is connected to the negative input terminal of the corresponding comparator, and the source of each first transistor is connected to the positive input terminal of the corresponding comparator. The output terminal of the comparator in the M-th stage comparison unit is coupled to the positive input terminal of the comparator in the (M+1)-th stage comparison unit. The ground terminal of the comparator in the M-th stage comparison unit is coupled to the negative input terminal of the comparator in the (M+1)-th stage comparison unit, where M+1≤N and M and N are both integers.

[0005] The gates of each zeroth transistor and each first transistor are used to receive sampling signals. The zeroth transistor and the first transistor in the same comparison unit receive the same sampling signal, which is used to control the conduction state of the corresponding zeroth transistor and the first transistor.

[0006] The charge pump is used to boost the power supply voltage based on the (N+1)th initial sampling signal to obtain the boosted power supply voltage, wherein the (N+1)th initial sampling signal has the same frequency but different phase.

[0007] The boost module receives the boosted power supply voltage and boosts the N+1 initial sampling signals to obtain N+1 sampling signals. The first N sampling signals are applied sequentially to N cascaded comparator units according to their phase delay order.

[0008] The first terminal of each sampling capacitor is connected to the non-inverting input of the comparator in the first-stage comparison unit, and the second terminal of each sampling capacitor is connected to a corresponding sampling switch. The sampling switch is used to connect any one of the input voltage, the second reference voltage, or the ground voltage to the second terminal of the corresponding sampling capacitor. Specifically, when the (N+1)th sampling signal is high, the input voltage is connected to the second terminal of each sampling capacitor.

[0009] The output of the comparator in the Nth-level comparison unit is connected to the SAR control module. The SAR control module is used to control the connection state of each switch and obtain the conversion voltage based on the comparison result of the comparator in the Nth-level unit.

[0010] In one possible implementation, a first capacitor is provided between the output terminal of the comparator in the M-th stage comparator unit and the positive input terminal of the comparator in the (M+1)-th stage comparator unit, and a second capacitor is provided between the ground terminal of the comparator in the M-th stage comparator unit and the negative input terminal of the comparator in the (M+1)-th stage comparator unit.

[0011] In one possible implementation, the charge pump includes a zeroth inverter, a first inverter, a zeroth PMOS transistor, a first PMOS transistor, a zeroth NMOS transistor, a first NMOS transistor, a second NMOS transistor, a third capacitor, and a first diode, wherein...

[0012] The input terminals of the zeroth inverter and the first inverter are used to receive the (N+1)th initial sampling signal. The power supply terminals of the zeroth inverter and the first inverter are used to receive the power supply voltage. The ground terminal of the first inverter is grounded.

[0013] The output terminal of the zeroth inverter is connected to the gate of the first PMOS transistor, and the ground terminal of the zeroth inverter is connected to the first terminal of the third capacitor, the drain of the zeroth NMOS transistor, and the source of the first NMOS transistor.

[0014] The output of the first inverter is connected to the gate of the zeroth NMOS transistor, and the source of the zeroth NMOS transistor is connected to the anode of the first diode and grounded.

[0015] The cathode of the first diode is connected to the source of the first PMOS transistor, the source of the zeroth PMOS transistor, and the second terminal of the third capacitor, for outputting the boosted power supply voltage.

[0016] The drain of the zeroth PMOS transistor is used to receive the power supply voltage, and the gate of the zeroth PMOS transistor is connected to the gate of the first NMOS transistor, the source of the second NMOS transistor, and the drain of the first PMOS transistor.

[0017] The drain of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is used to receive the opposite signal of the (N+1)th initial sampled signal.

[0018] The drain of the first NMOS transistor is used to receive the first reference voltage.

[0019] In one possible implementation, the device further includes:

[0020] The delay module is used to delay the first initial sampling signal multiple times to obtain various initial sampling signals.

[0021] In one possible implementation, the device further includes a third transistor, wherein,

[0022] The source of the third transistor is used to receive the input voltage, the gate of the third transistor is used to receive the (N+1)th sampled signal, and the drain of the third transistor is connected to each sampling switch.

[0023] In one possible implementation, the boost module includes a second NOT gate, a third NOT gate, a fourth NOT gate, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, wherein...

[0024] The input terminal of the second NOT gate is used to input the initial sampling signal, the output terminal of the second NOT gate is connected to the gate of the sixth transistor and the input terminal of the third NOT gate, and the power supply terminal of the second NOT gate is connected to the power supply voltage.

[0025] The source of the sixth transistor, the source of the ninth transistor, the ground terminal of the second NOT gate, the third NOT gate, and the fourth NOT gate are all grounded.

[0026] The drain of the sixth transistor is connected to the source of the seventh transistor and the gate of the eighth transistor.

[0027] The gate of the seventh transistor is connected to the source of the eighth transistor, the input of the fourth NOT gate, and the drain of the ninth transistor. The drain of the seventh transistor is connected to the drain of the eighth transistor and the power supply terminal of the fourth NOT gate, for connecting to a second power supply voltage.

[0028] The output terminal of the third NOT gate is connected to the gate of the ninth transistor, and the power supply terminal of the third NOT gate is connected to the power supply voltage.

[0029] The output of the fourth NOT gate is used to output the boosted sampled signal.

[0030] In one possible implementation, the sixth and ninth transistors are NMOS transistors, and the seventh and eighth transistors are PMOS transistors.

[0031] In one possible implementation, the device includes N+1 boost modules, the power supply terminal of each boost module being connected to the output terminal of the charge pump to receive the boosted power supply voltage; the input terminal of each boost module is used to receive each initial sampling signal, and the output terminal of each boost module is used to output the corresponding sampling signal.

[0032] According to one aspect of this disclosure, a successive approximation analog-to-digital converter is provided, the successive approximation analog-to-digital converter including the aforementioned analog-to-digital conversion device.

[0033] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the successive approximation analog-to-digital converter described above.

[0034] The analog-to-digital converter (ADC) of this embodiment uses a charge pump to boost the power supply voltage based on the (N+1)th initial sampling signal to obtain a boosted power supply voltage. The boost module receives the boosted power supply voltage and boosts the N+1 initial sampling signals respectively to obtain N+1 sampling signals. This improves the level of each sampling signal and the conduction capability of each transistor, thereby improving the conversion speed and accuracy of the ADC and enhancing its ability to operate in low-voltage environments.

[0035] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0037] Figure 1 A schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0038] Figure 2 A schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0039] Figure 3 A schematic diagram of a boost scheme according to an embodiment of the present disclosure is shown.

[0040] Figure 4 A schematic diagram of various signals according to embodiments of the present disclosure is shown.

[0041] Figure 5 A schematic diagram of a boost module according to an embodiment of the present disclosure is shown.

[0042] Figure 6 A schematic diagram of a charge pump according to an embodiment of the present disclosure is shown. Detailed Implementation

[0043] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0044] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0046] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0047] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0048] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0049] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0050] Please see Figure 1 , Figure 1 A schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0051] like Figure 1 As shown, the device is used to perform analog-to-digital conversion on the input voltage VIN to obtain a converted voltage. The device includes multiple sampling switches (such as K0 to K9), multiple sampling capacitors (such as C0 to C9), a successive approximation logic SAR control module 10, a charge pump 20, a boost module 30, and N cascaded comparator units 40, wherein...

[0052] Each comparison unit 40 includes a zeroth transistor Q0, a first transistor Q1, and a comparator (Cmp1 to CompN). The drain of each zeroth transistor Q0 and the drain of each first transistor Q1 are used to receive a first reference voltage VCM. The source of each zeroth transistor Q0 is connected to the negative input terminal of the corresponding comparator, and the source of each first transistor Q1 is connected to the positive input terminal of the corresponding comparator. The output terminal of the comparator in the M-th stage comparison unit 40 is coupled to the positive input terminal of the comparator in the (M+1)-th stage comparison unit 40. The ground terminal of the comparator in the M-th stage comparison unit 40 is coupled to the negative input terminal of the comparator in the (M+1)-th stage comparison unit 40, where M+1≤N and M and N are both integers.

[0053] The gates of each zeroth transistor Q0 and each first transistor Q1 are used to receive sampling signals (Smple1_pump to SmpleN_pump). In the same comparison unit 40, the zeroth transistor Q0 and the first transistor Q1 receive the same sampling signal (e.g., in comparison unit 1, the zeroth transistor Q0 and the first transistor Q1 receive the same sampling signal Smple1_pump). These sampling signals are used to control the conduction state of the corresponding zeroth transistor Q0 and the first transistor Q1.

[0054] The charge pump 20 is used to boost the power supply voltage (VDD) according to the (N+1)th initial sampling signal SmpleN+1 to obtain the boosted power supply voltage VDD_pump, wherein the N+1 initial sampling signals are of the same frequency but different phases;

[0055] The boost module 30 is used to receive the boosted power supply voltage VDD_pump and boost the N+1 initial sampling signals respectively to obtain N+1 sampling signals. The first N sampling signals are applied to the N cascaded comparison units 40 in sequence according to the phase delay order.

[0056] The first terminal of each sampling capacitor is connected to the non-inverting input of the comparator in the first-stage comparison unit 40. The second terminal of each sampling capacitor is connected to a corresponding sampling switch. The sampling switch is used to connect any one of the input voltage VIN, the second reference voltage VREF, or the ground voltage GND to the second terminal of the corresponding sampling capacitor. Specifically, when the (N+1)th sampling signal SmpleN+1_pump is high, the input voltage VIN is connected to the second terminal of each sampling capacitor.

[0057] The output of the comparator in the Nth-level comparison unit 40 is connected to the SAR control module 10. The SAR control module 10 is used to control the connection state of each switch and obtain the conversion voltage based on the comparison result of the comparator in the Nth-level unit.

[0058] The analog-to-digital converter (ADC) of this embodiment boosts the power supply voltage VDD based on the (N+1)th initial sampling signal using a charge pump 20 to obtain a boosted power supply voltage VDD_pump. The boost module 30 then receives the boosted power supply voltage VDD_pump and boosts the N+1 initial sampling signals to obtain N+1 sampling signals. This improves the level of each sampling signal and enhances the conduction capability of each transistor, thereby improving the conversion speed and accuracy of the ADC and enhancing its ability to operate in low-voltage environments.

[0059] The present invention does not limit the number of comparison units 40. Those skilled in the art can set the number of comparison units 40 according to actual conditions and needs. For example, the number of comparison units 40 may include at least two, such as two, three, four, etc.

[0060] The embodiments disclosed herein do not limit the specific types of the zeroth transistor Q0 and the first transistor Q1. For example, the zeroth transistor Q0 and the first transistor Q1 can both be NMOS transistors.

[0061] This disclosure does not limit the source of the first reference voltage VCM. For example, the first reference voltage VCM can originate from a voltage divider circuit. This circuit may include multiple voltage divider resistors connected in series between the power supply voltage VDD and ground. By selecting a suitable output node, the required voltage divider signal is obtained. Of course, the voltage divider circuit can also take other forms, which this disclosure does not limit. Furthermore, this disclosure does not limit the specific magnitude of the second reference voltage VREF; those skilled in the art can set it according to actual conditions and needs.

[0062] This disclosure does not limit the specific implementation of the charge pump 20 and the boost module 30. Those skilled in the art can adopt appropriate technical solutions according to actual conditions and needs. This disclosure does not limit the specific magnitude of the boost amplitude of the power supply voltage VDD by the charge pump 20. For example, the charge pump 20 can boost the power supply voltage VDD to between one times the power supply voltage (1×VDD) and two times the power supply voltage (2×VDD), so that the boost module 30 can improve the level of the sampling signal while avoiding excessively high levels that could damage the zeroth transistor Q0 and the first transistor Q1. For example, the first reference voltage VCM can be less than the power supply voltage. The charge pump 20 can raise the power supply voltage to the sum of the first reference voltage VCM and the power supply voltage (VCM+VDD), thereby raising the sampling phase voltage. The raising amplitude is the first reference voltage VCM. Therefore, the boosted power supply voltage is less than twice the power supply voltage. In this way, the present embodiment can raise the power supply voltage level while avoiding the power supply voltage from exceeding twice the power supply voltage, thus preventing the zeroth transistor Q0 and the first transistor Q1 from being destroyed. Furthermore, no additional circuitry is required, reducing costs.

[0063] This disclosure does not limit the specific implementation of the SAR control module 10. Those skilled in the art can adopt appropriate technical solutions according to actual conditions and needs. For example, the SAR control module 10 can be implemented through a SAR logic core and / or processing components. In one example, the processing components include, but are not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0064] Please see Figure 2 , Figure 2 A schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0065] In one possible implementation, such as Figure 2 As shown, a first capacitor C10 is provided between the output terminal of the comparator in the M-th stage comparator unit 40 and the positive input terminal of the comparator in the M+1-th stage comparator unit 40, and a second capacitor C11 is provided between the ground terminal of the comparator in the M-th stage comparator unit 40 and the negative input terminal of the comparator in the M+1-th stage comparator unit 40.

[0066] The embodiments disclosed herein can eliminate comparator offset by setting capacitors between each comparator, thereby improving the accuracy of comparator comparison results and further improving the conversion speed and accuracy of the analog-to-digital converter.

[0067] It should be noted that, Figure 1 , Figure 2 The number of sampling switches and sampling capacitors is exemplary and should not be regarded as a limitation on the embodiments of this disclosure. Those skilled in the art can set the number of sampling switches and sampling capacitors according to actual conditions and needs.

[0068] In one possible implementation, such as Figure 1As shown, the input voltage VIN can be sampled by a transmission gate. For example, the (N+1)th sampling signal SmpleN+1_pump and its inverted form SmpleN+1_pump_b can be fed into the gates of the two transistors of the transmission gate, respectively. When the (N+1)th sampling signal SmpleN+1_pump is high, the transmission gate transmits the input signal VIN to each sampling capacitor. Of course, the input capacitor VIN can also be sampled in other ways, which will be illustrated below.

[0069] For example, in one possible implementation, such as Figure 2 As shown, the device may further include a third transistor Q3, wherein,

[0070] The source of the third transistor Q3 is used to receive the input voltage VIN, the gate of the third transistor Q3 is used to receive the (N+1)th sampling signal SmpleN+1_pump, and the drain of the third transistor Q3 is connected to each sampling switch.

[0071] It should be noted that the embodiments disclosed herein do not limit the specific implementation of controlling the input voltage VIN to be connected to the sampling switch using the (N+1)th sampling signal SmpleN+1_pump. The exemplary description above using the third transistor Q3 as an example should not be regarded as a limitation of the embodiments disclosed herein. In other embodiments, those skilled in the art can adopt other methods according to actual conditions and needs, as long as the input voltage VIN can be controlled to be connected to the sampling switch according to the (N+1)th sampling signal SmpleN+1_pump.

[0072] Please see Figure 3 , Figure 3 A schematic diagram of a boost scheme according to an embodiment of the present disclosure is shown.

[0073] It should be noted that the boost module 30 in this embodiment can be integrated, that is, one boost module 30 completes the boosting of multiple initial sampling signals; on the other hand, the boost module 30 can also be separate, that is, multiple boost modules 30 are included to boost each initial sampling signal respectively. For ease of understanding, this embodiment is described using a separate boost scheme.

[0074] In one possible implementation, such as Figure 3As shown, the device may include N+1 boost modules 30, the power supply terminal of each boost module 30 is connected to the output terminal of the charge pump 20 to receive the boosted power supply voltage VDD_pump; the input terminal of each boost module 30 is used to receive each initial sampling signal, and the output terminal of each boost module 30 is used to output the corresponding sampling signal.

[0075] In one possible implementation, the device may further include:

[0076] The delay module is used to delay the first initial sampling signal multiple times to obtain various initial sampling signals.

[0077] The present disclosure does not limit the specific implementation of the delay module. For example, the delay module can be implemented with a buffer. The specific size of each delay of the delay module can be set according to the actual situation and needs. The present disclosure does not limit this as well.

[0078] Please see Figure 4 , Figure 4 A schematic diagram of various signals according to embodiments of the present disclosure is shown.

[0079] In one example, if the number N of comparison units 40 is 3, then the required sampling signal is 4(N+1). In this case, the delay module can, for example, delay the initial sampling signal Smple1 3 times to obtain the initial sampling signals Smple1 to Smple4 (e.g., ...). Figure 4 As shown, the charge pump 20 boosts the power supply voltage based on the (N+1)th initial sampling signal (e.g., initial sampling signal Smple4) to obtain a boosted power supply voltage VDD_pump. Each boost module 30 receives the boosted power supply voltage VDD_pump and boosts the N+1 initial sampling signals respectively, resulting in N+1 sampling signals (Smple1_pump to Smple4_pump), thus increasing the level of the sampling signals of each zeroth transistor Q0 and first transistor Q1. Furthermore, since the sampling signals Smple1_pump to Smple4_pump are sequentially delayed signals, this embodiment of the present disclosure can eliminate the charge injection error of the switch and further improve analog-to-digital accuracy through the step-by-step delay processing of the sampling signals.

[0080] Please see Figure 5 , Figure 5 A schematic diagram of a boost module 30 according to an embodiment of the present disclosure is shown.

[0081] In one possible implementation, such as Figure 5As shown, the boost module 30120 includes a second NOT gate (NOT2), a third NOT gate (NOT3), a fourth NOT gate (NOT4), a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, and a ninth transistor Q9, wherein...

[0082] The input terminal of the second NOT gate NOT2 is used to input each initial sampling signal Sample (such as initial sampling signals Smple1 to Smple4). The output terminal of the second NOT gate NOT2 is connected to the gate of the sixth transistor Q6 and the input terminal of the third NOT gate NOT3. The power supply terminal of the second NOT gate NOT2 is connected to the power supply voltage VDD.

[0083] The source of the sixth transistor Q6, the source of the ninth transistor Q9, the ground terminal of the second NOT gate NOT2, the third NOT gate NOT3, and the fourth NOT gate NOT4 are all grounded.

[0084] The drain of the sixth transistor Q6 is connected to the source of the seventh transistor Q7 and the gate of the eighth transistor Q8.

[0085] The gate of the seventh transistor Q7 is connected to the source of the eighth transistor Q8, the input of the fourth NOT gate, and the drain of the ninth transistor Q9. The drain of the seventh transistor Q7 is connected to the drain of the eighth transistor Q8 and the power supply terminal of the fourth NOT gate, for use in connecting to the second power supply voltage VDD2 (e.g., the boosted power supply voltage VDD_pump output by charge pump 20).

[0086] The output of the third NOT gate (NOT3) is connected to the gate of the ninth transistor (Q9), and the power supply terminal of the third NOT gate (NOT3) is connected to the power supply voltage (VDD).

[0087] The output of the fourth NOT gate NOT4 is used to output the boosted sampling signals Smple1_pump to Smple4_pump.

[0088] Of course, the above description of the boost module 30 is exemplary and should not be regarded as a limitation on the embodiments of this disclosure. In other embodiments, those skilled in the art can adopt other methods to implement the boost module 30 according to actual conditions and needs.

[0089] In one possible implementation, the sixth transistor Q6 and the ninth transistor Q9 are NMOS transistors, and the seventh transistor Q7 and the eighth transistor Q8 are PMOS transistors.

[0090] Please see Figure 6 , Figure 6A schematic diagram of a charge pump 20 according to an embodiment of the present disclosure is shown.

[0091] In one possible implementation, such as Figure 6 As shown, the charge pump 20 may include a zeroth inverter NOT0, a first inverter NOT1, a zeroth PMOS transistor PM0, a first PMOS transistor PM1, a zeroth NMOS transistor NM0, a first NMOS transistor NM1, a second NMOS transistor NM2, a third capacitor C3, and a first diode D1, wherein,

[0092] The input terminals of the zeroth inverter NOT0 and the first inverter NOT1 are used to receive the (N+1)th initial sampling signal SmpleN+1. The power supply terminals of the zeroth inverter NOT0 and the first inverter NOT1 are used to receive the power supply voltage VDD. The ground terminal of the first inverter NOT1 is grounded.

[0093] The output terminal of the zeroth inverter NOT0 is connected to the gate of the first PMOS transistor PM1, and the ground terminal of the zeroth inverter NOT0 is connected to the first terminal of the third capacitor C3, the drain of the zeroth NMOS transistor NM0, and the source of the first NMOS transistor NM1.

[0094] The output of the first inverter NOT1 is connected to the gate of the zeroth NMOS transistor NM0, and is used to output the inverted signal Smpleb of the (N+1)th initial sampling signal SmpleN+1. The source of the zeroth NMOS transistor NM0 is connected to the positive terminal of the first diode D1 and grounded.

[0095] The cathode of the first diode D1 is connected to the source of the first PMOS transistor PM1, the source of the zeroth PMOS transistor PM0, and the second terminal of the third capacitor C3, for outputting the boosted power supply voltage VDD_pump.

[0096] The drain of the zeroth PMOS transistor PM0 is used to receive the power supply voltage VDD, and the gate of the zeroth PMOS transistor PM0 is connected to the gate of the first NMOS transistor NM1, the source of the second NMOS transistor NM2, and the drain of the first PMOS transistor PM1.

[0097] The drain of the second NMOS transistor NM2 is grounded, and the gate of the second NMOS transistor NM2 is used to receive the inverse signal Sampleb of the (N+1)th initial sample signal.

[0098] The drain of the first NMOS transistor NM1 is used to receive the first reference voltage VCM.

[0099] For example, such as Figure 6 As shown, when charge pump 20 is working, if the (N+1)th initial sampling signal SmpleN+1 is low, the zeroth NMOS transistor NM0 is turned on, the first NMOS transistor NM1 is turned off, the second NMOS transistor NM2 is turned on, the first PMOS transistor PM1 is turned off, the zeroth PMOS transistor PM0 is turned on, the first terminal (point a) of the third capacitor C3 is ground, and the second terminal (point b) of the third capacitor C3 is VDD; if the (N+1)th initial sampling signal SmpleN+1 is high, the zeroth NMOS transistor NM0 is turned off, the first NMOS transistor NM1 is turned on, the second NMOS transistor NM2 is turned off, the first PMOS transistor PM1 is turned on, and the zeroth PMOS transistor... When PM0 is disconnected, the first terminal (point a) of the third capacitor C3 is the first reference voltage VCM, and the voltage at the second terminal (point b) of the third capacitor C3 is the sum of the first reference voltage VCM and the power supply voltage (VCM+VDD). This achieves a voltage boost in the sampling phase, and the boosting magnitude is the first reference voltage VCM. Since the first reference voltage VCM is a voltage division of the power supply voltage, that is, the first reference voltage VCM is less than the power supply voltage, the boosted power supply voltage is less than twice the power supply voltage. Thus, in this embodiment of the present disclosure, the charge pump 20 can achieve a voltage boost while avoiding the power supply voltage from exceeding twice the power supply voltage, thereby preventing the zeroth transistor Q0 and the first transistor Q1 from being destroyed, without the need to add other circuits, thus reducing costs.

[0100] For example, such as Figure 6 As shown, in this embodiment of the present disclosure, a first diode D1 is provided between VDD_pump and ground to prevent the pumped voltage from being too high as VDD and to appropriately limit the voltage.

[0101] According to one aspect of this disclosure, a successive approximation analog-to-digital converter is provided, the successive approximation analog-to-digital converter including the aforementioned analog-to-digital conversion device.

[0102] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the successive approximation analog-to-digital converter described above.

[0103] For example, electronic devices may include terminals, which in one example are also called user equipment (UE), mobile station (MS), mobile terminal (MT), etc., and are devices that provide voice and / or data connectivity to users, such as handheld devices with wireless connectivity, in-vehicle devices, etc. Currently, some examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc.

[0104] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital converter, characterized in that, The device is used to perform analog-to-digital conversion on the input voltage to obtain a converted voltage. The device includes multiple sampling switches, multiple sampling capacitors, a successive approximation logic SAR control module, a charge pump, a boost module, and N cascaded comparator units. Each comparison unit includes a zeroth transistor, a first transistor, and a comparator. The drain of each zeroth transistor and the drain of each first transistor are used to receive a first reference voltage. The source of each zeroth transistor is connected to the negative input terminal of the corresponding comparator, and the source of each first transistor is connected to the positive input terminal of the corresponding comparator. The output terminal of the comparator in the Mth stage comparison unit is coupled to the positive input terminal of the comparator in the (M+1)th stage comparison unit. The ground terminal of the comparator in the Mth stage comparison unit is coupled to the negative input terminal of the comparator in the (M+1)th stage comparison unit, where M+1≤N and M and N are both integers. The gates of each zeroth transistor and each first transistor are used to receive sampling signals. The zeroth transistor and the first transistor in the same comparison unit receive the same sampling signal, which is used to control the conduction state of the corresponding zeroth transistor and the first transistor. The charge pump is used to boost the power supply voltage based on the (N+1)th initial sampling signal to obtain the boosted power supply voltage, wherein the (N+1)th initial sampling signal has the same frequency but different phase. The boost module receives the boosted power supply voltage and boosts the N+1 initial sampling signals to obtain N+1 sampling signals. The first N sampling signals are applied sequentially to N cascaded comparator units according to their phase delay order. The first terminal of each sampling capacitor is connected to the non-inverting input of the comparator in the first-stage comparison unit, and the second terminal of each sampling capacitor is connected to a corresponding sampling switch. The sampling switch is used to connect any one of the input voltage, the second reference voltage, or the ground voltage to the second terminal of the corresponding sampling capacitor. Specifically, when the (N+1)th sampling signal is high, the input voltage is connected to the second terminal of each sampling capacitor. The output of the comparator in the Nth-level comparison unit is connected to the SAR control module. The SAR control module is used to control the connection state of each switch and obtain the conversion voltage based on the comparison result of the comparator in the Nth-level comparison unit.

2. The apparatus according to claim 1, characterized in that, A first capacitor is provided between the output terminal of the comparator in the M-th stage comparator unit and the positive input terminal of the comparator in the M+1-th stage comparator unit, and a second capacitor is provided between the ground terminal of the comparator in the M-th stage comparator unit and the negative input terminal of the comparator in the M+1-th stage comparator unit.

3. The apparatus according to claim 1, characterized in that, The charge pump includes a zeroth inverter, a first inverter, a zeroth PMOS transistor, a first PMOS transistor, a zeroth NMOS transistor, a first NMOS transistor, a second NMOS transistor, a third capacitor, and a first diode, wherein... The input terminals of the zeroth inverter and the first inverter are used to receive the (N+1)th initial sampling signal. The power supply terminals of the zeroth inverter and the first inverter are used to receive the power supply voltage. The ground terminal of the first inverter is grounded. The output terminal of the zeroth inverter is connected to the gate of the first PMOS transistor, and the ground terminal of the zeroth inverter is connected to the first terminal of the third capacitor, the drain of the zeroth NMOS transistor, and the source of the first NMOS transistor. The output of the first inverter is connected to the gate of the zeroth NMOS transistor, and the source of the zeroth NMOS transistor is connected to the anode of the first diode and grounded. The cathode of the first diode is connected to the source of the first PMOS transistor, the source of the zeroth PMOS transistor, and the second terminal of the third capacitor, for outputting the boosted power supply voltage. The drain of the zeroth PMOS transistor is used to receive the power supply voltage, and the gate of the zeroth PMOS transistor is connected to the gate of the first NMOS transistor, the source of the second NMOS transistor, and the drain of the first PMOS transistor. The drain of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is used to receive the opposite signal of the (N+1)th initial sampled signal. The drain of the first NMOS transistor is used to receive the first reference voltage.

4. The apparatus according to claim 1, characterized in that, The device further includes: The delay module is used to delay the first initial sampling signal multiple times to obtain various initial sampling signals.

5. The apparatus according to claim 1, characterized in that, The device further includes a third transistor, wherein... The source of the third transistor is used to receive the input voltage, the gate of the third transistor is used to receive the (N+1)th sampled signal, and the drain of the third transistor is connected to each sampling switch.

6. The apparatus according to claim 1, characterized in that, The boost module includes a second NOT gate, a third NOT gate, a fourth NOT gate, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, wherein... The input terminal of the second NOT gate is used to input the initial sampling signal, the output terminal of the second NOT gate is connected to the gate of the sixth transistor and the input terminal of the third NOT gate, and the power supply terminal of the second NOT gate is connected to the power supply voltage. The source of the sixth transistor, the source of the ninth transistor, the ground terminal of the second NOT gate, the third NOT gate, and the fourth NOT gate are all grounded. The drain of the sixth transistor is connected to the source of the seventh transistor and the gate of the eighth transistor. The gate of the seventh transistor is connected to the source of the eighth transistor, the input of the fourth NOT gate, and the drain of the ninth transistor. The drain of the seventh transistor is connected to the drain of the eighth transistor and the power supply terminal of the fourth NOT gate, for connecting to a second power supply voltage. The output terminal of the third NOT gate is connected to the gate of the ninth transistor, and the power supply terminal of the third NOT gate is connected to the power supply voltage. The output of the fourth NOT gate is used to output the boosted sampled signal.

7. The apparatus according to claim 6, characterized in that, The sixth and ninth transistors are NMOS transistors, and the seventh and eighth transistors are PMOS transistors.

8. The apparatus according to claim 1, characterized in that, The device includes N+1 boost modules, the power supply terminal of each boost module is connected to the output terminal of the charge pump to receive the boosted power supply voltage; the input terminal of each boost module is used to receive each initial sampling signal, and the output terminal of each boost module is used to output the corresponding sampling signal.

9. A successive approximation analog-to-digital converter, characterized in that, The successive approximation analog-to-digital converter includes the analog-to-digital conversion device according to any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the successive approximation analog-to-digital converter as described in claim 9.

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