Decision feedback equalizer and related methods

Abstract

This invention provides a decision feedback equalizer (DFE) and related methods, wherein the DFE includes a combinational circuit and a feedback filter. The combinational circuit combines an input signal and at least one feedback signal to generate an equalized signal. The feedback filter generates at least one feedback signal based on the equalized signal. The feedback filter includes a controllable delay circuit for receiving an output signal derived from the equalized signal and applying at least one delay to generate at least one delayed signal, wherein the at least one feedback signal is derived from the at least one delayed signal. The proposed DFE and related methods can eliminate the effects of post-marking, thus maintaining optimal DFE performance regardless of clock edge position.

Description

Technical Field

[0001] This invention relates to data communication, and more specifically, to a decision-feedback equalizer (DFE) and related methods using a feedback filter with a controllable delay circuit. Background Technology

[0002] In high-speed data communication systems, filtering and equalization schemes are commonly used. Detecting received signals in data communication systems is challenging due to various factors such as noise, crosstalk, and inter-symbol interference (ISI). A typical decision-feedback equalizer (DFE) at the receiver end can eliminate post-cursor ISI by using one or more past data bits. A typical DFE requires clock and data recovery (CDR) to place the clock edge at the data center location for optimal DFE performance. If the clock edge position when the slicer performs data decision operations on the data signal is not at the data center location, DFE performance will degrade. Furthermore, receiver (RX) eye diagram scanning provides a mechanism for measuring and visualizing the RX eye margin after equalization. However, RX eye diagram scanning requires changing the clock edge position to find the optimal data center location. Since DFE performance depends on the clock edge position, it is difficult for a typical DFE to perform RX eye diagram scanning and maintain optimal DFE performance. Therefore, a novel clockless DFE architecture is needed that can maintain optimal performance without considering the location of the clock edge. Summary of the Invention

[0003] One object of the present invention is to provide a decision feedback equalizer (DFE) using a feedback filter with a controllable delay circuit and a related method to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a decision feedback equalizer (DFE), the DFE including a combination circuit and a feedback filter. The combination circuit is used to combine an input signal and at least one feedback signal to generate an equalized signal. The feedback filter is used to generate at least one feedback signal based on the equalized signal. The feedback filter includes a controllable delay circuit for receiving an output signal derived from the equalized signal and applying at least one delay amount to generate at least one delayed signal, wherein the at least one feedback signal is derived from the at least one delayed signal.

[0005] Another embodiment of the present invention provides a decision feedback equalization method, comprising: combining an input signal and at least one feedback signal to generate an equalization signal; and generating at least one feedback signal based on the equalization signal. Generating at least one feedback signal based on the equalization signal includes, in response to receiving an output signal derived from the equalization signal, applying at least one delay amount via a controllable delay circuit to generate at least one delay signal, wherein the at least one feedback signal is derived from the at least one delay signal.

[0006] The DFE and related methods proposed in this invention can eliminate the effect of the post-mark, so that the best DFE performance can still be maintained without considering the position of the clock edge.

[0007] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating a first clock-less decision-feedback equalizer (DFE) according to an embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram illustrating the impulse response of a channel according to an embodiment of the present invention.

[0010] Figure 3 This is an example in having Figure 2 The diagram shows the waveform generated by the channel transmission mode "0010" of the impulse response.

[0011] Figure 4 This is an example in having Figure 2 The diagram shows the waveform generated by the channel transmission mode "0110" for the impulse response.

[0012] Figure 5 This is an example in having Figure 2 The diagram shows the waveform generated by the channel transmission mode "1010" for the impulse response shown.

[0013] Figure 6 yes Figure 1 The timing diagrams for different signals in a clockless DFE are shown.

[0014] Figure 7 This is a circuit diagram illustrating a differential circuit design for combining an input signal and two feedback signals according to an embodiment of the present invention.

[0015] Figure 8This is a schematic diagram illustrating a second clockless DFE according to an embodiment of the present invention.

[0016] Figure 9 This is a schematic diagram illustrating the use of the proposed clockless DFE half-rate receiver according to an embodiment of the present invention.

[0017] Figure 10 This is a schematic diagram illustrating the use of the proposed clockless DFE quarter-rate receiver according to an embodiment of the present invention. Detailed Implementation

[0018] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components by differences in name, but rather by differences in function. The term "comprising" throughout the specification and subsequent claims is an open-ended term and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if the text describes a first device electrically connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0019] Figure 1 This is a schematic diagram illustrating a first clock-less decision-feedback equalizer (DFE) according to an embodiment of the present invention. The clock-less DFE 100 can be part of a receiver in a data communication system. For example, the data communication system can be any source-synchronous system, such as a double data rate (DDR) memory system. The clock-less DFE 100 is configured to equalize the input signal DQ_INB received from a preceding stage (e.g., receiver analog front-end circuitry 10) to generate an output signal D. OUT And output it to the next level (e.g., one or more limiters, not in...). Figure 1(Shown in the diagram). The receiver analog front-end (RX AFE) circuit 10 compares the data signal DQ with a reference voltage VREF to generate the input signal DQ_INB. For example, the data signal DQ is provided by the transmitter of a source-synchronous system (e.g., a DDR memory system). The clockless DFE 100 includes a combinational circuit 102 and a feedback filter 104. The clockless DFE 100 can employ an n-tap (n≥2) DFE architecture. For simplicity, the clockless DFE 100 is shown as a 2-tap DFE. Therefore, the combinational circuit 102 acts as an adder to combine the input signal DQ_INB with two feedback signals FB_1 and FB_2 to generate the equalized signal DQ_SUM. The feedback filter 104 is used to generate the feedback signals FB_1 and FB_2 based on the equalized signal DQ_SUM. If the channel causes a post-cursor, the feedback signals FB_1 and FB_2 are intended to act as negative post-cursors to eliminate the post-cursor. Specifically, the clockless DFE 100 can negate the effect of the post-marking through the feedback filter 104.

[0020] In this embodiment, the equalization signal DQ_SUM output from the combinational circuit 102 is directly fed to the feedback filter 104 without being processed by any clock-driven limiter (i.e., clock-driven decision circuit), so that the clockless DFE 100 does not suffer from the DFE performance degradation suffered by typical DFEs (which require placing the clock edge at the data center location for optimal DFE performance). Since the clockless DFE 100 does not require a clock for data sampling, the clock-free DFE 100 can perform RX eye diagram scanning without suffering from the DFE performance degradation caused by changes in clock position.

[0021] In this embodiment, feedback signals FB_1 and FB_2 are generated by a controllable delay circuit 106. The controllable delay circuit 106 is used to receive the output signal D. OUT Multiple delay values ​​are applied to generate multiple delayed signals DL_1 and DL_2, where each delay value is adjustable. Feedback signal FB_1 is derived from delayed signal DL_1, and feedback signal FB_2 is derived from delayed signal DL_2. Figure 1 As shown, the controllable delay circuit 106 can be implemented by multiple digitally controlled delay lines 108 and 110 connected in series. The digitally controlled delay line (DCDL) 108 is used to apply the delay amount dT1 to the output signal D. OUTThis generates a delayed signal DL_1, from which the feedback signal FB_1 can be derived. DCDL 110 is used to apply a delay amount dT2 to the delayed signal DL_1 (which is equivalent to applying a delay amount dT1+dT2 to the output signal D). OUT The controllable delay circuit 106 generates a delayed signal DL_2, from which the feedback signal FB_2 can be derived. Therefore, the operation of the controllable delay circuit 106 is equivalent to adjusting the output signal D. OUT Apply a delay TD = dT1 to generate a delayed signal DL_1, and adjust the output signal D. OUT Apply another delay, TD = dT1 + dT2, to generate the delayed signal DL_2.

[0022] When the input signal DQ_INB is a differential signal, the feedback filter 104 also includes a differential-to-single-ended converter (labeled "D2S") 112, used to convert the equalized signal DQ_SUM into a single-ended signal as the output signal D. OUT In another case where the input signal DQ_INB is a single-ended signal, the feedback filter 104 can be modified to omit the differential-to-single-ended converter 112, so that the equalized signal DQ_SUM is directly used as the output signal D. OUT Simply put, the output signal D OUT It is derived from the equalization signal DQ_SUM and used to generate feedback signals FB_1 and FB_2 to eliminate post-cursor ISI.

[0023] The delayed signal DL_1 is fed back to the combinational circuit 102 via multiplexer (MUX) 114 and multiplier 118, or via inverter 116, multiplexer 114, and multiplier 118. Specifically, multiplexer 114 can select the delayed signal DL_1 as its multiplexer output signal DL_1P5 (i.e., DL_1P5 = DL_1) or select the inverted signal of the delayed signal DL_1 as its multiplexer output signal DL_1P5 (i.e., ...). The actual equalization requirement of the channel depends on the channel's actual equalization requirements.

[0024] The delayed signal DL_2 is fed back to the combinational circuit 102 via multiplexer (MUX) 120 and multiplier 124, or via inverter 122, multiplexer 120, and multiplier 124. Specifically, multiplexer 120 can select the delayed signal DL_2 as its multiplexer output signal DL_2P5 (i.e., DL_2P5 = DL_2) or select the inverted signal of the delayed signal DL_2 as its multiplexer output signal DL_2P5 (i.e., ...). The actual equalization requirement of the channel depends on the channel's actual equalization requirements.

[0025] When the input signal DQ_INB is a differential signal, the feedback filter 104 also includes a single-ended to differential converter (labeled "S2D") 126 for converting the multiplexer output signal DL_1P5 on one feedback path into differential form, and another single-ended to differential converter (labeled "S2D") 128 for converting the multiplexer output signal DL_2P5 on another feedback path into differential form. In another case where the input signal DQ_INB is a single-ended signal, the feedback filter 104 can be modified to omit both single-ended to differential converters 126 and 128.

[0026] Multiplier 118 multiplies the multiplexer output signal DL_1P5 by the tap coefficient T1 to generate a feedback signal FB_1, which is then output to the combinational circuit 102, i.e., FB1 = T1 × DL_1P5. The value of the tap coefficient T1 depends on the effect of the negativeed post-mark. Multiplier 124 multiplies the multiplexer output signal DL_2P5 by the tap coefficient T2 to generate a feedback signal FB_2, which is then output to the combinational circuit 102, i.e., FB2 = T2 × DL_2P5. The value of the tap coefficient T2 depends on the effect of the negativeed post-mark.

[0027] In one exemplary implementation, the clockless DFE 100 can be configured to equalize the input signal DQ_INB to improve eye height. That is, by appropriately setting the tap coefficients T1 and T2, the clockless DFE 100 can eliminate the post-marked ISI affecting eye height in the eye diagram. In another exemplary implementation, the clockless DFE 100 can be configured to equalize the input signal DQ_INB to improve eye width. In other words, by appropriately setting the tap coefficients T1 and T2, the clockless DFE 100 can eliminate the post-marked ISI affecting eye width in the eye diagram. Simply put, the settings of the tap coefficients T1 and T2 used by the clockless DFE 100 can be adjusted based on practical design considerations.

[0028] Figure 2 This is a schematic diagram illustrating the impulse response of a channel according to an embodiment of the present invention. The voltage at time T0 is represented by h0. Time T0 can be considered as the sampling time for sending / receiving one data bit "0" or "1" to / from the channel. 0.5 The voltage is represented by h. 0.5 It means that T 0.5 = T0 + 0.5UI (unit interval). In a data communication system, one UI is a bit cycle of one data bit. Time T1.5 The voltage is determined by h 1.5 It means that T 1.5 =T0 + 1.5UI. Time T 2.5 The voltage is determined by h 2.5 It means that T 2.5 =T0 + 2.5UI. Generally, the data sampling location (or data sampling time) is located at T. n The data transition location is at T. n+0.5 , where n is a positive integer. Figure 3 This is an example in having Figure 2 The diagram shows the waveform generated by the channel transmission mode "0010" in the pulse response. Preferably, the transmitted data is sampled at the data center location. Therefore, waveform 302 is sampled at time T0, where the voltage h0 has its maximum level at time T0. In other words, Figure 3 The voltage h0 shown is sampled for subsequent bit decision at the limiter. Figure 4 This is an example in having Figure 2 The diagram shows the waveform generated by the channel transmission mode "0110" for the impulse response. The waveform 404, representing the later data bit "1", was sampled at time T0, where the voltage h0 has its maximum level. In other words, Figure 4 The voltage h0 shown is sampled for subsequent bit decision at the limiter. Regarding the waveform 404 of the subsequent data bit "1", at time T... 0.5 This corresponds to the data transition position. However, when the preceding data bit "1" is transmitted through the channel, the resulting waveform 402 is at the data transition position T. 0.5 The location causes a post-mark (i.e., voltage h) 1.5 This affects the width of the eyes. Figure 5 This is an example in having Figure 2 The diagram shows the waveform generated by the channel transmission mode "1010" for the impulse response. The waveform 504, representing the subsequent data bit "1", was sampled at time T0, where the voltage h0 has its maximum level. In other words, Figure 5 The voltage h0 shown is sampled for subsequent bit decision at the limiter. Regarding the waveform 504 of the subsequent data bit "1", at time T... 0.5 This corresponds to the data transition position. However, when the previous data bit "1" is transmitted through the channel, the resulting waveform 502 is at the data transition position T. 0.5 The location causes a post-mark (i.e., voltage h) 2.5 This affects eye width. Eye diagram performance (especially eye width) is affected by residual post-labeled ISI (h). 1.5 and h 2.5The clockless DFE 100 can eliminate the post-marker ISI (h) and reduce it. 1.5 and h 2.5 This can optimize eye diagram performance (especially eye width). For example, the tap factor T1 can be set to -h. 1.5 Set the tap coefficient T2 to -h 2.5 In addition, such as Figure 1 As shown, the delay amount dT1 is configured by the delay code C1 assigned to DCDL 108, and the delay amount dT2 is configured by the delay code C2 assigned to DCDL 110. Therefore, the delay codes C1 and C2 can be appropriately set such that the delay applied to the output signal D... OUT A delay TD = dT1 equals 1.5UI and is applied to the output signal D OUT The other delay is TD = dT1 + dT2 = 1.5UI + 1UI, which equals 2.5UI.

[0029] Alternatively, eye diagram performance (particularly the eye height) can be degraded due to residual back-marked ISIs (h1 and h2). The clockless DFE 100 can remove the back-marked ISIs (h1 and h2) to optimize eye diagram performance (particularly the eye height). For example, tap factor T1 can be set to -h1, and tap factor T2 can be set to -h2. Furthermore, as... Figure 1 As shown, the delay amount dT1 is configured by the delay code C1 assigned to DCDL108, and the delay amount dT2 is configured by the delay code C2 assigned to DCDL110. Therefore, the delay codes C1 and C2 can be appropriately set such that the delay applied to the output signal D... OUT A delay TD = dT1 equals 1UI, and the applied signal D is made equal to the delay TD = dT1. OUT Another delay, TD = dT1 + dT2 = 1UI + 1UI, equals 2UI. This alternative DFE design also falls within the scope of this invention.

[0030] Figure 6 yes Figure 1 The timing diagrams for different signals in the clockless DFE 100 are shown. Assume dT1 is set by 1.5UI and dT2 by 1UI. The multiplexer output signal DL_1P5 can be considered as a delayed signal generated by applying a 1.5UI delay to the input signal DQ_INB. The multiplexer output signal DL_2P5 can be considered as a delayed signal generated by applying a 2.5UI delay to the input signal DQ_INB. The feedback signal FB_1 is generated by applying a tap coefficient T1 (e.g., -h...). 1.5 The feedback signal FB_2 is generated by applying the tap coefficient T2 (e.g., -h) to the multiplexer output signal DL_1P5. 2.5The equalization signal DQ_SUM is generated by adding the feedback signals FB_1 and FB_2 to the input signal DQ_INB, and can be expressed by the following equation.

[0031] DQ_SUM=DQ_INB+FB_1+FB_2=DQ_INB+T1×DL_1P5+T2×DL_2P5 (1)

[0032] When the input signal DQ_INB is a differential signal, the feedback signals FB_1 and FB_2, as well as the equalization signal DQ_SUM, are differential signals. Equation (1) above can be obtained by using... Figure 7 The circuit design shown is used to implement this, where the input signal DQ_INB is a differential signal composed of positive signal INP and negative signal INN, the feedback signal FB_1 is a differential signal composed of positive signal d1p and negative signal d1n, the feedback signal FB_2 is a differential signal composed of positive signal d2p and negative signal d2n, and the equalization signal DQ_SUM is a differential signal composed of positive signal Sum and negative signal Sum_B.

[0033] The post-marking in the equalization signal DQ_SUM caused by the previous data bit "1" can be eliminated using feedback signals FB_1 and FB_2. The output signal D of the clockless DFE 100... OUT This can be derived from the equalization signal DQ_SUM. When there is no clock, the output signal D of DFE100 is... OUT When the data is subsequently sampled by at least one decision circuit (e.g., a limiter) based on the rising and falling edges of the timing signal DQSI, the correct data bits can be obtained since the post-mark ISI has been eliminated.

[0034] As described above, delay code C1 determines the delay amount dT1 of DCDL 108, and delay code C2 determines the delay amount dT2 of DCDL 110. In an example design, the delay line step size of DCDL 108 and 110 can be measured by a measurement circuit (not shown) in the receiver of a data communication system (e.g., a DDR memory system). For example, the delay line step size can be measured in units of UI, such as k*UI. Delay code C1 can be derived from a lookup table based on multiple parameters, such as the data rate (which determines the size of a UI) and the delay line step size (which determines an increase / decrease in delay amount for unit changes in the delay code), where the lookup table can be built based on simulation. Delay code C2 can be derived based on UI and the delay line step size (e.g., ... It should be noted that the delay dT1 provided by the DCDL 108 is not necessarily 1.5UI, as the feedback loop may include other components with inherent delays. According to experimental results, at a data rate of 8.533Gbps, eye width can still be improved when the delay dT1 is close to the ideal value (i.e., 1.5UI) within a tolerance range of +0.25UI to -0.25UI.

[0035] exist Figure 1 In the illustrated embodiment, the clockless DFE 100 employs an n-tap (n≥2) DFE architecture, such as a 2-tap DFE architecture. However, this is for illustrative purposes only and is not intended to limit the invention. In practice, the proposed clockless DFE can also be applied to a 1-tap DFE architecture.

[0036] Figure 8 This is a schematic diagram illustrating a second clockless DFE according to an embodiment of the present invention. The clockless DFE 800 can be part of a receiver in a data communication system. For example, the data communication system can be any source-synchronous system, such as a DDR memory system. The clockless DFE 800 is arranged to equalize the input signal DQ_INB received from the preceding stage (e.g., receiver analog front-end circuitry 10) to generate an output signal D. OUT And output it to the next level (e.g., one or more limiters, not in...). Figure 8 (As shown in the diagram). The clockless DFE 800 includes a combinational circuit 802 and a feedback filter 804. In this embodiment, the clockless DFE 800 employs a 1-tap DFE architecture. Therefore, the combinational circuit 802 acts as an adder to combine the input signal DQ_INB and a single feedback signal FB_1 to generate the equalization signal DQ_SUM. The feedback filter 804 is used to generate the feedback signal FB_1 based on the equalization signal DQ_SUM. Therefore, the controllable delay circuit 806 included in the feedback filter 804 includes only one DCDL 108. Specifically, the feedback filter 804 is achieved by omitting... Figure 1 The DCDL 110, inverter 122, multiplexer 120, single-ended to differential converter 128, and multiplier 124 shown are used to obtain the signal. When the input signal DQ_INB is a differential signal, the feedback filter 804 includes a differential to single-ended converter (labeled "D2S") 112 to convert the equalized signal DQ_SUM into a single-ended signal as the output signal D. OUTThe feedback filter 804 also includes a single-ended to differential converter (labeled "S2D") 126 for converting the multiplexer output signal DL_1P5 into differential form. In another case where the input signal DQ_INB is a single-ended signal, the feedback filter 804 can be modified to omit the differential to single-ended converter 112 and the single-ended to differential converter 126. Those skilled in the art, after reading the above description of the clockless DFE 100 with an n-tap DFE architecture, can easily understand the details of the clockless DFE 800 with a 1-tap DFE architecture; for brevity, further description is omitted here.

[0037] The proposed clockless DFE 100 / 800 can be part of a receiver in a data communication system. For example, the receiver can employ a full-rate architecture. However, this is for illustrative purposes only and is not intended to limit the invention. Figure 9 This is a schematic diagram illustrating a half-rate receiver using the proposed clockless DFE 100 / 800 according to an embodiment of the present invention. In addition to the proposed clockless DFE 100 / 800, the half-rate receiver 900 also includes two limiters 902 and 904, which operate based on two clock signals Clk0 and Clk180 having the same frequency but different phases of 0° and 180°. The decision outputs of limiters 902 and 904 are Data0 and Data180, respectively. 180 Parallel-to-serial conversion is performed at deserializer 906. Figure 10 This is a schematic diagram illustrating a quarter-rate receiver using the proposed clockless DFE 100 / 800 according to an embodiment of the present invention. In addition to the proposed clockless DFE 100 / 800, the quarter-rate receiver 1000 also includes four limiters 1002, 1004, 1006, and 1008, which operate according to four clock signals Clk0, Clk90, Clk180, and Clk270 having the same frequency but different phases of 0°, 90°, 180°, and 270°. The decision outputs Data0, Data... 90 Data 180 and Data 270 The parallel-to-serial conversion will be performed at the deserializer (not shown). In short, any receiver architecture that uses the proposed clockless DFE 100 / 800 to eliminate post-marked ISI falls within the scope of this invention.

[0038] Those skilled in the art will readily recognize that many modifications and variations can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the appended claims.

Claims

1. A decision feedback equalizer (DFE), comprising: Combinatorial circuitry for combining an input signal and at least one feedback signal to generate an equalized signal; as well as A feedback filter, configured to generate the at least one feedback signal based on the equalization signal, wherein the feedback filter comprises: A controllable delay circuit is configured to receive an output signal derived from the equalization signal and apply at least one delay amount to generate at least one delayed signal, wherein the at least one feedback signal is derived from the at least one delayed signal; At least one multiplier; At least one multiplexer; and At least one inverter, wherein the at least one delayed signal is fed back to the combinational circuit via the at least one multiplexer and the at least one multiplier, or via the at least one inverter, the at least one multiplexer and the at least one multiplier; Wherein, the at least one feedback signal includes only a single feedback signal, the at least one delay signal includes only a single delay signal, and the at least one delay amount includes only a single delay amount.

2. The DFE of claim 1, wherein, The controllable delay circuit includes: A single digitally controlled delay line is used to apply the single delay amount to the output signal to generate the single delayed signal from which the single feedback signal is derived.

3. The DFE of claim 2, wherein, The individual delay amount is configured by a delay code assigned to the individual digital control delay line, and the delay code is obtained from a lookup table.

4. A decision feedback equalizer (DFE), comprising: Combinatorial circuits are used to combine input signals and multiple feedback signals to generate a balanced signal. as well as A feedback filter, used to generate the plurality of feedback signals based on the equalization signal, wherein the feedback filter includes: A controllable delay circuit is used to receive an output signal derived from the equalization signal and apply multiple delay amounts to generate multiple delay signals, wherein the multiple feedback signals are derived from the multiple delay signals; The controllable delay circuit includes: Multiple digitally controlled delay lines, wherein the multiple digitally controlled delay lines are connected in series and include: A first digitally controlled delay line is arranged to apply a first delay amount to the output signal to generate a first delayed signal from which a first feedback signal is derived; and A second digitally controlled delay line is arranged to apply a second delay amount to the first delay signal to generate a second delay signal from which a second feedback signal is derived. The first delay amount and the second delay amount are configured by a first delay code and a second delay code assigned to the first digital control delay line and the second digital control delay line, respectively, wherein the second delay code is obtained based on the unit interval UI and the delay line step size.

5. The DFE of claim 4, wherein, The first delay code is obtained from the lookup table.

6. The DFE of claim 4, wherein, The first delay code and the second delay code are appropriately set such that the applied first delay amount and the second delay amount are 1UI respectively, or such that the applied first delay amount and the second delay amount are 1.5UI and 1UI respectively.

7. The DFE of claim 4, wherein the input signal is derived from the data signal of the source synchronization system.

8. The DFE of claim 7, wherein the source synchronization system is a double data rate (DDR) memory system.

9. The DFE of claim 4, wherein the feedback filter further comprises a plurality of multipliers for multiplying the plurality of delayed signals or the inverted signals of the plurality of delayed signals with tap coefficients to generate the plurality of feedback signals.

10. A decision feedback equilibrium method, comprising: Combine the input signal and at least one feedback signal to generate an equalized signal; as well as Generating the at least one feedback signal based on the equalization signal includes: In response to receiving an output signal derived from the equalization signal, at least one delay amount is applied through a controllable delay circuit to generate at least one delay signal, wherein the at least one feedback signal is derived from the at least one delay signal; Wherein, the at least one feedback signal is obtained by passing the at least one delayed signal through at least one multiplexer and at least one multiplier, or by passing the at least one inverter, at least one multiplexer and at least one multiplier; Wherein, the at least one feedback signal includes only a single feedback signal, the at least one delay signal includes only a single delay signal, and the at least one delay amount includes only a single delay amount.

11. The decision feedback equalization method of claim 10 wherein, The controllable delay circuit includes a single digitally controlled delay line; The step of applying the at least one delay amount to generate the at least one delayed signal includes: The single delay amount is applied to the output signal by the single digitally controlled delay line to generate the single delayed signal from which the single feedback signal is derived.

12. The decision feedback equilibrium method as described in claim 11, wherein, The individual delay amount is configured by a delay code assigned to the individual digital control delay line, the delay code being obtained from a lookup table.

13. A decision feedback equilibrium method, comprising: Combine the input signal and multiple feedback signals to generate an equalized signal; as well as The plurality of feedback signals are generated based on the equalization signal, including: In response to receiving an output signal derived from the equalization signal, a plurality of delay amounts are applied through a controllable delay circuit to generate a plurality of delay signals, wherein the plurality of feedback signals are derived from the plurality of delay signals; The controllable delay circuit includes: Multiple digitally controlled delay lines, wherein the multiple digitally controlled delay lines are connected in series and include a first digitally controlled delay line and a second digitally controlled delay line; and the step of applying the multiple delay amounts to generate the multiple delayed signals includes: The first delay amount is applied to the output signal by the first digitally controlled delay line to generate a first delayed signal from which the first feedback signal is derived; and The second delay amount is applied to the first delay signal by the second digitally controlled delay line to generate a second delay signal from which a second feedback signal is derived; The first delay amount and the second delay amount are configured by a first delay code and a second delay code assigned to the first digital control delay line and the second digital control delay line, respectively, wherein the second delay code is obtained based on the unit interval UI and the delay line step size.

14. The decision feedback equilibrium method as described in claim 13, wherein, The first delay code is obtained from the lookup table.

15. The decision feedback equilibrium method as described in claim 13, wherein, The first delay code and the second delay code are appropriately set such that the applied first delay amount and the second delay amount are 1UI respectively, or such that the applied first delay amount and the second delay amount are 1.5UI and 1UI respectively.

16. The decision feedback equilibrium method as described in claim 13, wherein, The input signal is derived from the data signal of the source synchronization system.

17. The decision feedback equilibrium method as described in claim 16, wherein, The source synchronization system is a DDR memory system.

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