A circuit board and method for establishing a clock source connection to a chip

Abstract

The embodiment of the application provides a circuit board and a method for establishing a clock source and a chip connection. It relates to the technical field of circuits. The clock source connected by the circuit board includes multiple types, and the circuit board is provided with a pair of clock source pins corresponding to each type of clock source. The circuit board further includes a pair of chip clock input pins connected with a chip clock input end, and the clock source pins are arranged around the chip clock input pins. A first positive electrode pin is connected with a second positive electrode pin through a first capacitor, and a first negative electrode pin is connected with a second negative electrode pin through a second capacitor. Without connecting multiple capacitors in series, the chip clock input end can be connected with the target clock source, the loss of the clock signal is reduced, and only one capacitor is arranged on the wiring between the two pins connected by the first capacitor and the wiring between the two pins connected by the second capacitor. The wiring spacing is easy to adjust, and the difficulty of impedance matching is reduced.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a circuit board and method for establishing a connection between a clock source and a chip. Background Technology

[0002] High-speed data chips often employ differential clocking. Currently, multiple clock inputs can be achieved by connecting a clock source to the chip via a circuit board. However, multiple clock inputs often require multiple capacitors to be connected in series. Since the differential inputs of chips on the circuit board have a differential impedance requirement of 100 ohms, this increases the difficulty of impedance matching. Furthermore, since the clock inputs of high-speed data chips are all above 100MHz, connecting two capacitors in series consecutively will increase signal loss. Summary of the Invention

[0003] In view of this, embodiments of this application provide a circuit board and method for establishing a connection between a clock source and a chip, aiming to reduce the number of series capacitors, reduce impedance matching difficulty, and reduce signal loss.

[0004] In a first aspect, embodiments of this application provide a circuit board for establishing a connection between a clock source and a chip. The clock sources connected to the circuit board include multiple types. The circuit board is provided with a pair of clock source pins for each type of clock source. The circuit board also includes a pair of chip clock input pins connected to the chip clock input terminal.

[0005] The clock source pin is positioned around the chip clock input pin;

[0006] The first positive pin of a pair of chip clock input pins is connected to the second positive pin of a pair of clock source pins corresponding to the target clock source through a first capacitor, and the first negative pin of a pair of chip clock input pins is connected to the second negative pin of a pair of clock source pins corresponding to the target clock source through a second capacitor. The target clock source is one of the clock sources connected to the circuit board.

[0007] Optionally, the trace length between the first positive pin and the second positive pin is equal to the trace length between the first negative pin and the second negative pin.

[0008] Optionally, the differential impedance generated by the spacing between the traces between the first positive pin and the second positive pin and the traces between the first negative pin and the second negative pin is 100 ohms.

[0009] Optionally, the clock source includes a crystal oscillator, a clock signal transmitted from a circuit board other than the circuit board, and a clock signal generator.

[0010] Optionally, a first pair of clock source pins is provided on the circuit board on the first side of the connection between the first positive pin and the first negative pin, a second pair of clock source pins is provided on the second side of the connection near the first end of the connection, and a third pair of clock source pins is provided on the second side of the connection near the second end of the connection.

[0011] Optionally, the first pair of clock source pins includes a second pin and a third pin, the second pair of clock source pins includes a fourth pin and a fifth pin, and the third pair of clock source pins includes a sixth pin and a first pin;

[0012] The connection line between the second pin and the sixth pin passes through the first positive pin and is perpendicular to the connection line;

[0013] The connection line between the third pin and the fifth pin passes through the first negative pin and is perpendicular to the connection line.

[0014] The fourth pin is disposed on the extension line of the connection line near the first end, and the first pin is disposed on the extension line of the connection line near the second end.

[0015] Optionally, if the clock source corresponding to the first pair of clock source pins is the target clock source, then the second pin is the second positive pin, and the third pin is the second negative pin;

[0016] or,

[0017] If the clock source corresponding to the second pair of clock source pins is the target clock source, then the fifth pin is the second positive pin, and the fourth pin is the second negative pin;

[0018] or,

[0019] If the clock source corresponding to the third pair of clock source pins is the target clock source, then the first pin is the second positive pin, and the sixth pin is the second negative pin.

[0020] Optionally, the first capacitor is 0.1uf / 50V and the second capacitor is 0.1uf / 50V.

[0021] Secondly, this application also provides a method for establishing a circuit board for connecting a clock source and a chip, which is applied to the circuit board for establishing a clock source and a chip as described above.

[0022] The second pin is connected to the first terminal of the first capacitor, the first positive pin is connected to the second terminal of the first capacitor, the third pin is connected to the first terminal of the second capacitor, the first negative pin is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal of the clock source corresponding to the first pair of clock source pins.

[0023] or,

[0024] The fifth pin is connected to the first terminal of the first capacitor, the first positive pin is connected to the second terminal of the first capacitor, the fourth pin is connected to the first terminal of the second capacitor, the first negative pin is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal from the clock source corresponding to the second pair of clock source pins.

[0025] or,

[0026] The first pin is connected to the first terminal of the first capacitor, the first positive pin is connected to the second terminal of the first capacitor, the sixth pin is connected to the first terminal of the second capacitor, the first negative pin is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal from the clock source corresponding to the third pair of clock source pins.

[0027] Optionally, the board material is removed from the circuit board so that the trace length between the two pins connected to the first capacitor is the same as the trace length between the two pins connected to the second flashlight.

[0028] This application provides a circuit board and method for establishing a connection between a clock source and a chip. The circuit board connects to various clock sources, with a pair of clock source pins for each source. The circuit board also includes a pair of chip clock input pins connected to the chip's clock input terminal, with the clock source pins positioned around these input pins. A first positive pin is connected to a second positive pin via a first capacitor, and a first negative pin is connected to a second negative pin via a second capacitor. This eliminates the need for multiple capacitors in series, enabling connection between the chip's clock input terminal and the target clock source, reducing clock signal loss. Furthermore, only one capacitor is placed on each trace between the two pins connected by the first capacitor and the two pins connected by the second capacitor, making trace spacing easy to adjust and reducing impedance matching difficulties. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram illustrating the connection between a multi-channel clock source and a chip, provided in an embodiment of this application;

[0031] Figure 2 A schematic diagram of a circuit board for a clock source pin and a chip clock input pin provided for an embodiment of this application;

[0032] Figure 3 This application provides a schematic diagram illustrating the association between the first pair of clock source pins and the chip clock input pins in an embodiment.

[0033] Figure 4 This application provides a schematic diagram illustrating the association between the second pair of clock source pins and the chip clock input pins in an embodiment.

[0034] Figure 5 This application provides a schematic diagram illustrating the association between a third pair of clock source pins and chip clock input pins in an embodiment of the present application.

[0035] Explanation of Figure Numbers

[0036] 1-First pin; 2-Second pin; 3-Third pin; 4-Fourth pin; 5-Fifth pin; 6-Sixth pin; 7-First positive pin; 8-First negative pin. Detailed Implementation

[0037] Currently, high-speed data chips often use differential clocks. In some complex applications, the chip may need to access multiple clocks. For example, see... Figure 1 The diagram shows a multi-channel clock source connected to a chip. Clock source 2 and clock source 3 have an additional capacitor connected in series compared to clock source 1. Since the differential input of the chip on the board requires a differential impedance of 100 ohms, this increases the difficulty of impedance matching. Furthermore, high-speed data chips typically have clock inputs above 100MHz, and connecting two capacitors in series would increase signal loss.

[0038] Based on the above problems, this application proposes a circuit board for establishing a connection between a clock source and a chip. When the chip needs to be connected to three clock sources, the circuit board is configured with three pairs of clock source pins corresponding to the three clock sources, and the circuit board is configured with a pair of chip clock input pins corresponding to the chip clock input terminal.

[0039] Three pairs of clock source pins are positioned around a pair of chip clock input pins. When the chip requires a clock signal from a specific clock source (the target clock source), the first positive pin of the chip's clock input pins can be connected to the second positive pin of the corresponding pair of clock source pins using a first capacitor. Similarly, the first negative pin of the pair of chip clock input pins can be connected to the second negative pin of the corresponding pair of clock source pins using a second capacitor. In other words, the first positive pin is connected to the second positive pin via the first capacitor, and the first negative pin is connected to the second negative pin via the second capacitor. This eliminates the need for multiple capacitors in series, allowing connection between the chip's clock input and the target clock source, reducing clock signal loss. Furthermore, only one capacitor is used on the traces between the two pins connected by the first capacitor and the traces between the two pins connected by the second capacitor, making trace spacing easy to adjust and reducing impedance matching difficulties.

[0040] Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] Figure 2 A schematic diagram of a circuit board for a clock source pin and a chip clock input pin provided in an embodiment of this application is shown below. Figure 2 A circuit board for establishing a connection between a clock source and a chip, comprising:

[0042] The circuit board is connected to various clock sources, and the circuit board is provided with a pair of clock source pins for each clock source. The circuit board also includes a pair of chip clock input pins connected to the chip clock input terminal.

[0043] For example, the clock source may include a local clock source and an external clock source. The local clock source may be a local oscillator, and the external clock source may be a clock signal sent by a circuit board other than the circuit board or a clock signal generator.

[0044] By connecting the chip's clock input pin to a pair of clock source pins corresponding to the target clock source, the clock signal of the target clock source is sent to the chip.

[0045] The clock source pin is positioned around the chip's clock input pin.

[0046] Turn the clock source pin (to Figure 2 Taking pins numbered 1-6 as an example, pins 2 and 3 can be a pair of clock source pins, pins 4 and 5 can be a pair of clock source pins, and pins 6 and 1 can be a pair of clock source pins. These are set on the chip's clock input pins (using...). Figure 2 Taking pins numbered 7 and 8 as an example, shorten the distance around them to facilitate the connection of each clock source pin to the chip's clock input pin.

[0047] The first positive pin 7 of a pair of chip clock input pins is connected to the second positive pin of a pair of clock source pins corresponding to the target clock source through a first capacitor, and the first negative pin 8 of a pair of chip clock input pins is connected to the second negative pin of a pair of clock source pins corresponding to the target clock source through a second capacitor. The target clock source is one of the clock sources connected to the circuit board.

[0048] Each time, the chip can only receive signals from one clock source and use that clock source as the target clock source.

[0049] According to the circuit board described above for establishing a connection between a clock source and a chip, the first positive pin 7 is connected to the second positive pin via a first capacitor, and the first negative pin 8 is connected to the second negative pin via a second capacitor. This eliminates the need for multiple capacitors in series, enabling connection between the chip's clock input and the target clock source, reducing clock signal loss. Furthermore, only one capacitor is placed on each trace between the two pins connected by the first capacitor and the two pins connected by the second capacitor, making trace spacing easy to adjust and reducing impedance matching difficulties.

[0050] In one possible implementation of the above embodiments, the trace length between the first positive pin 7 and the second positive pin is equal to the trace length between the first negative pin 8 and the second negative pin.

[0051] Equal trace lengths ensure that there is no phase difference during differential clock transmission, thus guaranteeing the accuracy of the clock signal transmitted to the chip.

[0052] In another possible implementation, the differential impedance generated by the spacing between the trace between the first positive pin 7 and the second positive pin and the trace between the first negative pin 8 and the second negative pin is 100 ohms.

[0053] In this application, the pins of various clock sources are arranged around the clock input pin of the chip. The traces between the first positive pin 7 and the second positive pin are close to the traces between the first negative pin 8 and the second negative pin, ensuring that the differential impedance can be controlled at 100 ohms.

[0054] Based on the above embodiments, the circuit board in this application implements various possible ways to connect multiple clock sources to the chip clock input pins, which are described in detail below. It should be noted that the implementation methods given below are merely illustrative examples and do not represent all implementation methods of the embodiments in this application.

[0055] In a first possible implementation, a first pair of clock source pins is provided on the first side of the line connecting the first positive pin 7 and the first negative pin 8 on the circuit board, a second pair of clock source pins is provided on the second side of the line near the first end of the line, and a third pair of clock source pins is provided on the second side of the line near the second end of the line.

[0056] For example, the first pair of clock source pins, the second pair of clock source pins, and the third pair of clock source pins each correspond to a clock source, and the three clock sources are different. For example, the clock source corresponding to the first pair of clock source pins can be a crystal oscillator, the clock source corresponding to the second pair of clock source pins can be a clock signal sent by a circuit board other than the circuit board of this application, and the clock source corresponding to the third pair of clock source pins can be a clock signal generator.

[0057] For example, if a coordinate axis is set, the direction of the Y-axis is from the first negative terminal pin 8 to the first positive terminal pin 7, the midpoint of the line connecting the first negative terminal pin 8 and the first positive terminal pin 7 is the origin, and the X-axis is set perpendicular to the Y-axis through the origin.

[0058] In the region where X>0, a first pair of clock source pins is set. The pin closest to the first positive pin 7 is designated as pin 2, and the pin closest to the first negative pin 8 is designated as pin 3. The distance from pin 2 to the first positive pin 7 is equal to the distance from pin 3 to the first negative pin 8. The differential impedance between pin 2 and the first positive pin 7, and between pin 3 and the first negative pin 8, is 100 ohms.

[0059] A third pair of clock source pins is set in the region where X≤0, Y≥0. The sixth pin 6 is closer to the first negative pin 8 than the first pin 1. The distance from the first pin 1 to the first positive pin 7 is equal to the distance from the sixth pin 6 to the first negative pin 8. The differential impedance generated by the trace between the first pin 1 and the first positive pin 7 and the trace between the sixth pin 6 and the first negative pin 8 is 100 ohms.

[0060] A second pair of clock source pins is set in the region where X≤0, Y≤0. The fifth pin 5 is closer to the first positive pin 7 than the fourth pin 4. The distance from the fifth pin 5 to the first positive pin 7 is equal to the distance from the fourth pin 4 to the first negative pin 8. The differential impedance generated by the trace between the fifth pin 5 and the first positive pin 7 and the trace between the fourth pin 4 and the first negative pin 8 is 100 ohms.

[0061] For example, such as Figure 2 The first pair of clock source pins includes a second pin 2 and a third pin 3, the second pair of clock source pins includes a fourth pin 4 and a fifth pin 5, and the third pair of clock source pins includes a sixth pin 6 and a first pin 1.

[0062] The connection line between the second pin 2 and the sixth pin 6 passes through the first positive pin 7 and is perpendicular to the connection line.

[0063] For example, the distance from the second pin 2 and the sixth pin 6 to the first positive pin 7 can be 1 mm.

[0064] The connection line between the third pin 3 and the fifth pin 5 passes through the first negative pin 8 and is perpendicular to the connection line.

[0065] For example, the distance from the third pin 3 and the fifth pin 5 to the first positive pin 7 can be 1 mm. The distance between the first positive pin 7 and the first negative pin 8 can also be 1 mm.

[0066] The fourth pin 4 is provided on the extension line of the connection line near the first end, and the first pin 1 is provided on the extension line of the connection line near the second end.

[0067] For example, the distance between the first pin 1 and the fourth pin 4 and the first positive pin 7 can be 1.414 mm.

[0068] The three pairs of time source pins are easier to arrange relative to the positions of the first positive pin 7 and the first negative pin 8 (the sixth pin 6, the first positive pin 7, the second pin 2, the fifth pin 5, the first negative pin 8, and the third pin 3 form a two-row, three-column arrangement; the first positive pin 7 is positioned as the first pin 1 on the opposite side of the first negative pin 8; and the first negative pin 8 is positioned as the fourth pin 4 on the opposite side of the first positive pin 7). This makes it easier for users to position the pins on the circuit board.

[0069] Specifically, if the clock source corresponding to the first pair of clock source pins is the target clock source, then the second pin 2 is the second positive pin, and the third pin 3 is the second negative pin, as shown below. Figure 3 The diagram shows the association between the first pair of clock source pins and the chip clock input pins. Figure 3 In the middle, a connection is established between the second pin 2 and the first positive pin 7, and a connection is established between the third pin 3 and the second negative pin (in order to establish a connection between the second and third positive pins). Figure 3 The Chinese box indicates that a connection has been established.

[0070] or,

[0071] If the clock source corresponding to the second pair of clock source pins is the target clock source, then the fifth pin 5 is the second positive pin, and the fourth pin 4 is the second negative pin. For example... Figure 4 The diagram shows the association between the second pair of clock source pins and the chip clock input pins. Figure 4 In the middle, a connection is established between the fifth pin 5 and the first positive pin 7, and a connection is established between the fourth pin 4 and the second negative pin (in order to establish a connection between the fifth pin 5 and the first positive pin 7). Figure 4 The Chinese box indicates that a connection has been established.

[0072] or,

[0073] If the clock source corresponding to the third pair of clock source pins is the target clock source, then the first pin 1 is the second positive pin, and the sixth pin 6 is the second negative pin. For example... Figure 5 The diagram shows the association between the third pair of clock source pins and the chip clock input pins. Figure 5 In the process, a connection is established between the first pin 1 and the first positive pin 7, and a connection is established between the sixth pin 6 and the second negative pin (in order to establish a connection between the first positive pin 1 and the second negative pin 7). Figure 5 The Chinese box indicates that a connection has been established.

[0074] Each clock source pin is located around the first positive pin 7 and the first negative pin 8, making it convenient for users to connect the clock source to the chip's clock input terminal by soldering capacitors.

[0075] Each pair of clock source pins is connected to the chip's clock input pin, transmitting the clock signal from the pair of clock sources to the chip's clock input.

[0076] In the above embodiments, when the clock input of the high-speed data chip is 100MHz, the first capacitor can be 0.1uf / 50V and the second capacitor can be 0.1uf / 50V.

[0077] Based on the above description of a circuit board for establishing a connection between a clock source and a chip, the following describes in detail how to use this circuit board.

[0078] A method for establishing a circuit board for connecting a clock source to a chip, applied to the aforementioned circuit board for establishing a clock source to a chip;

[0079] The second pin 2 is connected to the first terminal of the first capacitor, the first positive pin 7 is connected to the second terminal of the first capacitor, the third pin 3 is connected to the first terminal of the second capacitor, the first negative pin 8 is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal of the clock source corresponding to the first pair of clock source pins.

[0080] or,

[0081] Pin 5 is connected to the first terminal of the first capacitor, pin 7 is connected to the second terminal of the first capacitor, pin 4 is connected to the first terminal of the second capacitor, pin 8 is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal from the clock source corresponding to the second pair of clock source pins.

[0082] or,

[0083] Pin 1 is connected to the first terminal of the first capacitor, pin 7 is connected to the second terminal of the first capacitor, pin 6 is connected to the first terminal of the second capacitor, pin 8 is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal from the clock source corresponding to the third pair of clock source pins.

[0084] In one possible implementation, the board material of the circuit board is removed so that the trace length between the two pins connected to the first capacitor is the same as the trace length between the two pins connected to the second flashlight.

[0085] For example, if the trace length between the two pins connected to the first capacitor (the trace length between the first positive pin 7 and the second positive pin) is longer than the trace length between the two pins connected to the second capacitor (the trace length between the first negative pin 8 and the second negative pin), then the trace path between the two pins connected to the second capacitor and / or the circuit board area corresponding to the second negative pin can be cut down by a certain thickness so that the trace length between the two pins connected to the first capacitor and the trace length between the two pins connected to the second capacitor are equal.

[0086] This application also provides corresponding devices and computer storage media for implementing the solutions provided in this application.

[0087] The device includes a memory and a processor. The memory stores instructions or code, and the processor executes the instructions or code to enable the device to perform a method for establishing a circuit board for connecting a clock source to a chip, as described in any embodiment of this application.

[0088] The computer storage medium stores code. When the code is executed, the device running the code implements a method for establishing a circuit board connecting a clock source and a chip, as described in any embodiment of this application.

[0089] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0090] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0091] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0092] The above description is merely an exemplary implementation of this application and is not intended to limit the scope of protection of this application.

Claims

1. A circuit board for establishing a connection between a clock source and a chip, characterized in that, The circuit board is connected to multiple clock sources, and the circuit board is provided with a pair of clock source pins for each clock source. The circuit board also includes a pair of chip clock input pins connected to the chip clock input terminal. The clock source pin is positioned around the chip clock input pin; The first positive pin of a pair of chip clock input pins is connected to the second positive pin of a pair of clock source pins corresponding to the target clock source through a first capacitor, and the first negative pin of a pair of chip clock input pins is connected to the second negative pin of a pair of clock source pins corresponding to the target clock source through a second capacitor. The target clock source is one of the clock sources connected to the circuit board.

2. The circuit board according to claim 1, characterized in that, The trace length between the first positive pin and the second positive pin is equal to the trace length between the first negative pin and the second negative pin.

3. The circuit board according to claim 1, characterized in that, The differential impedance generated by the spacing between the traces between the first positive pin and the second positive pin and the traces between the first negative pin and the second negative pin is 100 ohms.

4. The circuit board according to claim 1, characterized in that, The clock source includes a crystal oscillator, a clock signal transmitted from a circuit board other than the circuit board, and a clock signal generator.

5. The circuit board according to claim 2, characterized in that, A first pair of clock source pins is provided on the first side of the line connecting the first positive pin and the first negative pin on the circuit board, a second pair of clock source pins is provided on the second side of the line near the first end of the line, and a third pair of clock source pins is provided on the second side of the line near the second end of the line.

6. The circuit board according to claim 5, characterized in that, The first pair of clock source pins includes a second pin and a third pin, the second pair of clock source pins includes a fourth pin and a fifth pin, and the third pair of clock source pins includes a sixth pin and a first pin; The connection line between the second pin and the sixth pin passes through the first positive pin and is perpendicular to the connection line; The connection line between the third pin and the fifth pin passes through the first negative pin and is perpendicular to the connection line. The fourth pin is disposed on the extension line of the connection line near the first end, and the first pin is disposed on the extension line of the connection line near the second end.

7. The circuit board according to claim 6, characterized in that, If the clock source corresponding to the first pair of clock source pins is the target clock source, then the second pin is the second positive pin, and the third pin is the second negative pin; or, If the clock source corresponding to the second pair of clock source pins is the target clock source, then the fifth pin is the second positive pin, and the fourth pin is the second negative pin; or, If the clock source corresponding to the third pair of clock source pins is the target clock source, then the first pin is the second positive pin, and the sixth pin is the second negative pin.

8. The circuit board according to claim 1, characterized in that, The first capacitor is 0.1uf / 50V, and the second capacitor is 0.1uf / 50V.

9. A method for establishing a circuit board connecting a clock source and a chip, characterized in that: Applied to a circuit board for establishing a connection between a clock source and a chip as described in any one of claims 1-8; The second pin is connected to the first terminal of the first capacitor, the first positive pin is connected to the second terminal of the first capacitor, the third pin is connected to the first terminal of the second capacitor, the first negative pin is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal of the clock source corresponding to the first pair of clock source pins. or, The fifth pin is connected to the first terminal of the first capacitor, the first positive pin is connected to the second terminal of the first capacitor, the fourth pin is connected to the first terminal of the second capacitor, the first negative pin is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal from the clock source corresponding to the second pair of clock source pins. or, The first pin is connected to the first terminal of the first capacitor, the first positive pin is connected to the second terminal of the first capacitor, the sixth pin is connected to the first terminal of the second capacitor, the first negative pin is connected to the second terminal of the second capacitor, and the chip clock input terminal receives the clock signal from the clock source corresponding to the third pair of clock source pins.

10. The method according to claim 9, characterized in that, Remove the board material from the circuit board so that the trace length between the two pins connected to the first capacitor is the same as the trace length between the two pins connected to the second flashlight.

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