Semiconductor memory device

Abstract

The semiconductor storage device of the embodiment includes a laminate in which gate electrode layers and first insulating layers are alternately stacked in a first direction; a semiconductor layer provided in the laminate and extending in the first direction; a second insulating layer provided between the semiconductor layer and the laminate; a third insulating layer provided between the second insulating layer and the laminate; and a first layer provided between the second insulating layer and the third insulating layer, containing silicon (Si) and nitrogen (N), including a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region containing fluorine (F) or not containing fluorine (F), the second region containing fluorine (F), and the fluorine concentration of the second region being higher than the fluorine concentration of the first region.

Description

[0001] This application is based on and claims the priority interest of Japanese Patent Application No. 2022-41800, filed on March 16, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present invention relate to semiconductor memory devices. Background Technology

[0003] Three-dimensional NAND flash memory, which configures memory cells in a three-dimensional manner, achieves high integration and low cost. In a three-dimensional NAND flash memory, for example, memory vias are formed through a stack of alternating insulating layers and gate electrode layers. By forming charge accumulation layers and semiconductor layers in the memory vias, a memory string is formed that connects multiple memory cells in series. Data is stored in the memory cells by controlling the amount of charge held in the charge accumulation layers. Summary of the Invention

[0004] One implementation provides a semiconductor memory device capable of improving charge retention characteristics.

[0005] The semiconductor memory device of the embodiment includes: a laminate formed by alternately stacking a gate electrode layer and a first insulating layer in a first direction; a semiconductor layer disposed in the laminate and extending in the first direction; a second insulating layer disposed between the semiconductor layer and the laminate; a third insulating layer disposed between the second insulating layer and the laminate; and a first layer disposed between the second insulating layer and the third insulating layer, containing silicon (Si) and nitrogen (N), including a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, wherein the first region contains fluorine (F) or does not contain fluorine (F), and the second region contains fluorine (F), wherein the fluorine concentration in the second region is higher than the fluorine concentration in the first region.

[0006] Based on the above configuration, a semiconductor memory device that improves charge retention characteristics can be provided. Attached Figure Description

[0007] Figure 1 This is a circuit diagram of the memory cell array of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 This is a schematic cross-sectional view of a memory cell in a comparative example semiconductor memory device.

[0011] Figure 5 This is an explanatory diagram illustrating a problem with a comparative example of a semiconductor memory device.

[0012] Figure 6 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the second embodiment.

[0013] Figure 7 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the second embodiment.

[0014] Figure 8 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the third embodiment.

[0015] Figure 9 This is a circuit diagram of the memory cell array of the semiconductor memory device according to the fourth embodiment.

[0016] Figure 10 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fourth embodiment.

[0017] Figure 11 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fourth embodiment.

[0018] Figure 12 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the fourth embodiment.

[0019] Figure 13 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the fourth embodiment.

[0020] Figure 14 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fifth embodiment.

[0021] Figure 15 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fifth embodiment.

[0022] Figure 16 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the fifth embodiment.

[0023] Figure 17 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the fifth embodiment. Detailed Implementation

[0024] Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components that have been described once will be omitted as appropriate.

[0025] Additionally, the terms "upper" or "lower" are sometimes used in this specification for ease of explanation. "Upper" or "lower" is, for example, a term indicating a relative positional relationship in the accompanying drawings. The terms "upper" or "lower" do not necessarily specify a positional relationship relative to gravity.

[0026] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor memory device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and electron energy loss spectroscopy (EELS). Furthermore, measurements of the thickness of the components constituting the semiconductor memory device, the distance between components, etc., can be performed, for example, by transmission electron microscopy (TEM). In addition, the determination of the crystal system of the constituent materials of the components constituting the semiconductor memory device and the comparison of the proportion of the crystal system can be achieved by using methods such as transmission electron microscopy, X-ray diffraction (XRD), electron beam diffraction (EBD), X-ray photoelectron spectroscopy (XPS), and synchronous radiation X-ray absorption fine structure (XAFS).

[0027] In this specification, "ferroelectric" means a substance that has spontaneous polarization (spontaneous polarization) even without an externally applied electric field, and whose polarization reverses when an externally applied electric field is applied. Conversely, in this specification, "paraelectric" means a substance that generates polarization when an electric field is applied, and whose polarization disappears when the electric field is removed.

[0028] (First Embodiment)

[0029] The semiconductor memory device of the first embodiment includes: a laminate formed by alternately stacking a gate electrode layer and a first insulating layer in a first direction; a semiconductor layer disposed in the laminate and extending in the first direction; a second insulating layer disposed between the semiconductor layer and the laminate; a third insulating layer disposed between the second insulating layer and the laminate; and a first layer disposed between the second insulating layer and the third insulating layer, containing silicon (Si) and nitrogen (N), including a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region containing or not containing fluorine (F), the second region containing fluorine (F), and the fluorine concentration in the second region being higher than the fluorine concentration in the first region.

[0030] The semiconductor memory device of the first embodiment is a three-dimensional NAND flash memory. The memory cell of the semiconductor memory device of the first embodiment is a so-called metal-oxygen-oxide-semiconductor (MONOS) type memory cell.

[0031] Figure 1 This is a circuit diagram of the memory cell array of the semiconductor memory device according to the first embodiment.

[0032] like Figure 1 As shown, the memory cell array 100 of the three-dimensional NAND flash memory in the first embodiment includes multiple word lines WL, a common source line CSL, a source select gate line SGS, multiple drain select gate lines SGD, multiple bit lines BL, and multiple memory strings MS.

[0033] Multiple word lines (WL) are arranged separately in the z-direction. Multiple word lines (WL) are stacked in the z-direction. Multiple memory strings (MS) extend in the z-direction. Multiple bit lines (BL) extend, for example, in the x-direction.

[0034] Hereinafter, the x-direction is defined as the second direction, the y-direction as the third direction, and the z-direction as the first direction. The x, y, and z directions intersect each other, for example, they are perpendicular to each other.

[0035] like Figure 1 As shown, a memory string MS includes a source selection transistor SST connected in series between a common source line CSL and a bit line BL, multiple memory cells, and a drain selection transistor SDT. A memory string MS is selected by selecting one bit line BL and one drain selection gate line SGD, and a memory cell becomes selectable by selecting one word line WL. The word line WL is the gate electrode of the memory cell transistor MT that constitutes the memory cell.

[0036] Figure 2 of (a), Figure 2(b) is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the first embodiment. Figure 2 of (a), Figure 2 (b) indicates Figure 1 A cross-section of multiple memory cells in a memory string MS, for example, surrounded by dashed lines, in a memory cell array 100.

[0037] Figure 2 (a) is a yz cross-sectional view of the storage cell array 100. Figure 2 (a) is Figure 2 BB' section of (b). Figure 2 (b) is an xy cross-sectional view of the storage cell array 100. Figure 2 (b) is Figure 2 Section AA' of (a). In Figure 2 In (a), the area enclosed by the dashed line is one storage unit.

[0038] Figure 3 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the first embodiment. Figure 3 This is a partially enlarged cross-sectional view of the storage cell.

[0039] like Figure 2 of (a), Figure 2 (b) Figure 3 As shown, the memory cell array 100 includes word lines WL, semiconductor layers 10, interlayer insulating layers 12, tunnel insulating layers 14, charge storage layers 16, first barrier insulating layers 18, and core insulating regions 20.

[0040] Multiple word lines WL and multiple interlayer insulating layers 12 constitute a laminate 30. The charge storage layer 16 includes a charge storage region 16a and an inter-cell region 16b.

[0041] Word line WL is an example of a gate electrode layer. Interlayer insulation layer 12 is an example of a first insulation layer. Tunnel insulation layer 14 is an example of a second insulation layer. First barrier insulation layer 18 is an example of a third insulation layer. Charge accumulation layer 16 is an example of a first layer. Charge accumulation region 16a is an example of a first region. Intercell region 16b is an example of a second region.

[0042] The memory cell array 100 is disposed, for example, on a semiconductor substrate (not shown). The semiconductor substrate has surfaces parallel to the x-direction and the y-direction.

[0043] Word lines WL and interlayer insulating layers 12 are alternately stacked on a semiconductor substrate in the z-direction. The word lines WL are repeatedly arranged separately in the z-direction. Multiple word lines WL and multiple interlayer insulating layers 12 constitute a stack 30. The word lines WL function as control electrodes for memory cell transistors MT.

[0044] The word line (WL) is a plate-shaped conductor. The word line WL can be, for example, a metal, a metal nitride, a metal carbide, or a semiconductor. For example, the word line WL is tungsten (W). The thickness of the word line WL in the z-direction is, for example, 5 nm or more and 20 nm or less.

[0045] Interlayer insulation layer 12 separates the word lines WL from each other. Interlayer insulation layer 12 electrically separates the word lines WL from each other.

[0046] The interlayer insulating layer 12 is, for example, an oxide, an oxynitride, or a nitride. The interlayer insulating layer 12 may contain, for example, silicon (Si) and oxygen (O). The interlayer insulating layer 12 may be, for example, silicon oxide. The thickness of the interlayer insulating layer 12 in the z-direction is, for example, 5 nm or more and 20 nm or less.

[0047] Interlayer insulation 12 contains, for example, fluorine (F). The fluorine concentration of interlayer insulation 12 is, for example, 1 × 10⁻⁶. 19 atoms / cm 3 Above and 1×10 22 atoms / cm 3 the following.

[0048] A semiconductor layer 10 is disposed in the laminate 30. The semiconductor layer 10 extends in the z-direction. The semiconductor layer 10 extends in a direction perpendicular to the surface of the semiconductor substrate.

[0049] A semiconductor layer 10 is disposed throughout the laminate 30. The semiconductor layer 10 is surrounded by multiple word lines WL. The semiconductor layer 10 is, for example, cylindrical. The semiconductor layer 10 functions as the channel for the memory cell transistor MT.

[0050] Semiconductor layer 10 is, for example, a polycrystalline semiconductor. Semiconductor layer 10 is, for example, polycrystalline silicon.

[0051] A tunnel insulating layer 14 is disposed between the semiconductor layer 10 and the laminate 30. The tunnel insulating layer 14 is disposed between the semiconductor layer 10 and the word line WL. The tunnel insulating layer 14 is disposed between the semiconductor layer 10 and at least one of the plurality of word lines WL. The tunnel insulating layer 14 is disposed between the semiconductor layer 10 and the charge storage layer 16. The tunnel insulating layer 14 is also disposed between the semiconductor layer 10 and the interlayer insulating layer 12. The tunnel insulating layer 14 has the function of allowing charge to pass through according to the voltage applied between the word line WL and the semiconductor layer 10.

[0052] The tunnel insulation layer 14 contains, for example, silicon (Si), nitrogen (N), and oxygen (O). The tunnel insulation layer 14 contains, for example, silicon nitride or silicon oxynitride. The thickness of the tunnel insulation layer 14 is, for example, 3 nm or more and 8 nm or less.

[0053] The tunnel insulating layer 14 includes, for example, a lower layer, an intermediate layer, and an upper layer. The lower layer is disposed between the semiconductor layer 10 and the intermediate layer. The intermediate layer is disposed between the lower layer and the upper layer. The upper layer is disposed between the intermediate layer and the charge storage layer 16.

[0054] The lower layer is, for example, silicon oxide. The middle layer is, for example, silicon nitride or silicon oxynitride. The upper layer is, for example, silicon oxide.

[0055] The charge accumulation layer 16 is disposed between the tunnel insulation layer 14 and the first barrier insulation layer 18.

[0056] The charge accumulation layer 16 has the function of capturing and storing charge, such as electrons. The threshold voltage of the memory cell transistor MT changes according to the amount of charge stored in the charge accumulation layer 16. By utilizing this change in threshold voltage, one memory cell can store data.

[0057] For example, the voltage at which the memory cell transistor MT is turned on changes by the threshold voltage change of the memory cell transistor MT. For example, when the state with a high threshold voltage is defined as data "0" and the state with a low threshold voltage is defined as data "1", the memory cell can store 1 bit of data, which is both "0" and "1".

[0058] The charge storage layer 16 contains silicon (Si) and nitrogen (N). The charge storage layer 16 may contain, for example, silicon nitride. The thickness of the charge storage layer 16 may be, for example, 3 nm or more and 10 nm or less.

[0059] like Figure 3 As shown, the charge storage layer 16 includes a charge storage region 16a and an inter-cell region 16b. The charge storage region 16a is disposed between the word line WL and the semiconductor layer 10. The inter-cell region 16b is disposed between the interlayer insulating layer 12 and the semiconductor layer 10.

[0060] The charge accumulation region 16a contains silicon (Si) and nitrogen (N). The charge accumulation region 16a may or may not contain fluorine (F). The inter-unit region 16b contains silicon (Si), nitrogen (N), and fluorine (F). The fluorine concentration in the inter-unit region 16b is higher than that in the charge accumulation region 16a.

[0061] The fluorine concentration in inter-unit region 16b is, for example, 1 × 10⁻⁶. 19 atoms / cm 3 Above and 1×10 20 atoms / cm3 The following. Additionally, the fluorine concentration in charge accumulation region 16a is, for example, less than 1 × 10⁻⁶. 19 atoms / cm 3 .

[0062] The atomic ratio of nitrogen (N) to silicon (Si) in the charge accumulation layer 16 is, for example, 1.2 or more.

[0063] The atomic ratio of nitrogen (N) to silicon (Si) in charge accumulation region 16a is greater than that in inter-unit region 16b.

[0064] The atomic ratio (N / Si) of nitrogen (N) to silicon (Si) in the charge accumulation region 16a is, for example, 1.25 or more and 1.4 or less. Furthermore, the atomic ratio (N / Si) of nitrogen (N) to silicon (Si) in the inter-unit region 16b is, for example, 1.2 or more and less than 1.25.

[0065] Furthermore, when silicon nitride is in stoichiometric form, i.e., when silicon nitride is in the form of Si3N4, the atomic ratio of nitrogen (N) to silicon (Si) (N / Si) is approximately 1.33.

[0066] For example, by thermally diffusing fluorine from the fluorine-containing interlayer insulation layer 12, the fluorine concentration in the inter-cell region 16b can be higher than the fluorine concentration in the charge accumulation region 16a.

[0067] The first barrier insulating layer 18 is disposed between the tunnel insulating layer 14 and the word line WL. The first barrier insulating layer 18 is disposed between the charge storage layer 16 and the word line WL. The first barrier insulating layer 18 is also disposed between the semiconductor layer 10 and the interlayer insulating layer 12. The first barrier insulating layer 18 has the function of preventing the current flowing between the charge storage layer 16 and the word line WL.

[0068] The first barrier insulating layer 18 is, for example, an oxide, a nitride, or a nitride. The first barrier insulating layer 18 contains, for example, silicon (Si) and oxygen (O). The first barrier insulating layer 18 is, for example, silicon oxide. The thickness of the first barrier insulating layer 18 is, for example, 3 nm or more and 10 nm or less.

[0069] A core insulating region 20 is disposed within the laminate 30. The core insulating region 20 extends in the z-direction. The core insulating region 20 is disposed throughout the laminate 30. The core insulating region 20 is surrounded by a semiconductor layer 10. The core insulating region 20 is surrounded by multiple word lines WL. The core insulating region 20 is columnar. For example, the core insulating region 20 is cylindrical.

[0070] The core insulating region 20 is, for example, an oxide, a nitride, or a compound. The core insulating region 20 may contain, for example, silicon (Si) and oxygen (O). The core insulating region 20 may be, for example, silicon oxide.

[0071] Next, the function and effects of the semiconductor memory device of the first embodiment will be explained.

[0072] The three-dimensional NAND flash memory of the first embodiment improves charge retention characteristics by making the fluorine concentration in the inter-cell region 16b of the charge accumulation layer 16 higher than that in the charge accumulation region 16a. Threshold fluctuations of the memory cell transistor MT in the three-dimensional NAND flash memory of the first embodiment are suppressed.

[0073] Figure 4 This is a schematic cross-sectional view of a memory cell in a comparative example semiconductor memory device. The comparative example semiconductor memory device differs from the example in that the charge accumulation layer 16 does not include the high-fluorine-concentration inter-cell region 16b. Figure 3 The semiconductor memory device shown in the first embodiment is different.

[0074] Figure 5 This is an explanatory diagram illustrating a problem with a comparative example of a semiconductor memory device. Figure 5 This indicates the state in which electrons have been written into the charge accumulation layer 16.

[0075] like Figure 5 As shown, after electrons are written into the charge accumulation layer 16, electron de-trap occurs over time. The electrons written into the charge accumulation layer 16 detach laterally along the charge accumulation layer 16. This is known as lateral electron detachment.

[0076] When lateral electron ejection occurs, the threshold voltage of the memory cell transistor MT changes. In other words, when lateral electron ejection occurs, the charge retention characteristics of the 3D NAND flash memory deteriorate.

[0077] It is believed that the lateral detachment of electrons occurs due to the trapping energy level present in the charge accumulation layer 16. It is believed that electrons written into the charge accumulation layer 16 move laterally along the charge accumulation layer 16 via the trapping energy level.

[0078] When silicon nitride contains fluorine, the trapping level density in silicon nitride decreases. The charge accumulation layer 16 of the three-dimensional NAND flash memory in the first embodiment includes an inter-cell region 16b with a higher fluorine concentration than the charge accumulation region 16a. By increasing the fluorine concentration in the inter-cell region 16b, the trapping level density in the inter-cell region 16b decreases. Therefore, lateral electron ejection is suppressed. Consequently, fluctuations in the threshold voltage of the memory cell transistor MT are suppressed. In other words, the charge retention characteristics of the three-dimensional NAND flash memory are improved.

[0079] The preferred fluorine concentration in inter-unit region 16b is 1 × 10⁻⁶. 19 atoms / cm 3 Above and 1×10 20 atoms / cm 3 The following applies when the fluoride concentration exceeds 1×10⁻⁶. 20 atoms / cm 3 At this point, the trapping level density begins to increase. By satisfying the above conditions with fluorine concentration, a low trapping level density can be achieved. Furthermore, when the fluorine concentration exceeds 1 × 10⁻⁶... 20 atoms / cm 3 At this point, the trapping energy level becomes shallower. Therefore, electrons are not trapped by the trapping energy level, and lateral escape may be promoted.

[0080] The fluorine concentration in charge accumulation region 16a is preferably less than 1 × 10⁻⁶. 19 atoms / cm 3 When the fluorine concentration in charge accumulation region 16a becomes 1×10 19 atoms / cm 3 When the above conditions are met, the trapping energy level density in the charge accumulation region 16a decreases, and the amount of charge written to the memory cell decreases.

[0081] The atomic ratio of nitrogen (N) to silicon (Si) in the charge storage layer 16 is preferably 1.2 or more, for example.

[0082] Fluorine diffusion in silicon nitride depends on the atomic ratio of nitrogen (N) to silicon (Si) (N / Si). When the atomic ratio of nitrogen (N) to silicon (Si) is less than 1.2, fluorine diffusion in silicon nitride increases. Therefore, for example, fluorine in the inter-unit region 16b may diffuse into the charge accumulation region 16a, potentially lowering the trapping energy level density of the charge accumulation region 16a.

[0083] The atomic ratio (N / Si) of nitrogen (N) in charge storage region 16a is preferably greater than that of nitrogen (N) in inter-unit region 16b. By increasing the atomic ratio (N / Si) of nitrogen (N) in charge storage region 16a, diffusion of fluorine from inter-unit region 16b into charge storage region 16a can be suppressed.

[0084] The atomic ratio (N / Si) of nitrogen (N) in charge storage region 16a is preferably 1.25 or higher. By making the atomic ratio (N / Si) of nitrogen (N) in charge storage region 16a 1.25 or higher, the diffusion of fluorine from inter-unit region 16b into charge storage region 16a can be suppressed. Furthermore, by making the atomic ratio (N / Si) of nitrogen (N) in charge storage region 16a 1.25 or higher, the shallow trapping energy levels in charge storage region 16a are reduced, making electron detrapping more difficult.

[0085] The atomic ratio of nitrogen (N) to silicon (Si) in the inter-unit region 16b (N / Si) is preferably 1.2 or higher and less than 1.25. By making the atomic ratio of nitrogen (N) to silicon (Si) higher than the aforementioned lower limit, the diffusion of fluorine in silicon nitride is moderately suppressed, and the control of the fluorine concentration in the inter-unit region 16b becomes easier. Furthermore, by making the atomic ratio of nitrogen (N) to silicon (Si) lower than the aforementioned upper limit, the diffusion of fluorine progresses, and it becomes easier to increase the fluorine concentration in the inter-unit region 16b.

[0086] According to the first embodiment, by increasing the fluorine concentration in the inter-cell region 16b of the charge storage layer 16, the lateral detachment of electrons is suppressed, and a semiconductor memory device with improved charge retention characteristics can be provided.

[0087] (Second Implementation)

[0088] The semiconductor memory device of the second embodiment differs from the semiconductor device of the first embodiment in that it further includes a fourth insulating layer. This fourth insulating layer is disposed between the gate electrode layer and the third insulating layer, and between the gate electrode layer and the first insulating layer. It includes a third region between the gate electrode layer and the third insulating layer, and a fourth region between the gate electrode layer and the first insulating layer. The third region may or may not contain fluorine (F), while the fourth region contains fluorine (F), and the fluorine concentration in the fourth region is higher than that in the third region. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0089] Figure 6 of (a), Figure 6 (b) is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the second embodiment. Figure 6 of (a), Figure 6 (b) is the same as in the first embodiment. Figure 2 of (a), Figure 2 The diagram corresponding to (b).

[0090] Figure 6 (a) is a yz cross-sectional view of the storage cell array 200. Figure 6 (a) is Figure 6 (b) BB' section. Figure 6 (b) is an xy cross-sectional view of the storage cell array 200. Figure 6 (b) is Figure 6 Section AA' of (a). In Figure 6 In (a), the area enclosed by the dashed line is one storage unit.

[0091] Figure 7 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the second embodiment. Figure 7 This is a partially enlarged cross-sectional view of the storage cell. Figure 7 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0092] like Figure 6 of (a), Figure 6 (b) Figure 7 As shown, the memory cell array 200 includes word lines WL, semiconductor layers 10, interlayer insulating layers 12, tunnel insulating layers 14, charge storage layers 16, first barrier insulating layers 18, second barrier insulating layers 19, and core insulating regions 20.

[0093] Multiple word lines WL and multiple interlayer insulating layers 12 constitute a laminate 30. The charge accumulation layer 16 includes a charge accumulation region 16a and an inter-unit region 16b. The second barrier insulating layer 19 includes a barrier region 19a and an interlayer region 19b.

[0094] Word line WL is an example of a gate electrode layer. Interlayer insulation layer 12 is an example of a first insulation layer. Tunnel insulation layer 14 is an example of a second insulation layer. First barrier insulation layer 18 is an example of a third insulation layer. Charge accumulation layer 16 is an example of a first layer. Charge accumulation region 16a is an example of a first region. Inter-cell region 16b is an example of a second region. Second barrier insulation layer 19 is an example of a fourth insulation layer. Barrier region 19a is an example of a third region. Interlayer region 19b is an example of a fourth region.

[0095] The second barrier insulation layer 19 is disposed between the word line WL and the first barrier insulation layer 18. The second barrier insulation layer 19 is disposed between the word line WL and the interlayer insulation layer 12. The second barrier insulation layer 19 has the function of preventing the current flowing between the charge accumulation layer 16 and the word line WL.

[0096] The second barrier insulating layer 19 is, for example, an oxide, a nitride, or a nitride. The second barrier insulating layer 19 may contain, for example, aluminum (Al) and oxygen (O). The second barrier insulating layer 19 may be, for example, aluminum oxide. The thickness of the second barrier insulating layer 19 is, for example, 3 nm or more and 10 nm or less.

[0097] By providing a second barrier insulating layer 19, the charge retention characteristics of the three-dimensional NAND flash memory are further improved compared to the first embodiment.

[0098] like Figure 7 As shown, the second barrier insulation layer 19 includes a barrier region 19a and an interlayer region 19b. The barrier region 19a is disposed between the word line WL and the first barrier insulation layer 18. The interlayer region 19b is disposed between the word line WL and the interlayer insulation layer 12.

[0099] Barrier region 19a contains aluminum (Al) and oxygen (O). Barrier region 19a may or may not contain fluorine (F). Interlayer region 19b contains aluminum (Al), oxygen (O), and fluorine (F). The fluorine concentration in interlayer region 19b is higher than that in barrier region 19a.

[0100] For example, by thermally diffusing fluorine from the fluorine-containing interlayer insulation layer 12, the fluorine concentration in the interlayer region 19b can be higher than the fluorine concentration in the barrier region 19a.

[0101] By increasing the fluorine concentration in interlayer region 19b, the dielectric constant of interlayer region 19b is reduced. Therefore, the capacitance between word lines WL is reduced. This reduces the power consumption of the 3D NAND flash memory. Furthermore, the 3D NAND flash memory can be made faster.

[0102] According to the second embodiment, by increasing the fluorine concentration in the inter-cell region 16b of the charge storage layer 16, the lateral detachment of electrons is suppressed, and a semiconductor memory device with improved charge retention characteristics can be provided.

[0103] (Third Implementation)

[0104] The semiconductor memory device of the third embodiment differs from the semiconductor device of the first embodiment in that the third insulating layer contains a ferroelectric material in at least the region between the first insulating layer and the first layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0105] Figure 8 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the third embodiment. Figure 8 This is a partially enlarged cross-sectional view of the storage cell. Figure 8 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0106] At least a portion of the first barrier insulating layer 18 contains a ferroelectric material. The first barrier insulating layer 18, for example, contains at least one of hafnium (Hf) and zirconium (Zr) as well as oxygen (O). The first barrier insulating layer 18, for example, contains at least one of hafnium oxide and zirconium oxide. The first barrier insulating layer 18 is, for example, hafnium oxide or zirconium oxide.

[0107] like Figure 8 As shown, the first barrier insulating layer 18 includes a ferroelectric region 18a and a paraelectric region 18b. The ferroelectric region 18a is disposed between the interlayer insulating layer 12 and the charge accumulation layer 16. The ferroelectric region 18a is disposed between the interlayer insulating layer 12 and the inter-cell region 16b.

[0108] The paraelectric region 18b is located between the word line WL and the charge accumulation layer 16. The paraelectric region 18b is located between the word line WL and the charge accumulation region 16a.

[0109] Ferroelectric region 18a contains ferroelectric material. Ferroelectric region 18a exhibits ferroelectric properties.

[0110] Ferroelectric region 18a contains, for example, at least one of the metal elements chosen from hafnium (Hf) and zirconium (Zr) and oxygen (O). Ferroelectric region 18a is predominantly composed of orthorhombic or trigonal crystals. Predominantly composed of orthorhombic or trigonal crystals means that orthorhombic or trigonal crystals exhibit the highest proportion of presence in the material constituting ferroelectric region 18a.

[0111] The paraelectric region 18b contains a paraelectric material. The paraelectric region 18b is paraelectric.

[0112] The paraelectric region 18b contains, for example, at least one of the metal elements chosen from hafnium (Hf) and zirconium (Zr) and oxygen (O). The paraelectric region 18b is predominantly composed of elements other than those in orthorhombic and trigonal crystal systems. Predominantly composed of elements other than those in orthorhombic and trigonal crystal systems means that, among the materials constituting the paraelectric region 18b, elements other than those in orthorhombic and trigonal crystal systems exhibit the highest proportion of presence.

[0113] Hafnium oxide exhibits ferroelectric properties when it is crystallized in orthorhombic or trigonal systems.

[0114] Hafnium oxide exhibits ferroelectricity, for example, when crystallized in the third orthorhombic system (space group Pbc21, space group number 29) or the trigonal system (space group R3m or P3 or R3, space group number 160 or 143 or 146).

[0115] Hafnium oxide is not ferroelectric when it is in a crystal system other than orthorhombic or trigonal, or when it is amorphous. Hafnium oxide is paraelectric when it is in a crystal system other than orthorhombic or trigonal, or when it is amorphous. "Other than orthorhombic or trigonal" refers to cubic, hexagonal, tetragonal, monoclinic, and triclinic crystal systems.

[0116] Zirconia exhibits ferroelectricity when it is crystallized in orthorhombic or trigonal systems.

[0117] Zirconia exhibits ferroelectricity, for example, when crystallized in the orthorhombic III system (space group Pbc21, space group number 29) or the trigonal system (space group R3m or P3 or R3, space group number 160 or 143 or 146).

[0118] Zirconia does not exhibit ferroelectricity when it is in a crystalline form other than orthorhombic or trigonal, or when it is amorphous. Zirconia is paraelectric when it is in a crystalline form other than orthorhombic or trigonal, or when it is amorphous.

[0119] The first barrier insulating layer 18 has a ferroelectric region 18a disposed between the interlayer insulating layer 12 and the inter-cell region 16b. As a result, electrons trapped by the trapping energy level of the inter-cell region 16b are attracted by the ferroelectric region 18a. Therefore, the movement of electrons in the inter-cell region 16b is suppressed. Consequently, lateral electron detachment is further suppressed, and the charge retention characteristics of the three-dimensional NAND flash memory are further improved.

[0120] Alternatively, the structure can be configured such that the first barrier insulation layer 18 does not have a paraelectric region 18b, and the entire first barrier insulation layer 18 contains ferroelectric material.

[0121] According to the third embodiment, by increasing the fluorine concentration in the inter-cell region 16b of the charge storage layer 16, the lateral detachment of electrons is suppressed, and a semiconductor memory device with improved charge retention characteristics can be provided.

[0122] (Fourth implementation)

[0123] The semiconductor memory device according to the fourth embodiment includes: a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and adjacent to the first gate electrode layer in a second direction intersecting the first direction; a semiconductor layer disposed between the first gate electrode layer and the second gate electrode layer and extending in a third direction intersecting the first and second directions; a third gate electrode layer extending in the first direction and adjacent to the first gate electrode layer in the third direction; a first insulating layer disposed between the first gate electrode layer and the third gate electrode layer; and a second insulating layer disposed between the first and third gate electrode layers. The first insulating layer is disposed between the semiconductor layer and the first gate electrode layer and between the semiconductor layer and the first insulating layer; the third insulating layer is disposed between the second insulating layer and the first gate electrode layer and between the second insulating layer and the first insulating layer; the first layer is disposed between the second insulating layer and the third insulating layer, containing silicon (Si) and nitrogen (N), including a first region between the first gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region may or may not contain fluorine (F), the second region contains fluorine (F), and the fluorine concentration in the second region is higher than the fluorine concentration in the first region.

[0124] The semiconductor memory device of the fourth embodiment is a three-dimensional NAND flash memory. The memory cell of the semiconductor memory device of the fourth embodiment is a so-called metal-oxygen-oxide-semiconductor (MONOS) type memory cell.

[0125] The structure of the memory cell array in the fourth embodiment of the semiconductor memory device differs from that in the first embodiment. Specifically, the memory cell array in the first embodiment has a structure in which the semiconductor layer forming the channel of the memory cell transistor is surrounded by a gate electrode layer, but the memory cell array in the fourth embodiment has a structure in which the semiconductor layer is sandwiched between two electrically separated gate electrode layers. Hereinafter, some descriptions that are repeated with the first embodiment will be omitted.

[0126] Figure 9 This is a circuit diagram of the memory cell array of the semiconductor memory device according to the fourth embodiment.

[0127] like Figure 9 As shown, the memory cell array 400 of the three-dimensional NAND flash memory in the fourth embodiment includes a source select transistor SST, a drain select transistor SDT, word lines WLa and WLb, bit lines BL1 to BL4, a common source line CSL, a source select gate line SGS, a drain select gate line SGD, and a memory string MS.

[0128] the following, Figure 9The x-direction shown is an example of the first direction. The y-direction is an example of the second direction. The z-direction is an example of the third direction. The y-direction intersects the x-direction. The z-direction intersects both the x-direction and the y-direction. For example, the x-direction is orthogonal to the y-direction. For example, the z-direction is orthogonal to both the x-direction and the y-direction.

[0129] like Figure 9 As shown, a memory string MS includes a source selection transistor SST connected in series between a common source line CSL and a bit line BL, multiple memory cells, and a drain selection transistor SDT. A memory string MS is selected by selecting one bit line BL and one drain selection gate line SGD, and a memory cell becomes selectable by selecting one word line WL. The word line WL is the gate electrode of the memory cell transistor MT that constitutes the memory cell.

[0130] Word lines WLa and WLb extend in the x-direction. Word lines WLa and WLb are connected to the gate electrode of the memory cell transistor MT. Word lines WLa and WLb control the gate voltage of the memory cell transistor MT.

[0131] Word lines WLa and WLb are electrically disconnected. Word lines WLa and WLb are electrically connected. Word lines WLb and WLb are electrically connected.

[0132] The source-select transistor SST is electrically connected to the common-source line CSL. The source-select transistor SST is controlled by the voltage applied to the source-select gate line SGS.

[0133] The drain-select transistor SDT is connected to bit lines BL1 to BL4. The drain-select transistor SDT is controlled by the voltage applied to the drain-select gate line SGD.

[0134] exist Figure 9 In the example, when there are 4 memory cells connected in series, the case with 4 bit lines is illustrated, but the number of memory cells connected in series and the number of bit lines are not limited to 4 or 4.

[0135] Figure 10 , Figure 11 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fourth embodiment. Figure 10 This is the xy profile of the storage cell array 400. Figure 10 It includes Figure 11 A cross-section of the BB' face. Figure 11 This is the yz profile of the storage cell array 400. Figure 11 yes Figure 10 AA' section.

[0136] exist Figure 10 and Figure 11In the diagram, the area enclosed by a dashed line represents a storage unit. Figure 10 and Figure 11 The example shows memory cells MC1 and MC2 that are adjacent in the y-direction.

[0137] Figure 12 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the fourth embodiment. Figure 12 This is a partially enlarged cross-sectional view of the storage cell. Figure 12 yes Figure 11 A magnified view of a portion of the image.

[0138] Figure 13 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the fourth embodiment. Figure 13 yes Figure 10 A magnified view of a portion of the image.

[0139] The memory cell array 400 includes a semiconductor layer 10, a first gate electrode layer 11a, a second gate electrode layer 11b, a third gate electrode layer 11c, a fourth gate electrode layer 11d, an interlayer insulating layer 12, a trench insulating layer 13, a tunnel insulating layer 14, a charge accumulation layer 16, a first barrier insulating layer 18, and a core insulating region 20. The charge accumulation layer 16 includes a first charge accumulation region 16a1, a second charge accumulation region 16a2, a first inter-cell region 16b1, and a second inter-cell region 16b2.

[0140] Interlayer insulation layer 12 is an example of the first insulation layer. Tunnel insulation layer 14 is an example of the second insulation layer. First barrier insulation layer 18 is an example of the third insulation layer. Charge accumulation layer 16 is an example of the first layer. First charge accumulation region 16a1 is an example of the first region. Second charge accumulation region 16a2 is an example of the third region. First inter-unit region 16b1 is an example of the second region. Second inter-unit region 16b2 is an example of the fourth region.

[0141] The memory cell array 400 is disposed, for example, on a semiconductor substrate (not shown). The semiconductor substrate has surfaces parallel to the x-direction and the y-direction.

[0142] The first gate electrode layer 11a extends in the x direction. For example, the first gate electrode layer 11a is... Figure 9 The word line WLa shown corresponds to this. The first gate electrode layer 11a functions as the gate electrode of the transistor in the memory cell MC1.

[0143] The second gate electrode layer 11b extends in the x-direction. The second gate electrode layer 11b is adjacent to the first gate electrode layer 11a in the y-direction. For example, the second gate electrode layer 11b is adjacent to... Figure 9The word line WLb shown corresponds to this. The second gate electrode layer 11b functions as the gate electrode of the transistor in the memory cell MC2.

[0144] The third gate electrode layer 11c extends in the x-direction. The third gate electrode layer 11c is adjacent to the first gate electrode layer 11a in the z-direction. For example, the third gate electrode layer 11c is adjacent to... Figure 9 The word line WLa shown corresponds to this. The third gate electrode layer 11c functions as the gate electrode of the transistor in the memory cell.

[0145] The fourth gate electrode layer 11d extends in the x-direction. The fourth gate electrode layer 11d is adjacent to the third gate electrode layer 11c in the y-direction. Furthermore, the fourth gate electrode layer 11d is adjacent to the second gate electrode layer 11b in the z-direction. The fourth gate electrode layer 11d, for example, is adjacent to... Figure 9 The word line WLb shown corresponds to this. The fourth gate electrode layer 11d functions as the gate electrode of the transistor in the memory cell.

[0146] The first gate electrode layer 11a, the second gate electrode layer 11b, the third gate electrode layer 11c, and the fourth gate electrode layer 11d are, for example, metals, metal nitrides, metal carbides, or semiconductors. The first gate electrode layer 11a, the second gate electrode layer 11b, the third gate electrode layer 11c, and the fourth gate electrode layer 11d are, for example, tungsten (W).

[0147] Semiconductor layer 10 is disposed between the first gate electrode layer 11a and the second gate electrode layer 11b. Semiconductor layer 10 is disposed between the third gate electrode layer 11c and the fourth gate electrode layer 11d. Semiconductor layer 10 extends in the z-direction. Semiconductor layer 10 is, for example, cylindrical in shape.

[0148] Semiconductor layer 10 functions as the channel for the memory cell transistor MT.

[0149] Semiconductor layer 10 is, for example, a polycrystalline semiconductor. Semiconductor layer 10 contains, for example, polycrystalline silicon. Semiconductor layer 10 is, for example, a polycrystalline silicon layer. The thickness of semiconductor layer 10 in the xy plane is, for example, 5 nm or more and 30 nm or less.

[0150] Interlayer insulating layer 12 is disposed between the first gate electrode layer 11a and the third gate electrode layer 11c, and between the second gate electrode layer 11b and the fourth gate electrode layer 11d.

[0151] The interlayer insulating layer 12 is, for example, an oxide, a oxynitride, or a nitride. The interlayer insulating layer 12 may contain silicon oxide. The thickness of the interlayer insulating layer 12 in the z-direction is, for example, 5 nm or more and 30 nm or less.

[0152] Interlayer insulation 12 contains, for example, fluorine (F). The fluorine concentration of interlayer insulation 12 is, for example, 1 × 10⁻⁶.19 atoms / cm 3 Above and 1×10 22 atoms / cm 3 the following.

[0153] A trench insulating layer 13 is disposed between the first gate electrode layer 11a and the second gate electrode layer 11b. A trench insulating layer 13 is disposed between the third gate electrode layer 11c and the fourth gate electrode layer 11d. The trench insulating layer 13 is adjacent to the semiconductor layer 10 in the x-direction.

[0154] The trench insulating layer 13 is, for example, an oxide, a nitride, or a nitride. The trench insulating layer 13 may contain, for example, silicon oxide. The trench insulating layer 13 may be, for example, silicon oxide.

[0155] The trench insulation layer 13 contains, for example, fluorine (F). The fluorine concentration of the trench insulation layer 13 is, for example, 1 × 10⁻⁶. 19 atoms / cm 3 Above and 1×10 22 atoms / cm 3 the following.

[0156] A tunnel insulating layer 14 surrounds the semiconductor layer 10. The tunnel insulating layer 14 is disposed between the semiconductor layer 10 and the first gate electrode layer 11a. The tunnel insulating layer 14 is disposed between the semiconductor layer 10 and the second gate electrode layer 11b. The tunnel insulating layer 14 is disposed between the semiconductor layer 10 and the third gate electrode layer 11c. The tunnel insulating layer 14 is disposed between the semiconductor layer 10 and the fourth gate electrode layer 11d.

[0157] A tunnel insulating layer 14 is disposed between the semiconductor layer 10 and the charge storage layer 16. The tunnel insulating layer 14 is also disposed between the semiconductor layer 10 and the interlayer insulating layer 12. The tunnel insulating layer 14 has the function of allowing charge to pass through according to the voltage applied between the gate electrode layer and the semiconductor layer 10.

[0158] The tunnel insulation layer 14 contains, for example, silicon (Si), nitrogen (N), and oxygen (O). The tunnel insulation layer 14 contains, for example, silicon nitride or silicon oxynitride. The thickness of the tunnel insulation layer 14 is, for example, 3 nm or more and 8 nm or less.

[0159] The tunnel insulating layer 14 includes, for example, a lower layer, an intermediate layer, and an upper layer. The lower layer is disposed between the semiconductor layer 10 and the intermediate layer. The intermediate layer is disposed between the lower layer and the upper layer. The upper layer is disposed between the intermediate layer and the charge storage layer 16.

[0160] The lower layer is, for example, silicon oxide. The middle layer is, for example, silicon nitride or silicon oxynitride. The upper layer is, for example, silicon oxide.

[0161] A charge accumulation layer 16 is disposed between the tunnel insulating layer 14 and the first barrier insulating layer 18. The charge accumulation layer 16 surrounds the semiconductor layer 10.

[0162] The charge accumulation layer 16 has the function of capturing and storing charge, such as electrons. The threshold voltage of the memory cell transistor MT changes according to the amount of charge stored in the charge accumulation layer 16. By utilizing this change in threshold voltage, one memory cell can store data.

[0163] For example, the voltage at which the memory cell transistor MT is turned on changes by the threshold voltage change of the memory cell transistor MT. For example, when the state with a high threshold voltage is defined as data "0" and the state with a low threshold voltage is defined as data "1", the memory cell can store 1 bit of data, which is both "0" and "1".

[0164] The charge storage layer 16 contains silicon (Si) and nitrogen (N). The charge storage layer 16 may contain, for example, silicon nitride. The thickness of the charge storage layer 16 may be, for example, 3 nm or more and 10 nm or less.

[0165] like Figure 12 As shown, the charge storage layer 16 includes a first charge storage region 16a1 and a first inter-cell region 16b1. The first charge storage region 16a1 is disposed between the first gate electrode layer 11a and the semiconductor layer 10. The first inter-cell region 16b1 is disposed between the interlayer insulating layer 12 and the semiconductor layer 10.

[0166] The first charge accumulation region 16a1 contains silicon (Si) and nitrogen (N). The first charge accumulation region 16a1 may or may not contain fluorine (F). The first inter-unit region 16b1 contains silicon (Si), nitrogen (N), and fluorine (F). The fluorine concentration in the first inter-unit region 16b1 is higher than that in the first charge accumulation region 16a1.

[0167] The fluorine concentration in region 16b1 of inter-unit 1 is, for example, 1 × 10⁻⁶. 19 atoms / cm 3 Above and 1×10 20 atoms / cm 3 Below. Additionally, the fluorine concentration in the first charge accumulation region 16a1 is, for example, less than 1 × 10⁻⁶. 19 atoms / cm 3 .

[0168] The atomic ratio of nitrogen (N) to silicon (Si) in the charge accumulation layer 16 is, for example, 1.2 or more.

[0169] The atomic ratio (N / Si) of nitrogen (N) to silicon (Si) in the first charge accumulation region 16a1 is greater than that in the first inter-unit region 16b1.

[0170] The atomic ratio (N / Si) of nitrogen (N) to silicon (Si) in the first charge accumulation region 16a1 is, for example, 1.25 or more and 1.4 or less. In addition, the atomic ratio (N / Si) of nitrogen (N) to silicon (Si) in the first inter-unit region 16b1 is, for example, 1.2 or more and less than 1.25.

[0171] For example, by thermally diffusing fluorine from the fluorine-containing interlayer insulation layer 12, the fluorine concentration in the first inter-unit region 16b1 can be higher than the fluorine concentration in the first charge accumulation region 16a1.

[0172] like Figure 13 As shown, the charge storage layer 16 includes a first charge storage region 16a1, a second charge storage region 16a2, and a second inter-cell region 16b2. The second charge storage region 16a2 is disposed between the second gate electrode layer 11b and the semiconductor layer 10. The second inter-cell region 16b2 is disposed between the first charge storage region 16a1 and the second charge storage region 16a2. The second inter-cell region 16b2 is disposed between the trench insulating layer 13 and the semiconductor layer 10.

[0173] The first charge accumulation region 16a1 and the second charge accumulation region 16a2 contain silicon (Si) and nitrogen (N). The first charge accumulation region 16a1 and the second charge accumulation region 16a2 may or may not contain fluorine (F). The second inter-unit region 16b2 contains silicon (Si), nitrogen (N), and fluorine (F). The fluorine concentration in the second inter-unit region 16b2 is higher than the fluorine concentration in the first charge accumulation region 16a1 and the second charge accumulation region 16a2.

[0174] The fluorine concentration in region 16b2 of the second unit is, for example, 1 × 10⁻⁶. 19 atoms / cm 3 Above and 1×10 20 atoms / cm 3 The following is an explanation of the fluorine concentrations in the first charge accumulation region 16a1 and the second charge accumulation region 16a2, for example, are less than 1 × 10⁻⁶. 19 atoms / cm 3 .

[0175] The atomic ratio (N / Si) of nitrogen (N) to silicon (Si) in the first charge accumulation region 16a1 and the second charge accumulation region 16a2 is greater than that in the second inter-unit region 16b2.

[0176] The atomic ratio (N / Si) of nitrogen (N) to silicon (Si) in the first charge accumulation region 16a1 and the second charge accumulation region 16a2 is, for example, 1.25 or more and 1.4 or less. Furthermore, the atomic ratio (N / Si) of nitrogen (N) to silicon (Si) in the second inter-unit region 16b2 is, for example, 1.2 or more and less than 1.25.

[0177] For example, by thermally diffusing fluorine from the fluorine-containing trench insulation layer 13, the fluorine concentration in the second inter-unit region 16b2 can be higher than the fluorine concentration in the first charge accumulation region 16a1 and the second charge accumulation region 16a2.

[0178] A first barrier insulating layer 18 surrounds the semiconductor layer 10. The first barrier insulating layer 18 is disposed between the tunnel insulating layer 14 and the laminate 30. The first barrier insulating layer 18 is disposed between the tunnel insulating layer 14 and the first gate electrode layer 11a. The first barrier insulating layer 18 is disposed between the tunnel insulating layer 14 and the second gate electrode layer 11b. The first barrier insulating layer 18 is disposed between the tunnel insulating layer 14 and the third gate electrode layer 11c. The first barrier insulating layer 18 is disposed between the tunnel insulating layer 14 and the fourth gate electrode layer 11d.

[0179] A first barrier insulating layer 18 is disposed between the charge storage layer 16 and the first gate electrode layer 11a. A first barrier insulating layer 18 is disposed between the charge storage layer 16 and the second gate electrode layer 11b. A first barrier insulating layer 18 is disposed between the charge storage layer 16 and the third gate electrode layer 11c. A first barrier insulating layer 18 is disposed between the charge storage layer 16 and the fourth gate electrode layer 11d.

[0180] The first barrier insulating layer 18 is, for example, an oxide, a nitride, or a nitride. The first barrier insulating layer 18 contains, for example, silicon (Si) and oxygen (O). The first barrier insulating layer 18 is, for example, silicon oxide. The thickness of the first barrier insulating layer 18 is, for example, 3 nm or more and 10 nm or less.

[0181] The core insulating region 20 extends in the z-direction. The core insulating region 20 is surrounded by the semiconductor layer 10. The core insulating region 20 is columnar. For example, the core insulating region 20 is cylindrical.

[0182] The core insulating region 20 is, for example, an oxide, a nitride, or a nitride. The core insulating region 20 contains, for example, silicon (Si) and oxygen (O). The core insulating region 20 is, for example, silicon oxide.

[0183] The fourth embodiment of the three-dimensional NAND flash memory has a higher fluorine concentration in the first inter-cell region 16b1 and the second inter-cell region 16b2 of the charge accumulation layer 16 than the fluorine concentration in the first charge accumulation region 16a1 and the second charge accumulation region 16a2. Therefore, through the same effect as the first embodiment of the three-dimensional NAND flash memory, the charge retention characteristics are improved. Furthermore, through the same effect as the first embodiment of the three-dimensional NAND flash memory, threshold fluctuations of the memory cell transistor MT are suppressed.

[0184] According to the fourth embodiment, by making the fluorine concentration of the first inter-unit region 16b1 and the second inter-unit region 16b2 of the charge storage layer 16 higher than the fluorine concentration of the first charge storage region 16a1 and the second charge storage region 16a2, the lateral detachment of electrons is suppressed, and a semiconductor memory device with improved charge retention characteristics can be provided.

[0185] (Fifth Embodiment)

[0186] The semiconductor memory device of the fifth embodiment differs from that of the semiconductor memory device of the fourth embodiment in that it further includes a fourth insulating layer. This fourth insulating layer is disposed between the first gate electrode layer and the third insulating layer, and between the gate electrode layer and the first insulating layer. It includes a fifth region between the first gate electrode layer and the third insulating layer, and a sixth region between the first gate electrode layer and the first insulating layer. The fifth region may or may not contain fluorine (F), while the sixth region contains fluorine (F), and the fluorine concentration in the sixth region is higher than that in the fifth region. Hereinafter, descriptions that are repeated in the first or fourth embodiment will sometimes be omitted.

[0187] Figure 14 , Figure 15 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the fifth embodiment. Figure 14 This is the xy profile of the storage cell array 500. Figure 14 It includes Figure 15 A cross-section of the BB' face. Figure 15 This is the yz profile of the storage cell array 400. Figure 15 yes Figure 14 AA' section.

[0188] exist Figure 14 and Figure 15 In the diagram, the area enclosed by a dashed line represents a storage unit. Figure 15 and Figure 14 The example shows memory cells MC1 and MC2 that are adjacent in the y-direction.

[0189] Figure 16This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the fifth embodiment. Figure 16 This is a partially enlarged cross-sectional view of the storage cell. Figure 16 yes Figure 15 A magnified view of a portion of the image.

[0190] Figure 17 This is a schematic cross-sectional view of the memory cell of the semiconductor memory device according to the fifth embodiment. Figure 17 yes Figure 14 A magnified view of a portion of the image.

[0191] The memory cell array 500 includes a semiconductor layer 10, a first gate electrode layer 11a, a second gate electrode layer 11b, a third gate electrode layer 11c, a fourth gate electrode layer 11d, an interlayer insulating layer 12, a trench insulating layer 13, a tunnel insulating layer 14, a charge accumulation layer 16, a first barrier insulating layer 18, a second barrier insulating layer 19, and a core insulating region 20. The charge accumulation layer 16 includes a first charge accumulation region 16a1, a second charge accumulation region 16a2, a first inter-cell region 16b1, and a second inter-cell region 16b2. The second barrier insulating layer 19 includes a barrier region 19a, a first inter-layer region 19b1, and a second inter-layer region 19b2.

[0192] Interlayer insulation layer 12 is an example of the first insulation layer. Trench insulation layer 13 is an example of the fifth insulation layer. Tunnel insulation layer 14 is an example of the second insulation layer. First barrier insulation layer 18 is an example of the third insulation layer. Charge accumulation layer 16 is an example of the first layer. First charge accumulation region 16a1 is an example of the first region. Second charge accumulation region 16a2 is an example of the third region. First inter-unit region 16b1 is an example of the second region. Second inter-unit region 16b2 is an example of the fourth region. Barrier region 19a is an example of the fifth region. First interlayer region 19b1 is an example of the sixth region. Second interlayer region 19b2 is an example of the seventh region.

[0193] The second barrier insulating layer 19 is disposed between the first gate electrode layer 11a and the first barrier insulating layer 18. The second barrier insulating layer 19 is disposed between the second gate electrode layer 11b and the first barrier insulating layer 18. The second barrier insulating layer 19 is disposed between the third gate electrode layer 11c and the first barrier insulating layer 18. The second barrier insulating layer 19 is disposed between the fourth gate electrode layer 11d and the first barrier insulating layer 18.

[0194] The second barrier insulating layer 19 is disposed between the first gate electrode layer 11a and the interlayer insulating layer 12. The second barrier insulating layer 19 is disposed between the second gate electrode layer 11b and the interlayer insulating layer 12. The second barrier insulating layer 19 is disposed between the third gate electrode layer 11c and the interlayer insulating layer 12. The second barrier insulating layer 19 is disposed between the fourth gate electrode layer 11d and the interlayer insulating layer 12.

[0195] The second barrier insulating layer 19 is disposed between the first gate electrode layer 11a and the trench insulating layer 13. The second barrier insulating layer 19 is disposed between the second gate electrode layer 11b and the trench insulating layer 13. The second barrier insulating layer 19 is disposed between the third gate electrode layer 11c and the trench insulating layer 13. The second barrier insulating layer 19 is disposed between the fourth gate electrode layer 11d and the trench insulating layer 13.

[0196] The second barrier insulating layer 19 has the function of preventing the current flowing between the charge accumulation layer 16 and the gate electrode layer.

[0197] The second barrier insulating layer 19 is, for example, an oxide, a nitride, or a nitride. The second barrier insulating layer 19 may contain, for example, aluminum (Al) and oxygen (O). The second barrier insulating layer 19 may be, for example, aluminum oxide. The thickness of the second barrier insulating layer 19 is, for example, 3 nm or more and 10 nm or less.

[0198] By providing a second barrier insulating layer 19, the charge retention characteristics of the three-dimensional NAND flash memory are further improved compared to the fourth embodiment.

[0199] like Figure 16 As shown, the second barrier insulating layer 19 includes a barrier region 19a and a first interlayer region 19b1. The barrier region 19a is disposed between the first gate electrode layer 11a and the first barrier insulating layer 18. The first interlayer region 19b1 is disposed between the first gate electrode layer 11a and the interlayer insulating layer 12.

[0200] Barrier region 19a contains aluminum (Al) and oxygen (O). Barrier region 19a may or may not contain fluorine (F). Interlayer region 19b1 contains aluminum (Al), oxygen (O), and fluorine (F). The fluorine concentration in interlayer region 19b1 is higher than that in barrier region 19a.

[0201] For example, by thermally diffusing fluorine from the fluorine-containing interlayer insulation layer 12, the fluorine concentration in the first interlayer region 19b1 can be higher than the fluorine concentration in the barrier region 19a.

[0202] like Figure 17As shown, the second barrier insulating layer 19 includes a barrier region 19a and a second interlayer region 19b2. The barrier region 19a is disposed between the first gate electrode layer 11a and the first barrier insulating layer 18. The second interlayer region 19b2 is disposed between the first gate electrode layer 11a and the trench insulating layer 13.

[0203] Barrier region 19a contains aluminum (Al) and oxygen (O). Barrier region 19a may or may not contain fluorine (F). Interlayer region 19b2 contains aluminum (Al), oxygen (O), and fluorine (F). The fluorine concentration in interlayer region 19b2 is higher than that in barrier region 19a.

[0204] For example, by thermally diffusing fluorine from the fluorine-containing trench insulation layer 13, the fluorine concentration in the second interlayer region 19b2 can be higher than the fluorine concentration in the barrier region 19a.

[0205] By increasing the fluorine concentration in the first interlayer region 19b1 and the second interlayer region 19b2, the dielectric constant of the first interlayer region 19b1 and the second interlayer region 19b2 is reduced. Therefore, the capacitance between the gate electrode layers is reduced. This reduces the power consumption of the 3D NAND flash memory. Furthermore, the 3D NAND flash memory can be made faster.

[0206] According to the fifth embodiment, a semiconductor memory device with improved charge retention characteristics can be provided in the same manner as the first and fourth embodiments.

[0207] In the first to fifth embodiments, the case in which an interlayer insulating layer 12 is provided between the word line WL or the gate electrode layer is described as an example, but the space between the word line WL or the gate electrode layer may also be a void.

[0208] Applying the same first barrier insulating layer 18 containing a ferroelectric material as in the third embodiment to the semiconductor memory device of the second embodiment yields the same effect as in the third embodiment. Furthermore, applying the same first barrier insulating layer 18 containing a ferroelectric material as in the third embodiment to the semiconductor memory devices of the fourth and fifth embodiments also yields the same effect as in the third embodiment. Moreover, by providing a ferroelectric region in the first barrier insulating layer 18 between the trench insulating layer 13 and the second cell region 16b2, electrons trapped by the trapping energy level of the second cell region 16b2 are attracted by the ferroelectric region, and the movement of electrons in the second cell region 16b2 is suppressed. Therefore, lateral electron detachment is further suppressed, and the charge retention characteristics of the three-dimensional NAND flash memory are further improved.

[0209] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified to be constituent elements of other embodiments. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: A laminate formed by alternately stacking a gate electrode layer and a first insulating layer in a first direction; A semiconductor layer disposed in the laminate and extending in the first direction; A second insulating layer is disposed between the semiconductor layer and the laminate; A third insulating layer is disposed between the second insulating layer and the laminate; A first layer, disposed between the second and third insulating layers, contains silicon (Si) and nitrogen (N), including a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer. The first region may or may not contain fluorine (F), while the second region contains fluorine (F), with a higher fluorine concentration in the second region than in the first region. The fourth insulating layer is disposed between the gate electrode layer and the third insulating layer and between the gate electrode layer and the first insulating layer, and includes a third region between the gate electrode layer and the third insulating layer and a fourth region between the gate electrode layer and the first insulating layer. The third region contains fluorine (F) or does not contain fluorine (F), and the fourth region contains fluorine (F). The fluorine concentration in the fourth region is higher than that in the third region.

2. The semiconductor memory device according to claim 1, The fluorine concentration in the second region is 1×10⁻⁶. 20 atoms / cm 3 the following.

3. The semiconductor memory device according to claim 1 or 2, The atomic ratio of nitrogen (N) to silicon (Si) in the first layer, i.e., N / Si, is 1.2 or higher.

4. The semiconductor memory device according to claim 1, The atomic ratio of nitrogen (N) to silicon (Si) in the first region is greater than that in the second region.

5. The semiconductor memory device according to claim 4, The atomic ratio of nitrogen (N) to silicon (Si) in the first region is 1.25 or more, and the atomic ratio of nitrogen (N) to silicon (Si) in the second region is 1.2 or more and less than 1.

25.

6. The semiconductor memory device according to claim 1, The first insulating layer contains fluorine.

7. The semiconductor memory device according to claim 1, The first insulating layer contains silicon (Si) and oxygen (O), and the fourth insulating layer contains aluminum (Al) and oxygen (O).

8. The semiconductor memory device according to claim 1, The third insulating layer contains ferroelectric material in at least the region between the first insulating layer and the first layer.

9. The semiconductor memory device according to claim 8, The third insulating layer contains a paraelectric material in the region between the gate electrode layer and the first layer.

10. A semiconductor memory device comprising: A first gate electrode layer, which extends in a first direction; A second gate electrode layer extends in the first direction and is adjacent to the first gate electrode layer in a second direction that intersects the first direction; A semiconductor layer is disposed between the first gate electrode layer and the second gate electrode layer, and extends in a third direction intersecting the first direction and the second direction; A third gate electrode layer extends in the first direction and is adjacent to the first gate electrode layer in the third direction; A first insulating layer is disposed between the first gate electrode layer and the third gate electrode layer; A second insulating layer is disposed between the semiconductor layer and the first gate electrode layer and between the semiconductor layer and the first insulating layer; A third insulating layer is disposed between the second insulating layer and the first gate electrode layer, and between the second insulating layer and the first insulating layer; A first layer, disposed between the second and third insulating layers, contains silicon (Si) and nitrogen (N), including a first region between the first gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer. The first region may or may not contain fluorine (F), while the second region contains fluorine (F), with a higher fluorine concentration in the second region than in the first region. The fourth insulating layer is disposed between the first gate electrode layer and the third insulating layer, and between the first gate electrode layer and the first insulating layer. It includes a fifth region between the first gate electrode layer and the third insulating layer and a sixth region between the first gate electrode layer and the first insulating layer. The fifth region contains fluorine (F) or does not contain fluorine (F), and the sixth region contains fluorine (F). The fluorine concentration in the sixth region is higher than that in the fifth region.

11. The semiconductor memory device according to claim 10, The fluorine concentration in the second region is 1×10⁻⁶. 20 atoms / cm 3 the following.

12. The semiconductor memory device according to claim 10 or 11, The atomic ratio of nitrogen (N) to silicon (Si) in the first layer, i.e., N / Si, is 1.2 or higher.

13. The semiconductor memory device according to claim 10 or 11, The atomic ratio of nitrogen (N) to silicon (Si) in the first region is greater than that in the second region.

14. The semiconductor memory device according to claim 13, The atomic ratio of nitrogen (N) to silicon (Si) in the first region is 1.25 or more, and the atomic ratio of nitrogen (N) to silicon (Si) in the second region is 1.2 or more and less than 1.

25.

15. The semiconductor memory device according to claim 10 or 11, The first insulating layer contains fluorine.

16. The semiconductor memory device according to claim 10 or 11, The first layer further includes a third region between the second gate electrode layer and the semiconductor layer and a fourth region between the first region and the third region. The third region contains fluorine (F) or does not contain fluorine (F), and the fourth region contains fluorine (F). The fluorine concentration in the fourth region is higher than that in the first region and the fluorine concentration in the fourth region is higher than that in the third region.

17. The semiconductor memory device according to claim 10, The first insulating layer contains silicon (Si) and oxygen (O), and the fourth insulating layer contains aluminum (Al) and oxygen (O).

18. The semiconductor memory device according to claim 10, It also includes a fifth insulating layer, which is disposed between the first gate electrode layer and the second gate electrode layer. The fourth insulating layer further includes a seventh region between the first gate electrode layer and the fifth insulating layer. The seventh region contains fluorine, i.e., F, and the fluorine concentration in the seventh region is higher than that in the fifth region.

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