Display device

Abstract

A display device is provided. The display device includes a substrate having a display area provided with a display element to display an image and a non-display area surrounding the display area. The non-display area includes a bending area bent with respect to a bending axis; an encapsulation layer is disposed over the display area; a touch electrode is disposed over the encapsulation layer; a touch wiring is connected to the touch electrode and extends to the non-display area; a fan-out wiring is connected to a signal wiring that applies an electrical signal to the display area. At least a portion of the fan-out wiring is disposed in the bending area, the fan-out wiring including a same material as a material of the touch wiring.

Description

[0001] This application is a divisional application of the invention patent application filed on March 10, 2017, with application number 201710140850.5 and entitled "Display Device and Manufacturing Method Thereof".

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2016-0029716, filed on March 11, 2016, and Korean Patent Application No. 10-2016-0110091, filed on August 29, 2016, both of which are incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] An exemplary embodiment relates to a display device and a method of manufacturing the same. Background Technology

[0004] A display device for visually displaying data includes a substrate divided into display areas and non-display areas. In the display areas, gate lines and data lines are insulated from each other, and multiple pixel areas are defined by the intersection of the gate lines and data lines. Additionally, thin-film transistors (TFTs) and pixel electrodes electrically connected to the TFTs are disposed in the display areas, corresponding to the pixel areas. The non-display areas include pads and fan-out units. The fan-out units include wiring connecting the pads to the display areas and transmitting signals from a driver integrated circuit (IC) disposed on the pads via the wiring.

[0005] At least a portion of the display device can be bent to enhance visibility at various angles or reduce the size of non-display areas. Various technologies are being developed to reduce costs and defects during the manufacture of bent display devices.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the background of the inventive concept and may therefore contain information that does not constitute prior art known in the country to a person skilled in the art. Summary of the Invention

[0007] Exemplary embodiments of the present invention provide a display device with improved durability and low manufacturing cost. In the exemplary embodiments, various defects such as short circuits that can occur during various manufacturing processes can be prevented. The exemplary embodiments also include a method of manufacturing the display device.

[0008] Other aspects will be set forth in part in the following description, and in part will be apparent from disclosure or may become known by practice of the inventive concept.

[0009] An exemplary embodiment discloses a display device comprising: a substrate including a display area on which display devices are disposed for displaying an image and a non-display area disposed around the display area, wherein the non-display area includes a curved area curved about a bending axis; an encapsulation layer disposed above the display area; touch electrodes disposed above the encapsulation layer; touch wiring connected to the touch electrodes and extending into the non-display area; and fan-out wiring connected to signal wiring that applies electrical signals to the display area. At least a portion of the fan-out wiring is disposed in the curved area, and the fan-out wiring comprises the same material as the touch wiring.

[0010] An exemplary embodiment also discloses a display device, the display device comprising: a substrate including a display area disposed on a display device for displaying an image and a non-display area disposed around the display area, wherein the non-display area may include a curved area curved about a bending axis; an encapsulation layer disposed above the display area; a touch electrode disposed above the encapsulation layer; touch wiring connected to the touch electrode and extending to the non-display area; signal wiring disposed between the curved area and the display area and applying an electrical signal; a terminal disposed on one side of the non-display area; and a fan-out wiring disposed at least partially in the curved area and having one side connected to the signal wiring via a through-hole and the other side connected to the terminal. The fan-out wiring may include the same material as the touch wiring.

[0011] The foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed subject matter. Attached Figure Description

[0012] The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. The drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification.

[0013] Figure 1 This is a perspective view schematically showing a portion of a display device according to an exemplary embodiment.

[0014] Figure 2A This is a perspective view schematically showing a portion of a display device according to an exemplary embodiment.

[0015] Figure 2B This is a plan view schematically showing a portion of a display device according to an exemplary embodiment.

[0016] Figure 2C It is shown schematically. Figure 2A A cross-sectional view of a portion of the display device.

[0017] Figure 3AThis is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0018] Figure 3B This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0019] Figure 4A This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0020] Figure 4B This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0021] Figure 4C This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0022] Figure 4D This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0023] Figure 4E This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0024] Figure 4F This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0025] Figure 4G This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0026] Figure 4H This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0027] Figure 4I This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0028] Figure 5A This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0029] Figure 5B This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0030] Figure 5C This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0031] Figure 5D This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0032] Figure 5E This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0033] Figure 5F This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0034] Figure 5G This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0035] Figure 5H This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0036] Figure 5I This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0037] Figure 5J This is a plan view schematically showing a portion of a display device according to an exemplary embodiment.

[0038] Figure 5K This is a plan view schematically showing a portion of a display device according to an exemplary embodiment.

[0039] Figure 6A This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0040] Figure 6B This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment.

[0041] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G , Figure 7H and Figure 7I This is a cross-sectional view showing a method of manufacturing a display device according to an exemplary embodiment. Detailed Implementation

[0042] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of the various exemplary embodiments. However, it is clear that the various exemplary embodiments may be implemented without these specific details or in one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments.

[0043] In the accompanying drawings, the dimensions and relative dimensions of layers, films, panels, areas, etc., may be exaggerated for clarity and descriptive purposes. Furthermore, the same reference numerals denote the same elements.

[0044] When an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to," there are no intermediate elements or intermediate layers. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. The same reference numerals always denote the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms first, second, etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and / or part from another element, component, region, layer, and / or part. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part.

[0046] For descriptive purposes, spatially relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship of an element or feature to other elements or features as shown in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as “below” or “below” other elements or features would then be positioned “above” other elements or features. Thus, the exemplary term “below” can include both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatially relative descriptive terms used herein accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] Various exemplary embodiments are described herein with reference to cross-sectional views that serve as schematic representations of ideal exemplary embodiments and / or intermediate structures. Thus, variations in the shapes illustrated are expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the shapes of the specifically shown areas, but will include, for example, deviations in shape due to manufacturing processes. The areas shown in the figures are purely schematic, and their shapes are not intended to represent, nor are they intended to limit, the actual shapes of the areas of the device.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0050] In the examples below, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0051] When an embodiment can be implemented differently, a particular process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0052] Display devices are devices used to display images, such as liquid crystal display (LCD) devices, electrophoretic display devices, organic light-emitting display devices, inorganic light-emitting display devices, field emission display (FED) devices, surface conduction electron emission (SED) display devices, plasma display devices, or cathode ray display devices, etc.

[0053] In the following description, the organic light-emitting display device is used as an example of a display device according to an exemplary embodiment. However, the display device is not limited thereto, and may include various types of display devices.

[0054] Figure 1 and Figure 2A This is a perspective view schematically showing a portion of a display device according to an exemplary embodiment. Figure 2B This is a plan view schematically showing a portion of a display device according to an exemplary embodiment. Figure 2C It is shown schematically. Figure 2A A cross-sectional view of a portion of the display device. For example... Figure 1 As shown, because the substrate 100 in the display device is partially bent, a portion of the display device according to this exemplary embodiment is bent. For ease of description, Figure 2C The display device is shown in a non-bent state. For ease of description, the cross-sectional and plan views relating to the exemplary embodiments disclosed below also show the display device in a non-bent state.

[0055] like Figures 1 to 2C As shown, the substrate 100 of the display device according to this exemplary embodiment is divided into a display area DA on which display devices are disposed and images are displayed, and a non-display area surrounding the display area DA. The non-display area includes a curved area BA that is curved about a bending axis BAX. The curved area BA may refer to a curved area having a radius of curvature.

[0056] The curved region BA extends in a first direction (+y direction) and is arranged between the first region 1A and the second region 2A along a second direction (+x direction) intersecting the first direction. Furthermore, the base 100 is curved about the curved axis BAX extending in the first direction (+y direction), as follows: Figure 1 As shown in the figure. The substrate 100 may include a variety of flexible or bendable materials, such as polymeric resins, such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0057] The first region 1A includes the display region DA. In addition to the display region DA, the first region 1A may also include a portion of non-display areas surrounding or located outside the display region DA, such as... Figure 2C As shown in the diagram. The second region 2A also includes non-display areas.

[0058] Multiple pixels for displaying an image can be disposed in a display area DA of the substrate 100. The display area DA may include, for example, a display device 300, a thin-film transistor (TFT) 210, and a capacitor Cst (not shown).

[0059] Reference Figures 2A to 2CThe display area DA may also include signal wiring for transmitting pulse signals and DC signals, such as drive power lines and common power lines. The signal wiring includes gate lines for transmitting gate signals, data lines for transmitting data signals, etc. (all not shown). Pixels can be formed, and the pixels can display images based on electrical combinations of TFTs, capacitors, display devices, etc., connected to the gate lines, data lines, and drive power lines. The brightness of the pixel can correspond to the drive current flowing through the display device in response to the data signal based on the drive power and common power supplied to the pixel. The signal wiring can be connected to the terminal unit 20 via fan-out wiring 720a. That is, fan-out wiring 720a can transmit pulse signals such as gate signals and data signals, and DC current such as power. Multiple pixels can be provided, and the multiple pixels can be arranged in various ways, such as a stripe layout or a PenTile layout. TM Layout, etc.

[0060] Terminal unit 20, fan-out wiring 720a, additional conductive layer 215d, and touch wiring 720 can be arranged in the non-display area. Although not shown, common power lines, drive power lines, gate drive units, data drive units, etc., can be further arranged in the non-display area.

[0061] Terminal unit 20 may be disposed at one end of the non-display area and may include signal terminals 21 and touch terminals 22. Terminal unit 20 may not be covered by an insulating layer and may be exposed, allowing terminal unit 20 to be electrically connected to drive circuit units (not shown), such as flexible printed circuit boards (FPCBs), driver ICs, etc. The control unit may provide data signals, gate signals, drive voltage DLVDD, common voltage ELVSS, etc. The control unit may also provide signals to the touch screen layer 700 via touch wiring 720, or may receive signals sensed by the touch screen layer 700.

[0062] Fan-out wiring 720a is located in the non-display area and connected to the TFT 210 in the display area DA or the first signal wiring 213b that applies electrical signals to the display device 300. As described above, the first signal wiring 213b may correspond to various lines disposed in the display area DA, such as gate lines, data lines, drive power lines, or common power lines. Fan-out wiring 720a may be connected to the first signal wiring 213b, and at least a portion of fan-out wiring 720a may be located in the curved area BA. In some embodiments, fan-out wiring 720a may extend from the first area 1A and within a portion of the curved area BA, or extend through the curved area BA to the second area 2A. That is, fan-out wiring 720a may extend through the curved axis BAX. For example, fan-out wiring 720a may have various modifications, such as extending at a predetermined angle to the curved axis BAX. Fan-out wiring 720a may have various shapes, such as curved shapes, sawtooth shapes, etc. (in addition to straight shapes).

[0063] Fan-out wiring 720a can be connected to signal terminal 21 of terminal unit 20 to transmit electrical signals to display area DA.

[0064] An additional conductive layer 215d may be further disposed in the non-display area. The additional conductive layer 215d may be connected to signal lines, such as fan-out wiring 720a, that apply electrical signals to the TFT 210 or display device 300 disposed in the display area DA. The additional conductive layer 215d may comprise a material different from that of the fan-out wiring 720a. For example, the additional conductive layer 215d may comprise the same material as the gate line or data line that serves as an internal signal line in the display area DA. The additional conductive layer 215d may be disposed in a layer different from that of the fan-out wiring 720a, such as... Figure 2B As shown, the additional conductive layer 215d can be horizontally separated from the fan-out wiring 720a. However, the arrangement of the additional conductive layer 215d is not limited to this. The additional conductive layer 215d can at least partially overlap with the fan-out wiring 720a. For example, the additional conductive layer 215d can be electrically connected to the fan-out wiring 720a in the lower part of the fan-out wiring 720a to apply electrical signals to the display area DA. Another exemplary embodiment regarding the layout of the additional conductive layer 215d and the fan-out wiring 720a will be described below.

[0065] In addition to the fan-out wiring 720a, the display device according to this exemplary embodiment may include a first signal wiring 213b connected to the fan-out wiring 720a. In order to place the first signal wiring 213b in a different layer than the layer in which the fan-out wiring 720a is located, the first signal wiring 213b may be arranged in a first region 1A or a second region 2A and may be electrically connected to the fan-out wiring 720a.

[0066] The first signal wiring 213b can be electrically connected to the TFT 210 included in the display area DA. Therefore, the fan-out wiring 720a can be electrically connected to the TFT 210 included in the display area DA through the first signal wiring 213b. In this way, the first signal wiring 213b can be located outside the display area DA while being electrically connected to components located in the display area DA, and can be located outside the display area DA while extending in the direction of the display area DA. Therefore, the first signal wiring 213b can be at least partially located in the display area DA.

[0067] The display area DA can be sealed by the encapsulation layer 400. The encapsulation layer 400 can cover the display device 300 and other components in the display area DA, and protect the display device 300 and other components from external moisture or oxygen. The encapsulation layer 400 can cover the display area DA and partially extend to the outside of the display area DA.

[0068] A touchscreen layer 700 is provided on the encapsulation layer 400, including touch electrodes 710 with various patterns for touchscreen functionality. The touch electrodes 710 can be connected to touch wiring 720, through which signals detected by the touch electrodes 710 are transmitted. The touch wiring 720 can extend from the upper part of the encapsulation layer 400 along one side of the encapsulation layer 400 to a non-display area. The touch wiring 720 can be connected to the touchscreen layer 700 and extends from the upper part of the encapsulation layer 400 until at least a portion of the touch wiring 720 is located in a curved region BA.

[0069] Figure 2C An organic light-emitting device (also referred to as a display device) 300 is shown in the display area DA. The organic light-emitting device 300 is electrically connected to the TFT 210, which may refer to the pixel electrode 310 being electrically connected to the TFT 210. If necessary, another TFT (not shown) may be disposed in the surrounding area outside the display area DA of the substrate 100. The TFT disposed in the surrounding area may be, for example, part of a circuit unit for controlling electrical signals applied to the display area DA.

[0070] TFT 210 may include a semiconductor layer 211, which may include amorphous silicon, polycrystalline silicon, oxide semiconductor material, or organic semiconductor material. TFT 210 may also include a gate electrode 213, a source electrode 215a, and a drain electrode 215b.

[0071] The gate electrode 213 may be connected to a gate line (not shown) that applies on and off signals to the TFT 210. The gate electrode 213 may comprise a low-resistance metallic material. For example, the gate electrode 213 may be a single layer or multiple layers formed of a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti).

[0072] Each of the source electrode 215a and drain electrode 215b may be a single layer or multiple layers comprising a conductive material. The source electrode 215a and drain electrode 215b may be connected to the source region and drain region of the semiconductor layer 211, respectively. For example, each of the source electrode 215a and drain electrode 215b may be a single layer or multiple layers formed of a conductive material comprising, for example, Al, Cu and / or Ti.

[0073] According to an exemplary embodiment, the TFT 210 may be a top-gate TFT with the gate electrode 213 located above the semiconductor layer 211. However, other exemplary embodiments of the TFT 210 are not limited thereto. According to another exemplary embodiment, the TFT 210 may be a bottom-gate TFT with the gate electrode 213 located below the semiconductor layer 211.

[0074] To insulate the semiconductor layer 211 from the gate electrode 213, a gate insulating layer 120 may be disposed between the semiconductor layer 211 and the gate electrode 213. The gate insulating layer 120 comprises an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. Additionally, an interlayer insulating layer 130 may be disposed above the gate electrode 213. The interlayer insulating layer 130 comprises an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The source electrode 215a and drain electrode 215b may be disposed above the interlayer insulating layer 130. The insulating layer comprising inorganic material can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This also applies to the exemplary embodiments and modified examples of the exemplary embodiments described below.

[0075] A buffer layer 110 may be disposed between the TFT 210 and the substrate 100. The buffer layer 110 comprises an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The buffer layer 110 may planarize the upper surface of the substrate 100 or prevent impurities from penetrating from the substrate 100 into the semiconductor layer 211 of the TFT 210. The buffer layer 110 may have a single-layer structure or a multi-layer structure.

[0076] The planarization layer 140 can be disposed above the TFT 210. For example, as Figure 2C As shown, when the organic light-emitting device 300 is disposed above the TFT 210, the planarization layer 140 can planarize the upper part of the protective layer covering the TFT 210. The planarization layer 140 may include organic materials such as PI, acrylic, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO), although... Figure 2C The planarization layer 140 is shown as a single layer, but the planarization layer 140 can be multiple layers or modified in various other ways.

[0077] In the display area DA of the substrate 100, an organic light-emitting device 300 can be disposed on the planarization layer 140. The organic light-emitting device 300 may include a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 disposed between the pixel electrode 310 and the counter electrode 330 and including an emission layer. Figure 2C As shown, the pixel electrode 310 can be electrically connected to the TFT 210 by means of an opening formed in the planarization layer 140 to contact either the source electrode 215a or the drain electrode 215b.

[0078] A pixel defining layer 150 may be disposed above the planarization layer 140. The pixel defining layer 150 defines pixels using openings corresponding to sub-pixels (i.e., openings that at least expose the central portion of the pixel electrode 310). Figure 2C In this process, the pixel defining layer 150 on the pixel electrode 310 can increase the distance between the periphery of the pixel electrode 310 and the counter electrode 330, so that electric arcs are not generated at the periphery of the pixel electrode 310. The pixel defining layer 150 may include, for example, PI, acrylic, BCB, or HMDSO.

[0079] The intermediate layer 320 of the organic light-emitting device 300 may comprise a low-molecular-weight material or a high-molecular-weight material. When the intermediate layer 320 comprises a low-molecular-weight material, it may comprise an emitter layer (EML), and may further comprise at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). The intermediate layer 320 may comprise various organic materials, such as copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), or tris-8-hydroxyquinoline-aluminum (Alq3), etc. The layer may be formed by vapor deposition.

[0080] When the intermediate layer 320 comprises a polymer material, it may include an HTL and an EML. The HTL may include PEDOT, and the EML may include polyphenylenevinyl chloride (PPV) and polyfluorene polymer materials. The intermediate layer 320 may be formed by screen printing, inkjet printing, or laser-induced thermal imaging (LITI).

[0081] However, the intermediate layer 320 is not limited to the example above. The intermediate layer 320 may include a single layer spanning multiple pixel electrodes 310 or multiple layers patterned relative to each of the pixel electrodes 310.

[0082] The counter electrode 330 is located in the upper part of the display area DA. For example... Figure 2CAs shown, the counter electrode 330 can be configured to cover the display area DA. That is, the counter electrode 330 can be formed as a single element for a plurality of organic light-emitting devices 300, and thus the counter electrode 330 corresponds to a plurality of pixel electrodes 310.

[0083] Because such organic light-emitting devices are easily damaged by external moisture or oxygen, the encapsulation layer 400 covers and protects the organic light-emitting device. The encapsulation layer 400 can cover the pixel area and extend to the area outside the pixel area. Figure 2C As shown, the encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0084] The first inorganic encapsulation layer 410 may cover the counter electrode 330 and includes silicon oxide, silicon nitride, and / or silicon oxynitride. If necessary, other layers, such as a capping layer, may be disposed between the first inorganic encapsulation layer 410 and the counter electrode 330. Because the first inorganic encapsulation layer 410 is formed along its underlying structure, the upper surface of the first inorganic encapsulation layer 410 is not flat, such as… Figure 2C As shown in the diagram. Unlike the first inorganic encapsulation layer 410, the organic encapsulation layer 420 covering the first inorganic encapsulation layer 410 may have a flat upper surface. Specifically, the upper surface of the organic encapsulation layer 420 corresponding to the display area DA may be substantially flat. The organic encapsulation layer 420 may include at least one selected from the group consisting of PET, PEN, PC, PI, PES, polyoxymethylene (POM), polyarylate, and HMDSO. The second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420 and includes silicon oxide, silicon nitride, and / or silicon oxynitride. The periphery of the second inorganic encapsulation layer 430 located outside the display area DA may contact the first inorganic encapsulation layer 410, such that the organic encapsulation layer 420 is not exposed to the outside.

[0085] Because the encapsulation layer 400 has a multilayer structure including a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430, even if cracks exist in the encapsulation layer 400, the cracks will not extend between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, external moisture or oxygen can be prevented from penetrating into the display area DA.

[0086] A touchscreen layer 700, including touch electrodes 710, is disposed above the encapsulation layer 400. A cover layer 730 may be disposed above the touchscreen layer 700 and protect the touchscreen layer 700.

[0087] The touchscreen layer 700 can be, for example, capacitive. When the cover layer 730 is touched, it can be determined whether a partial touch has occurred by detecting changes in the mutual capacitance between the touch electrodes 710 formed on the touchscreen layer 700. Alternatively, the touchscreen layer 700 can determine whether a partial touch has occurred by detecting changes in the capacitance between the touch electrodes 710 and the counter electrode 330, or by other techniques.

[0088] Touch electrode 710 can be connected to touch wiring 720 for transmitting signals detected by touch electrode 710. Touch wiring 720 can extend from the upper portion of encapsulation layer 400 along one side of encapsulation layer 400 to a non-display area. Touch wiring 720 can be connected to touchscreen layer 700 and extends from the upper portion of encapsulation layer 400 until at least a portion of touch wiring 720 is in curved region BA. In an exemplary embodiment, touch wiring 720 can be arranged to pass through curved region BA. Touch wiring 720 can extend from the encapsulation layer 400 along one side of encapsulation layer 400, in which case that side of encapsulation layer 400 can be curved. This curvature can be formed due to steps formed by planarization layer 140 and pixel defining layer 150, such as... Figure 2C As shown in the diagram. Due to this curvature, the touch wiring 720 can extend from the top of the encapsulation layer 400 to the non-sealed area with a gradually changing slope.

[0089] Each of the touch electrode 710 and the touch wiring 720 may be a single layer or multiple layers of a conductive material comprising, for example, Al, Cu, and / or Ti. The touch electrode 710 and the touch wiring 720 may comprise the same material.

[0090] The cover layer 730 can be flexible and includes materials such as polymethyl methacrylate, polydimethylsiloxane, PI, acrylate, PET, or PEN. The cover layer 730 can be disposed above the touch screen layer 700 to protect the touch screen layer 700.

[0091] A touch buffer layer 610 can be disposed between the encapsulation layer 400 and the touch screen layer 700. The touch buffer layer 610 prevents damage to the encapsulation layer 400 and blocks interference signals generated during operation of the touch screen layer 700. The touch buffer layer 610 can comprise inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride) or organic materials (such as PI, polyester, or acrylic). Alternatively, the touch buffer layer 610 can be formed by stacking layers of the above materials.

[0092] The touch buffer layer 610 can be formed directly on the encapsulation layer 400 by deposition or other methods. Since the touch screen layer 700 is also formed directly on the touch buffer layer 610, an additional adhesion layer does not need to be located on the encapsulation layer 400. Therefore, the thickness of the display device can be reduced.

[0093] The non-display area may include a curved area BA. Fan-out wiring 720a may be configured to pass through the curved area BA in the non-display area. Fan-out wiring 720a may be electrically connected to the TFT 210 or electrically connected to the first signal wiring 213b, the second signal wiring 213c, and the third signal wiring 215c that apply electrical signals to the display device 300 disposed in the display area DA. The fan-out wiring 720a electrically connected to the first signal wiring 213b, the second signal wiring 213c, and the third signal wiring 215c does not only refer to the fan-out wiring 720a passing through... Figure 2C The contact hole shown is directly connected to the first signal wiring 213b, and also indicates that the fan-out wiring 720a is indirectly connected to the second signal wiring 213c or the third signal wiring 215c via the first signal wiring 213b.

[0094] The first signal wiring 213b can be electrically connected to the second signal wiring 213c or the third signal wiring 215c in the display area DA. In an exemplary embodiment, the second signal wiring 213c or the third signal wiring 215c can be a gate line that applies a signal to the gate electrode 213. In an exemplary embodiment, the second signal wiring 213c or the third signal wiring 215c can be a data line that applies a signal to the source electrode 215a or the drain electrode 215b. In an exemplary embodiment, the first signal wiring 213b can be connected to the second signal wiring 213c through a via.

[0095] In an exemplary embodiment, the first signal wiring 213b and the second signal wiring 213c may comprise the same material as the gate electrode 213. The third signal wiring 215c may comprise the same material as the source electrode 215a and the drain electrode 215b.

[0096] The fan-out wiring 720a may comprise the same material as the touch wiring 720. The fan-out wiring 720a and the touch wiring 720 may be formed simultaneously under the same manufacturing conditions. In an exemplary embodiment, the fan-out wiring 720a and the touch wiring 720 may comprise Al. In other exemplary embodiments, the fan-out wiring 720a and the touch wiring 720 may comprise Ti / Al / Ti.

[0097] In an exemplary embodiment, the fan-out wiring 720a may include a material that is the same as that of the touch wiring 720 but different from the material of the first signal wiring 213b, the second signal wiring 213c, the third signal wiring 215c, the source electrode 215a, or the drain electrode 215b.

[0098] In an exemplary embodiment, the fan-out wiring 720a may include the same material as the first signal wiring 213b, the second signal wiring 213c, the third signal wiring 215c, the source electrode 215a, or the drain electrode 215b.

[0099] Fan-out wiring 720a and touch wiring 720 can be formed using a low-temperature layer forming process at approximately 90°C or below. This is likely to protect the already formed display device 300 or other components. On the other hand, first signal wiring 213b, second signal wiring 213c, third signal wiring 215c, source electrode 215a, and drain electrode 215b can be formed using a high-temperature layer forming process at a temperature equal to or above 90°C (e.g., approximately 150°C), wherein the first signal wiring 213b, second signal wiring 213c, third signal wiring 215c, source electrode 215a, and drain electrode 215b are formed before the formation of the display device 300, encapsulation layer 400, or other components.

[0100] Therefore, even when the fan-out wiring 720a is formed using the same material as the first signal wiring 213b, the second signal wiring 213c, the third signal wiring 215c, the source electrode 215a, or the drain electrode 215b, the resistivity values ​​and the die sizes can be varied. For example, when using the same material, the resistivity value of the fan-out wiring 720a can be approximately 25% larger than the resistivity values ​​of the first signal wiring 213b, the second signal wiring 213c, and the third signal wiring 215c. Furthermore, the die size of the fan-out wiring 720a can be smaller than the die sizes of the first signal wiring 213b, the second signal wiring 213c, and the third signal wiring 215c.

[0101] In embodiments, the thicknesses of the fan-out wiring 720a, the first signal wiring 213b, the second signal wiring 213c, and the third signal wiring 215c can be different from each other. For example, the thickness of the fan-out wiring 720a can be less than the thickness of the third signal wiring 215c, which is formed using the same material as the source electrode 215a and the drain electrode 215b. In an exemplary embodiment, the thickness of the fan-out wiring 720a can be approximately 50% of the thickness of the third signal wiring 215c.

[0102] An organic material layer 160 may be disposed in at least a portion of the curved region BA located between the fan-out wiring 720a and the substrate 100. When the display device is bent, the organic material layer 160 can prevent cracks in the fan-out wiring 720a of the curved region BA. The organic material layer 160 can absorb the tensile stress on the substrate 100 and other components caused by bending, thus effectively reducing the tensile stress concentrated on the fan-out wiring 720a.

[0103] The organic material layer 160 can be formed using the same material as the planarization layer 140, pixel defining layer 150, organic encapsulation layer 420 of encapsulation layer 400, or touch buffer layer 610, and can be formed simultaneously with the planarization layer 140, pixel defining layer 150, organic encapsulation layer 420 of encapsulation layer 400, or touch buffer layer 610. That is, the organic material layer 160 can be formed during the masking process used to form the planarization layer 140, pixel defining layer 150, organic encapsulation layer 420 of encapsulation layer 400, or touch buffer layer 610. Therefore, the additional masking process for forming the organic material layer 160 can be omitted. The buffer layer 110, gate insulating layer 120, or interlayer insulating layer 130 may also include organic materials. In this case, the organic material layer 160 can be formed by using the same material as the buffer layer 110, the gate insulating layer 120, or the interlayer insulating layer 130, and can be formed simultaneously with the buffer layer 110, the gate insulating layer 120, or the interlayer insulating layer 130.

[0104] If the fan-out wiring 720a is formed simultaneously with the first signal wiring 213b, the second signal wiring 213c, the third signal wiring 215c, the source electrode 215a, or the drain electrode 215b, an additional mask must be used to form the organic material layer 160. According to an exemplary embodiment, since the fan-out wiring 720a and the touch wiring 720 are formed simultaneously, the organic material layer 160 can be formed together with the organic material-containing layer disposed in the display area DA, thus simplifying the masking process.

[0105] Each layer, including an inorganic buffer layer 110, a gate insulating layer 120, and an interlayer insulating layer 130, can be referred to as an inorganic insulating layer. The inorganic insulating layer can have properties similar to... Figure 2C The opening corresponding to the curved region BA is shown in the diagram. That is, the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130 can each have openings 110a, 120a, and 130a corresponding to the curved region BA, respectively. The opening corresponding to the curved region BA can refer to an opening superimposed on the curved region BA. The opening can be larger than the curved region BA. Therefore, Figure 2C The width OW of the opening is shown to be greater than the width of the curved region BA. The smallest of the corresponding openings 110a, 120a, and 130a in the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130 can be determined as the size of the opening. Figure 2C In this context, the size of the opening 110a in the buffer layer 110 is determined as the size of the opening.

[0106] The display device according to this exemplary embodiment includes an organic material layer 160 that fills at least a portion of an opening in an inorganic insulating layer. Figure 2CThe organic material layer 160 is shown to completely fill the opening. Fan-out wiring 720a can extend from the first region 1A through the curved region BA to the second region 2A and can be located on the organic material layer 160. In regions where the organic material layer 160 is not provided, fan-out wiring 720a can be located on an inorganic insulating layer such as interlayer insulating layer 130.

[0107] Because the inorganic insulating layer has a higher hardness than the organic material layer 160, the inorganic insulating layer in the bending region BA may have cracks. When the inorganic insulating layer breaks, the fan-out wiring 720a is highly likely to fracture. Although the organic material layer 160 can prevent crack propagation, openings formed in the inorganic insulating layer can further reduce the likelihood of cracks appearing in the inorganic insulating layer. Therefore, the horizontally reduced tensile stress can be concentrated on the fan-out wiring 720a.

[0108] like Figure 2C As shown, the organic material layer 160 may cover the inner surface of the opening of the inorganic insulating layer. Various wirings of the display device can be formed by forming a conductive material layer on the entire surface of the substrate 100 and patterning the conductive material layer. If, during the patterning of the conductive material layer, the organic material layer 160 does not cover the inner surface of the opening 110a of the buffer layer 110, the inner surface of the opening 120a of the gate insulating layer 120, or the inner surface of the opening 130a of the interlayer insulating layer 130, then the conductive material may not be removed from the inner surface of the opening 110a of the buffer layer 110, the inner surface of the opening 120a of the gate insulating layer 120, or the inner surface of the opening 130a of the interlayer insulating layer 130, but may instead remain in the inner surface of the opening 110a of the buffer layer 110, the inner surface of the opening 120a of the gate insulating layer 120, or the inner surface of the opening 130a of the interlayer insulating layer 130. In this case, the retained conductive material will cause a short circuit between the conductive layers. Therefore, the organic material layer 160 can be formed as the inner surface of the opening covering the inorganic insulating layer. Although Figure 2C The organic material layer 160 is shown to have a uniform thickness for reference; however, alternatively, the organic material layer 160 may have different thicknesses at various locations, such that the organic material layer 160 gradually rises and falls around the inner surface of the opening 110a of the buffer layer 110, the inner surface of the opening 120a of the gate insulating layer 120, or the inner surface of the opening 130a of the interlayer insulating layer 130.

[0109] The display device according to this exemplary embodiment may further include a protective film 170. The protective film 170 may be a lower protective film protecting the lower surface of the substrate 100, such as... Figure 2C As shown, it may have an opening 170OP. The opening 170OP may correspond to the curved region BA. The area of ​​the opening 170OP may be larger than the area of ​​the curved region BA. Figure 2CIn the middle, the width of the opening 170OP can be greater than the width of the curved area BA.

[0110] The protective film 170 protects the lower surface of the substrate 100 and is therefore rigid. Therefore, when the protective film 170 has low flexibility, it will separate from the substrate 100 due to bending. Thus, as... Figure 2C As shown, the protective film 170 may have an opening 170OP corresponding to the curved region BA, thereby effectively preventing the protective film 170 from separating from the substrate 100. Therefore, as described above, the area of ​​the opening 170OP of the protective film 170 may be larger than the area of ​​the curved region BA. Figure 2C In this process, the protective film 170 is removed from the curved region BA, but is not limited thereto. The protective film 170 can be modified in various ways; for example, the protective film 170 may not be completely removed from the curved region BA, and may have a smaller thickness in the curved region BA compared to the first region 1A or the second region 2A.

[0111] The bend protection layer (BPL) 600 can be located outside the display area DA. That is, the BPL 600 can at least correspond to the bend area BA and be located above the fan-out wiring 720a.

[0112] When the stacked structure is bent, a stress-neutral surface can exist within the stacked structure. Without BPL 600, excessive tensile stress would be applied to the fan-out wiring 720a in the bent region BA due to the bending of the substrate 100, because the position of the fan-out wiring 720a would not correspond to the stress-neutral surface. However, by allowing the presence of BPL 600 and adjusting its thickness and modulus, the position of the stress-neutral surface in the stacked structure, which includes all substrates 100, fan-out wiring 720a, and BPL 600, can be adjusted. Therefore, the stress-neutral surface can be located near the fan-out wiring 720a passing through BPL 600, thus less tensile stress would be applied to the fan-out wiring 720a.

[0113] exist Figure 2C In this embodiment, the top surface of BPL 600 in the direction toward the display area DA (-x direction) coincides with the top surface of the cover layer 730 in the direction (+z direction), but the invention is not limited thereto. For example, one end of BPL 600 in the direction toward the display area DA (-x direction) may partially cover the top surface located at the edge of the cover layer 730. Furthermore, various modifications are possible; for example, one end of BPL 600 in the direction toward the display area DA (-x direction) may not contact the cover layer 730. BPL 600 may extend to the upper part of the display area DA to cover the touch electrode 710.

[0114] BPL 600 can be formed by coating a liquid-phase material or a paste-type material and then curing it. In this case, the volume of BPL 600 is reduced during the curing process. In this respect, when a portion of BPL 600 in the direction towards the display area DA (-x direction) contacts the cover layer 730, the position of that portion of BPL 600 is fixed; therefore, volume reduction occurs in the remaining portion of BPL 600. Thus, the thickness of the portion of BPL 600 in the direction towards the display area DA (-x direction) can be greater than the thickness of the other portions of BPL 600.

[0115] BPL 600 can expose signal terminal 21 of the second area 2A (see...) Figure 2B In this respect, in the second area 2A, the signal terminal 21 can be used to connect control units such as various electronic components or PCBs.

[0116] Figure 3A This is a schematic cross-sectional view illustrating a portion of a display device according to another exemplary embodiment. (Refer to...) Figure 3A The cover layer 730 extends from the top of the touchscreen layer 700 to the non-display area to cover the fan-out wiring 720a. Therefore, the cover layer 730 can protect both the touchscreen layer 700 and the fan-out wiring 720a simultaneously. Figure 3A As shown, the overlay layer 730 can extend as a whole from the display area DA to at least the curved area BA. In this case, the overlay layer 730 can be used as BPL600 (see...). Figure 2C That is, the capping layer 730 can adjust the position of the stress neutral surface in the bending region BA. The stress neutral surface can be located near the fan-out wiring 720a passing through the capping layer 730, so that horizontally reduced tensile stress can be applied to the fan-out wiring 720a.

[0117] Figure 3B This is a schematic cross-sectional view illustrating a portion of a display device according to another exemplary embodiment. (Refer to...) Figure 3B The cover layer 730 can extend from the top of the touchscreen layer 700 to the non-display area to cover the fan-out wiring 720a. That is, the cover layer 730 can extend as a whole from the display area DA to at least the curved area BA. The BPL 600 can also be disposed above the cover layer 730 in the non-display area. As described above, the BPL 600 can be used to apply horizontally reduced tensile stress to the fan-out wiring 720a by positioning the stress neutral plane near the fan-out wiring 720a.

[0118] In the accompanying drawings of the exemplary embodiments described below, the cover layer 730 extends into the curved region BA, but the invention is not limited thereto. As described above, various modifications can be made; for example, BPL 600 may be arranged in place of the cover layer 730 in the curved region BA, and both the cover layer 730 and BPL 600 may be arranged simultaneously or neither may be arranged.

[0119] Figure 4A This is a schematic cross-sectional view illustrating a portion of a display device according to another exemplary embodiment. (Refer to...) Figure 4A A touch electrode 710 can be formed by sequentially stacking a first touch conductive layer 711, a first insulating layer 712, a second touch conductive layer 713, and a second insulating layer 714. The first touch conductive layer 711 can be electrically connected to the second touch conductive layer 713. In some embodiments, the first insulating layer 712 may include a through-hole exposing the upper surface of the first touch conductive layer 711, through which the first touch conductive layer 711 can be connected to the second touch conductive layer 713.

[0120] By using the first touch conductive layer 711 and the second touch conductive layer 713, the resistance of the touch electrode 710 can be reduced, thereby improving the response speed of the touch screen layer 700.

[0121] In an exemplary embodiment, the fan-out wiring 720a and the touch wiring 720 may comprise the same material as the first touch conductive layer 711 or the second touch conductive layer 713. In other exemplary embodiments, the fan-out wiring 720a and the touch wiring 720 may have a structure with a first layer and a second layer stacked thereon, the first layer comprising the same material as the first touch conductive layer 711 and the second layer comprising the same material as the second touch conductive layer 713.

[0122] In an exemplary embodiment, the touch wiring 720 may include the same material as the first touch conductive layer 711 or the second touch conductive layer 713. In other exemplary embodiments, the touch wiring 720 may be formed by stacking a first layer and a second layer, the first layer including the same material as the first touch conductive layer 711 and the second layer including the same material as the second touch conductive layer 713.

[0123] Each of the first touch conductive layer 711 and the second touch conductive layer 713 may be a single layer or multiple layers formed of a conductive material such as Al, Cu, and / or Ti. In an exemplary embodiment, each of the first touch conductive layer 711 and the second touch conductive layer 713 may have a stacked structure formed of Ti / Al / Ti.

[0124] The first insulating layer 712 may comprise an inorganic or organic material. The inorganic material may comprise at least one selected from silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The organic material may comprise at least one selected from acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins.

[0125] The second insulating layer 714 may include an organic material, for example, at least one selected from acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins.

[0126] In this case, the organic material layer 160 can be formed simultaneously with the first insulating layer 712 or the second insulating layer 714 by using the same material as the first insulating layer 712 or the second insulating layer 714.

[0127] The organic material layer 160 can be formed simultaneously with the planarization layer 140, pixel defining layer 150, encapsulation layer 420 of encapsulation layer 400, touch buffer layer 610, first insulating layer 712, or second insulating layer 714 using the same material as the planarization layer 140, pixel defining layer 150, encapsulation layer 400, organic encapsulation layer 420, touch buffer layer 610, first insulating layer 712, or second insulating layer 714. However, the invention is not limited thereto. For example, the organic material layer 160 can be formed using a different process than that used to form the planarization layer 140, pixel defining layer 150, encapsulation layer 400, organic encapsulation layer 420, touch buffer layer 610, first insulating layer 712, or second insulating layer 714.

[0128] The buffer layer 110, gate insulating layer 120, and / or interlayer insulating layer 130 may comprise organic materials. In this case, the organic material layer 160 may be formed by using the same material as the buffer layer 110, gate insulating layer 120, or interlayer insulating layer 130.

[0129] Figure 4B and Figure 4CThis is a schematic cross-sectional view illustrating a portion of a display device according to another exemplary embodiment. The display device according to this exemplary embodiment differs from the display device according to the exemplary embodiment described above in that an additional conductive layer 215d may be further disposed in the lower portion of the fan-out wiring 720a. As described above, if the fan-out wiring 720a is formed simultaneously with the additional conductive layer 215d using the same material as the additional conductive layer 215d, the additional conductive layer 215d may be formed simultaneously with the source electrode 215a or the drain electrode 215b using the same material as the source electrode 215a or the drain electrode 215b. The additional conductive layer 215d may be located at least in the lower portion of the fan-out wiring 720a in the bending region BA, such that the additional conductive layer 215d is electrically connected to the fan-out wiring 720a.

[0130] As described above, since the display device according to this exemplary embodiment includes a fan-out wiring 720a and an additional conductive layer 215d in the curved region BA, the conductive layer of the curved region BA can have a multilayer structure. Therefore, even if a defect occurs in the curved region BA due to a crack formed in the fan-out wiring 720a, the electrical signal can be transmitted to the display region DA without problems through the additional conductive layer 215d. Alternatively, even if a defect occurs due to a crack formed in the additional conductive layer 215d, the electrical signal can be transmitted to the display region DA without problems through the fan-out wiring 720a.

[0131] In this exemplary embodiment, the fan-out wiring 720a and the touch wiring 720 may include, as shown in the example Figure 4B The material of the first touch conductive layer 711 shown in the figure is the same as that of the material shown in the figure, or may include materials such as Figure 4C The material of the second touch conductive layer 713 shown is the same.

[0132] Figure 4D This is a schematic cross-sectional view of a display device according to another exemplary embodiment. The display device according to this exemplary embodiment and reference... Figure 4B The difference in the described display device is that the fan-out wiring 720a has a structure with a first layer 721a and a second layer 723a stacked together, the first layer 721a comprising the same material as the first touch conductive layer 711, and the second layer 723a comprising the same material as the second touch conductive layer 713.

[0133] In this exemplary embodiment, the touch wiring 720 may have a structure in which a first wiring layer 721 and a second wiring layer 723 are stacked. The first wiring layer 721 comprises the same material as the first touch conductive layer 711, and the second wiring layer 723 comprises the same material as the second touch conductive layer 713.

[0134] As described above, since the display device according to this exemplary embodiment includes a conductive layer with a multilayer structure in the curved region BA, even if a crack appears in the conductive layer with a single-layer structure, the electrical signal can be transmitted to the display region DA without any problems.

[0135] Figure 4E This is a schematic cross-sectional view illustrating a portion of a display device according to another exemplary embodiment. (Refer to...) Figure 4E An additional conductive layer 215d may be disposed in the lower portion of the fan-out wiring 720a. The additional conductive layer 215d can be formed by extending the first signal wiring 213b through the bend region BA. That is, the additional conductive layer 215d may comprise the same material as the gate electrode 213. In this exemplary embodiment, the additional conductive layer 215d may directly contact the fan-out wiring 720a in the bend region BA to form a multilayer structure.

[0136] As described above, since the display device according to this exemplary embodiment includes a fan-out wiring 720a and an additional conductive layer 215d in the curved region BA, the conductive layer of the curved region BA can have a multilayer structure. Therefore, even if a defect occurs in the curved region BA due to a crack formed in the fan-out wiring 720a, the electrical signal can be transmitted to the display region DA without problems through the additional conductive layer 215d. Alternatively, even if a defect occurs due to a crack formed in the additional conductive layer 215d, the electrical signal can be transmitted to the display region DA without problems through the fan-out wiring 720a.

[0137] As described above, the fan-out wiring 720a may include the same material as the first touch conductive layer 711 or the second touch conductive layer 713. The fan-out wiring 720a may have a structure with a first layer and a second layer stacked thereon, the first layer including the same material as the first touch conductive layer 711 and the second layer including the same material as the second touch conductive layer 713.

[0138] Figure 4F and Figure 4G This is a schematic cross-sectional view of a portion of a display device according to another exemplary embodiment.

[0139] Reference Figure 4F The display device according to this exemplary embodiment may include an additional conductive layer 215d located in the lower part of the fan-out wiring 720a in the curved region BA and an insulating layer 180 located between the fan-out wiring 720a and the additional conductive layer 215d.

[0140] As described above, the fan-out wiring 720a can be formed simultaneously with the touch wiring 720 using the same material as the touch wiring 720. The additional conductive layer 215d can be formed simultaneously with the source electrode 215a, drain electrode 215b, or gate electrode 213 using the same material as the source electrode 215a, drain electrode 215b, or gate electrode 213. The additional conductive layer 215d can be electrically connected to the fan-out wiring 720a through vias CNTs disposed in the insulating layer 180. These vias can be arranged in the first region 1A and / or the second region 2A.

[0141] The additional conductive layer 215d and fan-out wiring 720a can have various modifications. For example, the additional conductive layer 215d and fan-out wiring 720a can be arranged above the curved region BA, or can be stacked only in a portion of the curved region BA as described in the exemplary embodiments above.

[0142] The insulating layer 180 may include organic or inorganic materials. The insulating layer 180 may be formed simultaneously with the planarization layer 140, the pixel defining layer 150, the inorganic encapsulation layers 410 and 430 of the encapsulation layer 400, the organic encapsulation layer 420, the touch buffer layer 610, etc., using the same material as the planarization layer 140, the pixel defining layer 150, the encapsulation layer 400, the inorganic encapsulation layers 410 and 430, the organic encapsulation layer 420, the touch buffer layer 610, etc.

[0143] Reference Figure 4G The additional conductive layer 215d may exist only in a portion of the curved region BA. For example, the additional conductive layer 215d may exist in both edges of the curved region BA to contact the fan-out wiring 720a. The additional conductive layer 215d may have various modifications; for example, the additional conductive layer 215d may exist in only one edge of the curved region BA.

[0144] Figure 4H This is a schematic cross-sectional view illustrating a portion of a display device according to another exemplary embodiment. (Refer to...) Figure 4H The fan-out wiring 720a may exist only in a portion of the curved region BA. For example, the fan-out wiring 720a may exist in both edges of the curved region BA to contact the additional conductive layer 215d. The fan-out wiring 720a may have various modifications; for example, the fan-out wiring 720a may exist in only one edge of the curved region BA.

[0145] Figure 4I This is a schematic cross-sectional view of a portion of a display device according to another exemplary embodiment.

[0146] In addition to TFT 210, the display device according to this exemplary embodiment may include a second TFT 210' in the display area DA. TFT 210' may include a semiconductor layer 211', a source electrode 215a', a drain electrode 215b', and a gate electrode 213'. In this regard, the semiconductor layer 211' may include the same material as the semiconductor layer 211 and may be located on the same layer as the semiconductor layer 211. The source electrode 215a' and drain electrode 215b' may also include the same material as the source electrode 215a and drain electrode 215b and may be located in the same layer as the source electrode 215a and drain electrode 215b. However, the gate electrode 213' may be located in a different layer than the gate electrode 213, which indicates that the gate electrode 213' and the gate electrode 213 are not formed simultaneously and are formed in different operations.

[0147] More specifically, the gate insulating layer 120' may be located above the gate insulating layer 120, and the source electrode 215a, drain electrode 215b, source electrode 215a', and drain electrode 215b' may be located above the interlayer insulating layer 130 covering the gate insulating layer 120'. The gate electrode 213 may be located above the gate insulating layer 120. The gate insulating layer 120' may cover the gate electrode 213. The gate electrode 213' may be located above the gate insulating layer 120'.

[0148] In some exemplary embodiments, wiring and / or electrodes of a capacitor (not shown) disposed in the same layer as the gate electrode 213' may be added. In this case, various modifications can be made, for example, the TFT 210' may be omitted.

[0149] In this exemplary embodiment, the display device may further include a first additional conductive layer 215d' and / or a second additional conductive layer 215d'' in the curved region BA. The first additional conductive layer 215d' may include the same material as the gate electrode 213 and may be disposed in the same layer as the gate electrode 213. The second additional conductive layer 215d'' may include the same material as the gate electrode 213' and may be disposed in the same layer as the gate electrode 213'.

[0150] The first additional conductive layer 215d' and / or the second additional conductive layer 215d'' may extend above the bending region BA and may be arranged in the lower part of the fan-out wiring 720a within the bending region BA. Figure 4IIn this configuration, the first additional conductive layer 215d', the second additional conductive layer 215d'', and the fan-out wiring 720a can be sequentially stacked in the curved region BA to form a multilayer structure. Therefore, even if defects arise in the curved region BA due to cracks formed in the fan-out wiring 720a, electrical signals can still be transmitted to the display area DA without problems through the first additional conductive layer 215d' and / or the second additional conductive layer 215d''. Alternatively, even if defects arise due to cracks formed in the first additional conductive layer 215d' and / or the second additional conductive layer 215d'', electrical signals can still be transmitted to the display area DA without problems through the fan-out wiring 720a.

[0151] However, the invention is not limited thereto. For example, the first additional conductive layer 215d', the second additional conductive layer 215d'' and / or the fan-out wiring 720a may be arranged above the curved region BA, or may be stacked in only a portion of the curved region BA, as described in the embodiments above.

[0152] In an exemplary embodiment, the first additional conductive layer 215d' and the fan-out wiring 720a may be stacked in a portion of the curved region BA, and the second additional conductive layer 215d'' and the fan-out wiring 720a may be stacked in another portion of the curved region BA. Alternatively, various modifications may be possible; for example, the first additional conductive layer 215d' and / or the second additional conductive layer 215d'' may not be stacked with the fan-out wiring 720a, and only the first additional conductive layer 215d'' and / or the second additional conductive layer 215d'' may be arranged in a portion of the curved region BA.

[0153] Insulation layer 180 (see) Figure 4F It can be arranged between each of the first additional conductive layer 215d', the second additional conductive layer 215d'', and the fan-out wiring 720a.

[0154] Figures 5A to 5I This is a schematic cross-sectional view illustrating a portion of a display device according to an exemplary embodiment. Specifically, Figures 5A to 5I This is a cross-sectional view showing the area near the curved region BA.

[0155] Reference Figure 5A At least a portion of the height h1 of the organic material layer 160 within the opening of the inorganic insulating layer can be greater than the height h2 of the inorganic insulating layer. For example... Figure 5A As shown, the height of the central portion of the opening in the organic material layer 160 can be greater than the height at both ends of the opening. The organic material layer 160 can cover the inner surface of the opening, so that no short circuit occurs between the fan-out wiring 720a and the conductive material remaining on the inner surface of the opening.

[0156] Reference Figure 5B The height h1 of the organic material layer 160 in the opening of the inorganic insulating layer can be substantially the same as the height h2 of the inorganic insulating layer. In this case, the organic material layer 160 can cover the inner surface of the opening, preventing a short circuit between the fan-out wiring 720a and the conductive material remaining on the inner surface of the opening. The height h1 of the organic material layer 160 can be varied according to the tensile stress caused by bending.

[0157] Reference Figure 5C At least a portion of the upper surface (in the +z direction) of the organic material layer 160 within the opening of the inorganic insulating layer may have a certain degree of surface inhomogeneity. Therefore, the surface area of ​​the upper surface of the organic material layer 160 within the opening, as well as the surface areas of the upper and lower surfaces of the fan-out wiring 720a, can be increased. This increased surface area of ​​the upper surface of the organic material layer 160 and the upper and lower surfaces of the fan-out wiring 720a can mean an increased deformation margin, thereby reducing tensile stress due to the bending of the substrate 100.

[0158] Since the fan-out wiring 720a is located on the organic material layer 160, the lower surface of the fan-out wiring 720a can be shaped to correspond to the non-uniform surface 160a of the organic material layer 160.

[0159] The non-uniform surface 160a of the upper surface (in the +z direction) of the organic material layer 160 can be formed using various methods. For example, a photosensitive material can be used when forming the organic material layer 160, and during the manufacturing process, the exposure can be differentiated by using slit masks or halftone masks on various portions of the organic material layer 160, which still has a substantially flat upper surface. Therefore, some portions can be etched (removed) relatively more than others. The relatively more etched portions can be portions recessed relative to the upper surface of the organic material layer 160. The method of manufacturing the display device according to this exemplary embodiment is not limited to the foregoing method. For example, certain portions can be dry-etched after forming the organic material layer 160 with a substantially flat upper surface, or various other methods can be used.

[0160] Reference Figure 5D The organic material layer 160 may cover the inner surface of the opening and extend to a portion of the upper surface of the inorganic insulating layer. In an exemplary embodiment, the organic material layer 160 may not be disposed in at least a portion of the central portion of the opening. The organic material layer 160 may cover the inner surface of the opening to prevent short circuits between the fan-out wiring 720a and the conductive material held on the inner surface of the opening. According to this exemplary embodiment, since there is no inorganic insulating layer in the bending region BA, the likelihood of cracks forming in the fan-out wiring 720a is low.

[0161] Reference Figure 5E The inorganic insulating layer may have a groove in the curved region BA instead of an opening exposing the substrate 100. In other words, only a portion of the inorganic insulating layer (i.e., only a portion of the buffer layer 110, gate insulating layer 120, and interlayer insulating layer 130) may be removed in the curved region BA. For example, the buffer layer 110 may continue through the first region 1A, the curved region BA, and the second region 2A. Additionally, the gate insulating layer 120 may have an opening 120a corresponding to the curved region BA, and the interlayer insulating layer 130 may have an opening 130a corresponding to the curved region BA. Therefore, the inorganic insulating layer comprising the buffer layer 110, the gate insulating layer 120, and the interlayer insulating layer 130 may have a groove corresponding to the curved region BA. The inorganic insulating layer may have a groove with a shape different from the shape described above. For example, the upper surface of the buffer layer 110 (in the +z direction) may be partially removed, but the lower surface of the gate insulating layer 120 (in the -z direction) may not be removed and may be retained.

[0162] In the display device according to this exemplary embodiment, the organic material layer 160 may fill at least a portion of the groove. The formation of the groove in the inorganic insulating layer can reduce the likelihood of cracks in the inorganic insulating layer, and thus reduce the likelihood of cracks extending into the fan-out wiring 720a. Although the organic material layer 160 can block crack propagation, the formation of the groove in the inorganic insulating layer can further reduce the likelihood of cracks forming in the inorganic insulating layer. Therefore, a lower level of tensile stress can be concentrated on the fan-out wiring 720a.

[0163] Reference Figure 5F The inorganic insulating layer may not have openings or grooves in the bending region BA, and the organic material layer 160 may be located on top of the inorganic insulating layer. That is, the inorganic insulating layer may not have openings in the bending region BA. The organic material layer 160 can absorb the tensile stress of the inorganic insulating layer to reduce the amount of tensile stress transmitted to the fan-out wiring 720a. The height of the organic material layer 160 can be varied.

[0164] Reference Figure 5G The inorganic insulating layer may not have openings or grooves in the bending region BA, and the organic material layer 160 may be located on the inorganic insulating layer. Furthermore, at least a portion of the upper surface (in the +z direction) of the organic material layer 160 may have a non-uniform surface. Therefore, the surface area of ​​the upper surface of the organic material layer 160 in the opening, as well as the surface areas of the upper and lower surfaces of the fan-out wiring 720a, can be increased. This increased surface area of ​​the upper surface of the organic material layer 160 and the upper and lower surfaces of the fan-out wiring 720a can mean an increased deformation margin, thereby reducing the level of tensile stress due to the bending of the substrate 100.

[0165] Reference Figure 5HThe buffer layer 110, gate insulating layer 120, or interlayer insulating layer 130 may have surface inhomogeneities in the bent region BA. Figure 5H In this invention, the interlayer insulating layer 130 may have a non-uniform surface 130a, but the invention is not limited thereto. For example, at least one of the buffer layer 110, the gate insulating layer 120, the interlayer insulating layer 130, and another insulating layer present in the curved region BA may have surface non-uniformity.

[0166] like Figure 5H As shown, the interlayer insulating layer 130 may have a non-uniform surface 130a. Therefore, the shapes of the upper and / or lower surfaces of the organic material layer 160 and the fan-out wiring 720a located above the interlayer insulating layer 130 may correspond to the non-uniform surface 130a of the interlayer insulating layer 130. In an exemplary embodiment, the organic material layer 160 may be omitted. Although the organic material layer 160 may be omitted, the amount of tensile stress can be minimized due to the non-uniform nature of the fan-out wiring 720a. As described above, when the substrate 100 is bent in the bending region BA during the manufacturing process, since tensile stress is applied to the fan-out wiring 720a, the shapes of the upper and / or lower surfaces of the fan-out wiring 720a may correspond to the non-uniform surface 130a, thereby applying less tensile stress to the fan-out wiring 720a.

[0167] Reference Figure 5I The display device according to an exemplary embodiment may include an inorganic material layer 160' disposed in the curved region BA between the fan-out wiring 720a and the substrate 100, instead of an organic material layer 160. When the inorganic material layer 160' is applied, the inorganic material layer 160' may include the same material as the first inorganic encapsulation layer 410, the second inorganic encapsulation layer 430, the touch buffer layer 610, the first insulating layer 712, or the second insulating layer 714. If the planarization layer 140 or the pixel defining layer 150 may include an inorganic material, then the inorganic material layer 160' may include the same material as the planarization layer 140 or the pixel defining layer 150.

[0168] At least a portion of the upper surface (in the +z direction) of the inorganic material layer 160' may have a non-uniform surface 160'a. Therefore, the surface area of ​​the upper surface of the inorganic material layer 160' in the opening and the surface areas of the upper and lower surfaces of the fan-out wiring 720a can be increased. This can mean an increased deformation margin to reduce tensile stress due to bending of the substrate 100.

[0169] In the exemplary embodiments described above, the non-uniform surface 160a can be formed by extending the protruding surface in a certain direction. In some exemplary embodiments, the fan-out wiring 720a can extend in a second direction (+x direction), and the protruding surface of the non-uniform surface 160a can extend in a first direction (+y direction), such that the fan-out wiring 720a and the protruding surface of the non-uniform surface 160a can intersect each other. The intersection angle can be 90 degrees, such as... Figure 5J As shown, Figure 5J This is a schematic plan view illustrating a portion of a display device according to another exemplary embodiment, where the intersecting angle can be any angle other than 90 degrees, such as... Figure 5K As shown. For reference, Figure 5J and Figure 5K The reference numeral GD in the accompanying drawings can indicate the direction of extension of the protruding surface of the non-uniform surface 160a formed in the upper surface of the organic material layer 160. Figure 5K In, with Figure 5J In contrast, the protruding surface of the non-uniform surface 160a formed in the upper surface of the organic material layer 160 extends in a direction inclined relative to the second direction (+x direction), but the exemplary embodiment is not limited thereto. For example, as Figure 5J As shown, the direction in which the protruding surface of the non-uniform surface 160a formed in the upper surface of the organic material layer 160 extends can be a first direction (+y direction). According to an exemplary embodiment, the direction in which the fan-out wiring 720a extends may not be the second direction (+x direction), but may be a direction inclined relative to the second direction (+x direction) (e.g., a direction forming a 45-degree angle relative to the second direction (+x direction). When there are multiple fan-out wirings 720a, the angle formed by some of the multiple fan-out wirings 720a relative to the second direction (+x direction) may be different from the angle formed by other fan-out wirings 720a relative to the second direction (+x direction).

[0170] Figure 6A and Figure 6B This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment. Specifically, the drawing schematically shows the area near one end of the fan-out wiring 720a.

[0171] Reference Figure 6A The driving circuit 800 can be located at one end of the fan-out wiring 720a. The driving circuit 800 can be electrically connected to the first signal wiring 213b, the second signal wiring 213c, and the third signal wiring 215c via the fan-out wiring 720a to provide driving signals to the display area DA. Driving signals refer to various signals used to drive the display device, such as driving voltage, gate signals, or data signals.

[0172] Reference Figure 6B Fan-out wiring 720a can be connected to lower fan-out wiring 213d in the second region 2A. Lower fan-out wiring 213d can be disposed on the gate insulating layer 120 and formed simultaneously with the gate electrode 213 using the same material as the gate electrode 213. Fan-out wiring 720a can be connected to lower fan-out wiring 213d via a contact hole. Upper fan-out wiring 215e can be additionally located at one end of lower fan-out wiring 213d. Upper fan-out wiring 215e can be formed simultaneously with the source electrode 215a or drain electrode 215b using the same material as the source electrode 215a or drain electrode 215b. Alternatively, upper fan-out wiring 215e can be formed simultaneously with fan-out wiring 720a using the same material as fan-out wiring 720a.

[0173] Various modifications can be implemented. For example, the lower fan-out routing 213d or the upper fan-out routing 215e can be omitted.

[0174] The driving circuit 800 can be located at one end of the upper fan-out wiring 215e or one end of the lower fan-out wiring 213d. The driving circuit 800 can be electrically connected to the first signal wiring 213b, the second signal wiring 213c, and the third signal wiring 215c via the upper fan-out wiring 215e or the lower fan-out wiring 213d and fan-out wiring 720a to provide driving signals to the display area DA. Driving signals refer to various signals used to drive the display device, such as driving voltages, gate signals, or data signals.

[0175] Figures 7A to 7I This is a cross-sectional view sequentially illustrating a method for manufacturing a display device according to an exemplary embodiment. Here, the manufacturing process will be described as an example. Figure 2C Methods for displaying devices.

[0176] Reference Figure 7A A buffer layer 110 and a semiconductor material layer are sequentially stacked on a substrate 100. Then, a semiconductor layer 211 is formed by patterning the semiconductor material layer.

[0177] The substrate 100 may include a variety of flexible or bendable materials, such as polymeric resins such as PES, PAR, PEI, PEN, PET, PPS, polyarylate, PI, PC, or CAP.

[0178] First, a buffer layer 110 and a semiconductor material can be deposited over the entire area of ​​the substrate 100. The buffer layer 110 may include inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride. The semiconductor material layer may be formed as a semiconductor, including amorphous silicon, polycrystalline silicon, or organic semiconductor materials. The buffer layer 110 and the semiconductor material layer can be deposited using various deposition methods.

[0179] Next, a photoresist pattern can be formed on the semiconductor material layer using a mask, and then the semiconductor material layer can be patterned to form the semiconductor layer 211.

[0180] Reference Figure 7B A gate insulating layer 120 covering the semiconductor layer 211 is formed over the entire area of ​​the substrate 100, and a first conductive material layer is deposited on the gate insulating layer 120. A photoresist pattern is formed on the first conductive material layer using a mask, and then the first conductive material layer is patterned to form the gate electrode 213, the first signal wiring 213b, and the second signal wiring 213c. The gate electrode 213 may be stacked with the semiconductor layer 211.

[0181] The gate insulating layer 120 may include inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride, and the gate insulating layer 120 may be deposited using various deposition methods.

[0182] The first conductive material layer can be formed using a low-resistance metallic material. For example, the first conductive material layer may include Mo, Al, Cu, and / or Ti. The first conductive material layer may be a single layer or multiple layers.

[0183] The first conductive material layer can be deposited using various deposition methods. The first conductive material layer can be deposited at temperatures of 90°C or higher (e.g., at 150°C or higher) to improve conductivity and reduce resistivity.

[0184] After the gate electrode 213, the first signal wiring 213b, and the second signal wiring 213c are formed, an interlayer insulating layer 130 is formed to cover the gate electrode 213, the first signal wiring 213b, and the second signal wiring 213c. The interlayer insulating layer 130 may comprise inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the interlayer insulating layer 130 may be deposited using various deposition methods.

[0185] Next, a photoresist pattern can be formed on the interlayer insulating layer 130 using a mask. Then, the interlayer insulating layer 130 and the gate insulating layer 120 can be etched simultaneously to form contact holes C1 and C2 exposing the semiconductor layer 211, contact hole C3 exposing the first signal wiring 213b, an opening 130a in the interlayer insulating layer 130 in the non-display area, and an opening 120a in the gate insulating layer 120. The openings 130a in the interlayer insulating layer 130 and 120a in the gate insulating layer 120 can be omitted according to the exemplary embodiment.

[0186] Next, as Figure 7CAs shown, an opening 110a of a buffer layer 110 is formed in an opening 130a of the interlayer insulating layer 130 and an opening 120a of the gate insulating layer 120. The opening 110a of the buffer layer 110 can be formed using a mask (not the mask used to form the opening 130a of the interlayer insulating layer 130 and the opening 120a of the gate insulating layer 120). When the opening 110a of the buffer layer 110 is formed simultaneously with the opening 130a of the interlayer insulating layer 130 and the opening 120a of the gate insulating layer 120, the semiconductor layer 211 will be damaged.

[0187] Reference Figure 7D A source electrode 215a, a drain electrode 215b, and a third signal wiring 215c are formed by depositing a second conductive material layer on the interlayer insulating layer 130, forming a photoresist pattern on the second conductive material layer using a mask, and patterning the second conductive material layer. The source electrode 215a and the drain electrode 215b can be connected to the source and drain regions of the semiconductor layer 211, respectively, via contact holes C1 and C2 exposing the semiconductor layer 211. According to an exemplary embodiment, the source and drain regions can be formed by doping.

[0188] The second conductive material layer can be formed using a low-resistance metallic material. For example, the second conductive material layer may include Al, Cu, and / or Ti. The second conductive material layer may be a single layer or multiple layers.

[0189] A second conductive material layer can be deposited using various deposition methods. The second conductive material layer can be deposited at temperatures of 90°C or higher (e.g., at 150°C or higher) to improve conductivity and reduce resistivity.

[0190] Next, the substrate 100 can be coated or deposited with a first organic material, and a planarization layer 140 and an organic material layer 160 can be formed simultaneously using a masking process. By forming the planarization layer 140 and the organic material layer 160 simultaneously, a separate masking process for forming the organic material layer 160 is not required.

[0191] The first organic material can be an organic material such as PI, acrylic, BCB, or HMDSO. The first organic material can be a photosensitive organic material. Therefore, the planarization layer 140 and the organic material layer 160 can be formed by partially exposing, developing, and curing using a mask. The heights of the planarization layer 140 and the organic material layer 160 can be different from each other. This is because the exposure can be differentiated using a slit mask or a halftone mask, allowing specific areas to be removed relatively more than others. The planarization layer 140 may include an opening OP1 exposing the source electrode 215a or the drain electrode 215b.

[0192] The organic material layer 160 may not be formed simultaneously with the planarization layer 140, but rather simultaneously with the organic encapsulation layer 420 of the pixel defining layer 150 or the encapsulation layer 400. Various other methods may also be used to form the organic material layer 160.

[0193] Reference Figure 7E The pixel electrode 310 is formed by depositing a third conductive material on the planarization layer 140, forming a photoresist pattern on the third conductive material using a mask, and etching the third conductive material. The pixel electrode 310 can fill the opening OP1 of the planarization layer 140 and can be connected to the source electrode 215a or the drain electrode 215b.

[0194] The third conductive material may include at least one transparent conductive oxide selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). In addition to transparent conductive oxides, the third conductive material may also include a metal reflective film, which includes one or more selected from silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), and chromium (Cr).

[0195] Next, a second organic material is formed on the entire surface of the substrate 100 to cover the pixel electrode 310. The second organic material can be an organic material such as PI, acrylic, BCB, or HMDSO. The second organic material can be a photosensitive organic material. Therefore, the pixel defining layer 150 exposing the central portion of the pixel electrode 310 can be formed by partially exposing, developing, and curing using a mask.

[0196] The pixel defining layer 150 and the planarization layer 140 may have a stepped structure in the peripheral region outside the display area DA. Therefore, the peripheral region outside the display area DA may be formed into a gradually curved step by an organic material.

[0197] As described above, the organic material layer 160 can be formed simultaneously with the pixel defining layer 150.

[0198] Reference Figure 7F The display device 300 is formed by forming an intermediate layer 320 of the organic light-emitting device in a region of the pixel electrode 310 that is not covered by the pixel limiting layer 150, and then forming a counter electrode 330 on the intermediate layer 320. The counter electrode 330 may extend to the upper part of the pixel limiting layer 150.

[0199] The intermediate layer 320 may comprise a low-molecular-weight material or a high-molecular-weight material. When the intermediate layer 320 comprises a low-molecular-weight material, it may comprise an EML, and may also comprise at least one of HIL, HTL, ETL, and EIL. The intermediate layer 320 may comprise various organic materials, such as CuPc, NPB, or Alq3. The layer may be formed by vapor deposition.

[0200] When the intermediate layer 320 comprises a polymer material, it may include an HTL and an EML. The HTL may include PEDOT, and the EML may include PPV-based and polyfluorene-based polymer materials. The intermediate layer 320 may be formed by screen printing, inkjet printing, or LITI, etc.

[0201] The counter electrode 330 may comprise various conductive materials. For example, the counter electrode 330 may comprise a transparent conductive metal oxide selected from the group consisting of ITO, IZO, ZnO, In2O3, IGO, and AZO. According to another exemplary embodiment, the counter electrode 330 may be formed as a thin film comprising at least one material selected from lithium (Li), calcium (Ca), LiF / Ca, LiF / Al, aluminum (Al), silver (Ag), magnesium (Mg), and ytterbium (Yb). The counter electrode 330 may be formed as a single layer or multiple layers. The counter electrode 330 may be a reflective electrode in a bottom-emitting display device. The counter electrode 330 may be a transparent electrode or a translucent electrode in a top-emitting display device.

[0202] The counter electrode 330 can be formed using various deposition methods (e.g., sputtering, vacuum deposition, CVD, pulsed laser deposition, printing, and atomic layer deposition).

[0203] Next, an encapsulation layer 400 is formed to encapsulate the display area. The encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. The encapsulation layer 400 is formed in the order of a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430 to cover the display area. The periphery of the second inorganic encapsulation layer 430, located outside the display area DA, may contact the first inorganic encapsulation layer 410, so that the organic encapsulation layer 420 is not exposed to the outside.

[0204] Each of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may comprise silicon oxide, silicon nitride, and / or silicon oxynitride. The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may be deposited using various deposition methods, such as CVD, ALD, and sputtering.

[0205] The organic encapsulation layer 420 may include at least one selected from the group consisting of PET, PEN, PC, PI, PES, POM, polyarylates, and HMDSO. A second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420 and may include silicon oxide, silicon nitride, and / or silicon oxynitride. The organic encapsulation layer 420 may be coated or deposited by flash evaporation, inkjet printing, or slot die coating, etc.

[0206] Reference Figure 7G A touch buffer layer 610 is formed on the encapsulation layer 400, and then touch electrodes 710, touch wiring 720 and fan-out wiring 720a are formed simultaneously.

[0207] A touch buffer layer 610 may be formed on the encapsulation layer 400. The touch buffer layer 610 may include silicon oxide, silicon nitride, and / or silicon oxynitride. The touch buffer layer 610 may be deposited using various deposition methods such as CVD, ALD, or sputtering.

[0208] Next, a fourth conductive material layer is formed on the entire surface of the substrate 100. The fourth conductive material layer may include a low-resistance metallic material, such as Al, Cu, and / or Ti. The fourth conductive material layer may be a single layer or multiple layers.

[0209] The fourth conductive material layer can be deposited using various deposition methods. The fourth conductive material layer can be deposited at low temperatures without damaging the display device 300, thus preventing damage to the display device 300 and other already formed components. For example, the fourth conductive material layer can be deposited at temperatures of approximately 90°C or below using a thermal evaporation deposition method.

[0210] The fourth conductive material layer can be formed using a material different from the material of the first or second conductive material layer, or a thickness different from the thickness of the first or second conductive material layer. For example, the thickness of the fourth conductive material layer can be less than the thickness of the second conductive material layer, such as approximately 50% of the thickness of the second conductive material layer.

[0211] Alternatively, a fourth conductive material layer can be deposited using the same material and structure as the second conductive material layer. However, due to differences in deposition conditions, the final deposited material can have different properties.

[0212] When deposited at temperatures of 90°C or higher (e.g., approximately 150°C), the second conductive material layer can have a large grain size and a low resistivity value.

[0213] However, the fourth conductive material layer can be deposited at low temperatures below 90°C, thus the fourth conductive material layer has a smaller grain size than the second conductive material layer and a higher resistivity. For example, the resistivity of the fourth conductive material layer can be approximately 25% higher than that of the second conductive material layer.

[0214] Fan-out wiring 720a, touch wiring 720, and touch electrode 710 can be formed simultaneously by using a mask to form a photoresist pattern on the fourth conductive material layer and patterning the fourth conductive material layer.

[0215] As described above, the touch electrode 710 may include a first touch conductive layer 711, a first insulating layer 712, a second touch conductive layer 713, and a second insulating layer 714. In this case, the fan-out wiring 720a and the touch wiring 720 may be formed simultaneously with the first touch conductive layer 711 or the second touch conductive layer 713. In an exemplary embodiment, the fan-out wiring 720a and the touch wiring 720 may be formed in the same manner as the stacking of the first touch conductive layer 711 and the second touch conductive layer 713. Therefore, the first layer may be formed simultaneously with the first touch conductive layer 711, and the second layer may be formed simultaneously with the second touch conductive layer 713.

[0216] Since the fan-out wiring 720a and the touch wiring 720 are formed simultaneously, the organic material layer 160 can be formed simultaneously with the organic material layer disposed in the display area DA, thus simplifying the mask process.

[0217] Reference Figure 7H A cover layer 730 is formed on the entire surface of the substrate 100. The cover layer 730 may be flexible and may include polymethyl methacrylate, polydimethylsiloxane, PI, acrylate, PET, or PEN, etc. The cover layer 730 may extend as a monomer to at least the curved region BA of the non-display area.

[0218] Reference Figure 7I BPL 600 can be formed in the curved region BA. BPL 600 can be formed by coating a liquid-phase material or a slurry-type material and then curing it.

[0219] Next, the display device can be bent about the bending axis BAX of the bending region BA, so that the display device is roughly shaped as follows. Figure 2C The display device shown is shown.

[0220] As described above, according to the exemplary embodiment, when the display device is bent by using an organic material layer 160 between the fan-out wiring 720a and the substrate 100, the possibility of a short circuit occurring at the fan-out wiring 720a can be reduced. Furthermore, according to the exemplary embodiment, the masking process can be simplified by simultaneously forming the organic material layer 160 and the organic material-containing layer disposed in the display area DA.

[0221] According to the aforementioned exemplary embodiments, a durable display device can be manufactured at a low manufacturing cost by reducing defects such as short circuits during the manufacturing process and reducing the number of operations.

[0222] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather encompasses a wider range of the given claims, various apparent modifications, and equivalent arrangements.

Claims

1. A display device, the display device comprising: The substrate includes a display area on which a display device is disposed and a non-display area arranged around the display area; An encapsulation layer is disposed above the display area; A touch screen layer is disposed on the encapsulation layer corresponding to the display area, and the touch screen layer includes touch electrodes; A touch wiring is disposed in the non-display area, and the touch wiring is connected to the touch electrode; Fan-out wiring connects to signal wiring extending from the display area; Terminals are arranged on one side of the non-display area; as well as An organic material layer is disposed between the terminal and the display area. in: At least a portion of the fan-out wiring is disposed on the organic material layer; At least a portion of the touch wiring is disposed on the organic material layer; The fan-out wiring comprises the same material as the touch wiring; and In the plan view, the fan-out wiring is configured to be spaced apart from the encapsulation layer.

2. The display device according to claim 1, wherein, The touchscreen layer also includes a touch buffer layer disposed between the encapsulation layer and the touch electrodes. The touch buffer layer is in direct contact with the encapsulation layer on the encapsulation layer.

3. The display device according to claim 2, wherein, The organic material layer comprises the same material as the touch buffer layer.

4. The display device according to claim 1, wherein: The touch electrode comprises a first touch conductive layer, a first insulating layer, a second touch conductive layer, and a second insulating layer stacked sequentially. The first touch conductive layer is electrically connected to the second touch conductive layer; The touch wiring comprises the same material as the second touch conductive layer.

5. The display device according to claim 4, wherein, The organic material layer comprises the same material as the first insulating layer.

6. The display device according to claim 1, wherein: The display device includes a pixel electrode, a counter electrode facing the pixel electrode, and an intermediate layer disposed between the pixel electrode and the counter electrode; The display device further includes a pixel defining layer, the pixel defining layer including an opening exposing a central portion of the pixel electrode and defining a pixel region in the display region; The organic material layer comprises the same material as the pixel defining layer.

7. The display device according to claim 1, wherein: The encapsulation layer includes an inorganic encapsulation layer and an organic encapsulation layer; The organic material layer comprises the same material as the organic encapsulation layer.

8. The display device according to claim 1, further comprising: A cover layer that covers the touchscreen layer and protects the touch electrodes.

9. The display device according to claim 8, wherein, The overlay extends from the top of the touch electrode to the non-display area and covers at least a portion of the fan-out wiring.

10. The display device according to claim 1, further comprising an inorganic insulating layer disposed between the substrate and the fan-out wiring. in, The inorganic insulating layer includes openings or grooves that are stacked with the organic material layer.

11. The display device according to claim 1, wherein, At least a portion of the upper surface of the organic material layer has surface unevenness.

12. The display device according to claim 1, further comprising: A thin-film transistor is disposed in the display area or the non-display area and includes a source electrode, a drain electrode, and a gate electrode; as well as An additional conductive layer is disposed, at least partially, in the non-display area. The additional conductive layer is disposed in the same layer as the source electrode, drain electrode, or gate electrode by using the same material as the source electrode, drain electrode, or gate electrode.

13. The display device according to claim 1, further comprising: A first thin-film transistor is disposed in the display area or the non-display area and includes a first semiconductor layer, a first source electrode, a first drain electrode, and a first gate electrode. A second thin-film transistor is disposed in the display area or the non-display area, and includes a second semiconductor layer, a second source electrode, a second drain electrode, and a second gate electrode. The first additional conductive layer comprises the same material as the first gate electrode; as well as The second additional conductive layer comprises the same material as the second gate electrode. in: The first gate electrode and the second gate electrode are arranged in different layers; and At least one of the first additional conductive layer and the second additional conductive layer is stacked with the organic material layer.

14. The display device according to claim 1, wherein, In the plan view, the organic material layer is arranged to be spaced apart from the organic material layer in the display area.

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