Phase change memory, fabrication method and memory system

Abstract

The embodiment of the present application discloses a phase change memory, a manufacturing method and a memory system. The phase change memory comprises a first conductive line, a second conductive line and a first phase change memory unit between the first conductive line and the second conductive line; the first conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the first phase change memory unit is perpendicular to the first conductive line and the second conductive line, and the first phase change memory unit comprises a first electrode layer, a first gating layer, a second electrode layer, a first phase change storage layer, a third electrode layer which are sequentially stacked; the first phase change memory unit further comprises at least one of the following: a first leakage potential barrier layer stacked in front of the first electrode layer, a second leakage potential barrier layer stacked between the second electrode layer and the first phase change storage layer and a third leakage potential barrier layer stacked behind the third electrode layer; the first leakage potential barrier layer, the second leakage potential barrier layer and the third leakage potential barrier layer are used for reducing a transient inrush current formed when the first gating layer is turned on.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a phase-change memory, a manufacturing method, and a memory system. Background Technology

[0002] Phase-change memory (PCM) is a memory element that uses the difference in conductivity or impedance between the crystalline and amorphous states of a specific phase-change material to store information. During the operation of switching the phase-change material between the crystalline and amorphous states in the PCM, different pulses can be used to control the heating of the phase-change material. Currently, during programming or reading operations of PCM, the large switching ratio of the gating device generates a relatively large inrush current, which seriously affects the lifespan of the PCM and causes read and write disturbances, significantly reducing device reliability. Summary of the Invention

[0003] This application provides a phase-change memory, a manufacturing method, and a memory system.

[0004] In a first aspect, embodiments of this application provide a phase-change memory (PCM), comprising: a first conductive line, a second conductive line, and a first PCM storage unit between the first conductive line and the second conductive line; wherein the first conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the first PCM storage unit is perpendicular to both the first conductive line and the second conductive line; and the first PCM storage unit comprises: a first electrode layer, a first gate layer, a second electrode layer, a first PCM storage layer, and a third electrode layer stacked sequentially; wherein...

[0005] The first phase change memory cell further includes at least one of the following: a first leakage barrier layer stacked in front of the first electrode layer, a second leakage barrier layer stacked between the second electrode layer and the first phase change memory layer, and a third leakage barrier layer stacked after the third electrode layer; the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are used to reduce the transient inrush current formed when the first gate layer is turned on.

[0006] In the above scheme, the bandgap width of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer is greater than the bandgap width of the first gate layer, and the thickness of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer is less than the thickness of the first gate layer.

[0007] In the above scheme, the materials constituting the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer include wide bandgap semiconductor materials.

[0008] In the above scheme, the wide bandgap semiconductor material includes at least one of the following:

[0009] silicon oxide;

[0010] silicon nitrides;

[0011] Silicon carbide;

[0012] Carbon and nitride compounds.

[0013] In the above scheme, the thickness and defects contained in the wide bandgap semiconductor material should be such that the bandgap width of the wide bandgap semiconductor material can reduce the transient inrush current formed when the gate layer is turned on, and the leakage current of the wide bandgap semiconductor material can meet the driving requirements of the first phase change memory layer.

[0014] In the above scheme, the wide bandgap semiconductor material is formed by controlling the timing and / or reactants of the process.

[0015] In the above scheme, the phase-change memory further includes: a third conductive line and a second phase-change memory unit between the second conductive line and the third conductive line; wherein, the third conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the second phase-change memory unit is perpendicular to both the second conductive line and the third conductive line; and the second phase-change memory unit includes: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer stacked sequentially; wherein...

[0016] The second phase change memory cell further includes at least one of the following: a fourth leakage barrier layer stacked before the fourth electrode layer, a fifth leakage barrier layer stacked between the fifth electrode layer and the second phase change memory layer, and a sixth leakage barrier layer stacked after the sixth electrode layer; the fourth leakage barrier layer, the fifth leakage barrier layer, and the sixth leakage barrier layer are used to reduce the transient inrush current formed when the second gate layer is turned on.

[0017] In the above scheme, the phase-change memory further includes:

[0018] Substrate;

[0019] A first isolation structure is alternately disposed on the substrate surface along a first direction, alongside the first conductive line and the first phase change memory cell stacked thereon; wherein, the first direction is parallel to the substrate surface;

[0020] The second isolation structure is alternately disposed on the substrate surface alongside the first phase change memory cell and the second conductive line stacked together along the second direction; wherein the second direction is parallel to the substrate and perpendicular to the first direction.

[0021] In the above scheme, the first isolation structure includes: a first isolation layer, which is disposed perpendicular to the first direction and covers the sidewall of the third electrode layer and the sidewall of the first phase change storage layer;

[0022] The second isolation layer is disposed perpendicular to the first direction and covers the sidewall of the second electrode layer, the sidewall of the first gate layer, the sidewall of the first electrode layer, and the sidewall of the first conductive line.

[0023] In the above scheme, the second isolation structure includes:

[0024] A third isolation layer is disposed perpendicular to the second direction and covers the sidewall of the third electrode layer and the sidewall of the first phase change storage layer;

[0025] A fourth isolation layer is disposed perpendicular to the second direction and covers the sidewall of the second electrode layer, the sidewall of the first gate layer, the sidewall of the first electrode layer, and the sidewall of the second conductive line.

[0026] In the above scheme, the phase-change memory further includes:

[0027] Along the extension direction parallel to the first conductive line, the first phase change storage layer has a first width, and the second electrode layer has a second width; wherein the second width is greater than the first width;

[0028] And / or,

[0029] Along the extension direction parallel to the second conductive line, the first phase change storage layer has a third width, and the second electrode layer has a fourth width; wherein the fourth width is greater than the third width.

[0030] Secondly, embodiments of this application also provide a method for manufacturing a phase-change memory, including: forming a first conductive line;

[0031] The first phase-change memory cell is formed;

[0032] Form a second conductive line;

[0033] The first phase change memory cell includes: a first electrode layer, a first gate layer, a second electrode layer, a first phase change memory layer, and a third electrode layer stacked sequentially; and the first phase change memory cell further includes at least one of the following: a first leakage barrier layer stacked before the first electrode layer, a second leakage barrier layer stacked between the second electrode layer and the first phase change memory layer, and a third leakage barrier layer stacked after the third electrode layer; the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are used to reduce the transient inrush current formed when the first gate layer is turned on.

[0034] The above scheme also includes:

[0035] Forming a second phase-change memory cell;

[0036] Forming a third conductive line;

[0037] The second phase-change memory cell includes: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer stacked sequentially; and the second phase-change memory cell further includes at least one of the following: a fourth leakage barrier layer stacked before the fourth electrode layer, a fifth leakage barrier layer stacked between the fifth electrode layer and the second phase-change memory layer, and a sixth leakage barrier layer stacked after the sixth electrode layer; the fourth leakage barrier layer, the fifth leakage barrier layer, and the sixth leakage barrier layer are used to reduce the transient inrush current formed when the second gate layer is turned on. Thirdly, embodiments of this application also provide a memory system including: a memory associated with any of the above-mentioned items and a memory controller coupled to the phase-change memory.

[0038] This application provides a phase-change memory, a manufacturing method, and a memory system. The phase-change memory includes...

[0039] A first conductive line, a second conductive line, and a first phase-change memory unit between the first conductive line and the second conductive line; wherein the first conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the first phase-change memory unit is perpendicular to both the first conductive line and the second conductive line; and the first phase-change memory unit includes: a first electrode layer, a first gate layer, a second electrode layer, a first phase-change memory layer, and a third electrode layer stacked sequentially; wherein...

[0040] The first phase-change memory cell further includes at least one of the following: a first leakage barrier layer stacked before the first electrode layer, a second leakage barrier layer stacked between the second electrode layer and the first phase-change memory layer, and a third leakage barrier layer stacked after the third electrode layer; the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are used to reduce the transient inrush current formed when the first gate layer is turned on. The phase-change memory provided in this application reduces the transient inrush current formed when the first gate layer is turned on by providing at least one of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer in the first phase-change memory layer, thereby reducing the transient inrush current formed when the first gate layer is turned on due to its limited leakage current. Attached Figure Description

[0041] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0042] Figure 1 This is a schematic diagram of the structure of a phase-change memory provided according to some aspects of this application;

[0043] Figure 2 A partial equivalent circuit diagram of a phase-change memory provided according to some aspects of this application;

[0044] Figure 3 A voltage-current characteristic curve of a phase-change memory provided according to some aspects of this application;

[0045] Figure 4 A voltage-current characteristic curve of a gating layer of a phase-change memory provided according to some aspects of this application;

[0046] Figure 5 For some aspects provided under this application Figure 1 The diagram shows the energy band structure of the phase-change memory.

[0047] Figure 6 This is a schematic diagram of another phase-change memory structure provided according to some aspects of this application;

[0048] Figure 7 For some aspects provided under this application Figure 4 The diagram shows the energy band structure of the phase-change memory.

[0049] Figure 8 This is a schematic diagram of another phase-change memory structure provided according to some aspects of this application;

[0050] Figure 9 This is a flowchart illustrating a method for manufacturing a phase-change memory according to some aspects of this application;

[0051] Figure 10 This is a flowchart illustrating another method for fabricating a phase-change memory according to some aspects of this application. Detailed Implementation

[0052] The various embodiments of this application are described in more detail below with reference to the accompanying drawings. Other embodiments, which can be variations of any disclosed embodiment, can be formed by different configurations or arrangements of the elements and features in the embodiments of this application. Therefore, the embodiments of this application are not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that the embodiments of this application are thorough and complete, and fully convey the scope of the embodiments of this application to those skilled in the art to which the embodiments of this application pertain. It should be noted that references to "embodiment," "another embodiment," etc., do not necessarily indicate only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. It should be understood that although the terms "first," "second," "third," etc., may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Therefore, without departing from the spirit and scope of the embodiments of this application, a first element in one embodiment may also be referred to as a second or third element in another embodiment.

[0053] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When an element is referred to as a connection or coupling to another element, it should be understood that the former may be directly connected to or coupled to the latter, or may be electrically connected to or coupled to the latter via one or more intermediate elements between the two. Furthermore, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Singular forms as used herein are intended to include plural forms unless the context clearly indicates otherwise. Unless otherwise stated or clearly understood from the context, the articles “a” and / or “an” used in the embodiments of this application and the appended claims should be interpreted as meaning “one or more”. It should be further understood that the terms “comprising,” “including,” “containing,” and “comprising” as used in the embodiments of this application specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The term “and / or” as used in the embodiments of this application includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms used in the embodiments of this application, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains in light of the embodiments of this application. It should be further understood that unless explicitly defined in the embodiments of this application, terms such as “belong to” as defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the embodiments of this application and related technologies, and should not be interpreted in an idealized or overly formal manner.

[0055] In the following description, numerous specific details are set forth to provide a thorough understanding of this application, which can be practiced without some or all of these specific details. In other instances, well-known processing structures and / or processes have not been described in detail to avoid unnecessarily obscuring this application. It should also be understood that, in some cases, unless otherwise specifically apparent to those skilled in the art, a feature or element described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Various embodiments of this application are described in detail below with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of embodiments of this application. Well-known technical details may have been omitted to avoid obscuring the features and aspects of the embodiments of this application.

[0056] It should be noted that the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0057] Figure 1 This is a partial schematic diagram of a phase-change memory (PCM) 1000 provided according to some aspects of this application. See also Figure 1As shown, the PCM1000 may include: a first conductive line 1100, a phase change memory unit 1200, and a second conductive line 1300 stacked sequentially. The phase change memory unit 1200 may include: an electrode layer 1210, a selection layer 1220, an electrode layer 1230, a phase change memory layer 1240, and an electrode layer 1250. This PCM can utilize heating and quenching of the phase change memory layer to allow the phase change memory layer 1240 to switch between an amorphous and crystalline state, thereby storing data by utilizing the difference in resistivity between the amorphous and crystalline states of the phase change memory layer 1240.

[0058] Figure 2 This is a partial equivalent circuit diagram of a phase-change memory provided according to some aspects of this application. Figure 2As shown, the phase-change memory 1000 includes a memory array consisting of nine phase-change memory cells; three first conductive lines 1100u1, 1100u2, and 1100u3 extending parallel to the y-direction; and three second conductive lines 1300u1, 1200u2, and 1300u3 extending parallel to the x-direction. In each phase-change memory cell, the gating layer 1220 can be equivalent to a gating element, and the phase-change memory layer 1240 can be equivalent to a variable resistor. That is, each phase-change memory cell can be equivalent to a variable resistor and a gating element connected in series. The phase-change memory cell can be electrically connected to a first conductive line 1100 through one end of the gating element and to a second conductive line 1300 through one end of the variable resistor. Based on this equivalence, when programming operation is required for phase-change memory cell S, but not for phase-change memory cells a, b, and c, phase-change memory cell S is the selected memory cell, and phase-change memory cells a, b, and c are the unselected memory cells. At this time, a first bit line voltage (-Vll) can be applied to phase-change memory cell S through the first conductive line 1100s, and a first word line voltage (Vhh) can be applied to phase-change memory cell S through the second conductive line 1300s, making the voltage (Vhh+Vll) applied to phase-change memory cell S sufficiently large to perform programming operation on phase-change memory cell S. Simultaneously, a second bit line voltage (Vub) is applied to phase-change memory cells a and c through the first conductive line 1100u1 or 1100u2, and a second word line voltage (Vuw) is applied to phase-change memory cells b and c through the second conductive line 1300u1 or 1300u2. Specifically, the absolute value of the second bit line voltage is less than the absolute value of the first bit line voltage, and the absolute value of the second word line voltage is less than the absolute value of the first word line voltage. It should be noted that while applying the first bit line voltage (-Vll) to the selected phase-change memory cell S through the first conductive line 1100s, the first bit line voltage (-Vll) is also applied to the phase-change memory cell b connected in series with the first conductive line 1100s. Similarly, while applying the first word line voltage (Vhh) to the selected phase-change memory cell S through the second conductive line 1300s, the first word line voltage (Vhh) is also applied to the phase-change memory cell a connected in series with the second conductive line 2300s.

[0059] Therefore, for Figure 2 The voltages of phase-change memory cells S, a, b, and c in the shown memory array are as follows:

[0060] VS=Vhh+Vll (1)

[0061] Va=Vhh-Vub (2)

[0062] Vb=Vuw+Vll (3)

[0063] Vc = Vuw - Vub (4)

[0064] Where VS is the voltage of phase change memory cell S; Va is the voltage of phase change memory cell a; Vb is the voltage of phase change memory cell b; and Vc is the voltage of phase change memory cell c.

[0065] Figure 3 This is a voltage-current characteristic curve of a phase-change memory provided according to some aspects of this application. See also... Figure 3 As shown, when performing a set operation (or programming operation) on a phase-change memory cell, when the voltage on the phase-change memory cell increases to a value greater than the first threshold voltage (Vt1) and less than the second threshold voltage (Vt2), the phase-change storage layer in the phase-change memory cell changes from an amorphous state to a crystalline state. The resistance of the crystalline phase-change storage layer is less than that of the amorphous phase-change storage layer. When performing a read operation on the phase-change memory cell, the voltage applied to the storage cell is the read voltage (Vsense), which is greater than the first threshold voltage and less than the second threshold voltage. When performing a reset operation on the phase-change memory cell, when the voltage on the phase-change memory cell increases to a value greater than the second threshold voltage, the phase-change storage layer in the phase-change memory cell changes from a crystalline state to an amorphous state. The resistance of the crystalline phase-change storage layer is less than that of the amorphous phase-change storage layer.

[0066] Figure 4 This is a voltage-current characteristic curve of a gating layer of a phase-change memory (PCM) according to some aspects of this application. It should be understood that when a selected PCM cell performs a programming or reading operation, the gating layer, which acts as a gating element, must first be turned on before a voltage can be applied to the PCM layer of the selected PCM cell to achieve data writing or reading. The current-voltage characteristic of this gating element is as follows: Figure 4 As shown, the gating element needs a large switching ratio to meet the requirements of low leakage current and strong drive current. It is precisely because of this large switching ratio that a huge inrush current is generated when the voltage across the gating element reaches a certain value, at the moment of activation. A large inrush current severely affects the durability of the various hardware components contained in the phase-change memory, and can even directly lead to the breakdown and failure of these components. At the same time, a large inrush current also causes read disturb and write disturb, significantly reducing device reliability. Currently, inrush current has become a common problem for high-speed switching ratio gating elements.

[0067] Specifically, see Figure 5 As shown Figure 1The energy band structure of the phase-change memory is shown. According to... Figure 5 As shown, from an energy band perspective, the inrush current originates from the energy band change at the instant the gating element is turned on, causing the energy band barrier to disappear and a large number of non-equilibrium carriers to flood into the metal. This inrush current formed by these non-equilibrium carriers quickly relaxes to a steady state under the influence of the RLC circuit. The non-equilibrium carriers themselves behave similarly to carriers during breakdown, and the excessive inrush current leads to intense heating, further exacerbating thermally excited carriers; the two reinforce each other. The inrush of non-equilibrium carriers damages the conductive path that is about to form in the gating element, resulting in a soft failure; in more severe cases, it can even damage the various hardware components contained in the memory, leading to a hard failure.

[0068] To address the aforementioned problems, embodiments of this application provide another phase-change memory. Specifically, as shown in the example... Figure 6 As shown. The phase-change memory 2000 may include:

[0069] A first conductive line 2100, a second conductive line 2300, and a first phase-change memory unit 2200 between the first and second conductive lines; wherein the first and second conductive lines are parallel to the same plane and perpendicular to each other; the first phase-change memory unit is perpendicular to both the first and second conductive lines; and the first phase-change memory unit 2200 includes: a first electrode layer 2210, a first gate layer 2220, a second electrode layer 2230, a first phase-change memory layer 2240, and a third electrode layer 2250 stacked sequentially; wherein...

[0070] The first phase change memory cell further includes at least one of the following: a first leakage barrier layer 2260 stacked in front of the first electrode layer, a second leakage barrier layer 2270 stacked between the second electrode layer and the first phase change memory layer, and a third leakage barrier layer 2280 stacked after the third electrode layer; the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer are used to reduce the transient inrush current formed when the first gate layer is turned on.

[0071] Here, the constituent materials of the first conductive line 2100 and the second conductive line 2300 may include conductive materials. These conductive materials may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or polycrystalline silicon. The constituent materials of the first electrode layer, the second electrode layer, and the third electrode layer may include, but are not limited to, W, Co, Cu, Al, carbon, polycrystalline silicon, doped silicon, silicides, or any combination thereof. For example, the constituent materials of the first electrode layer, the second electrode layer, and the third electrode layer may be amorphous carbon, such as α-phase carbon. The function of the first electrode layer, the second electrode layer, and the third electrode layer is to conduct electrical signals. The constituent material of the first gating layer 2220 may include: an Ovonic threshold switching (OTS) material, such as ZnaTeb, GeaTeb, NbaOb, or SiaAsbTec. The material of the first phase change storage layer may include: a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material.

[0072] See Figure 6 As shown, the first electrode layer, the first gate layer, the second electrode layer, the first phase-change memory layer, and the third electrode layer are stacked sequentially. It should be noted that the first plane on which the first conductive line is set and the second plane on which the second conductive line is set are parallel to each other, and the first plane overlaps with the second plane. The phase-change memory cell 2200 is located between the first plane and the second plane, and is perpendicular to both the first plane and the second plane.

[0073] To resolve the issues mentioned above, see [link to relevant documentation]. Figure 6 As shown in the embodiments of this application, the first phase change memory cell of the phase change memory further includes at least one of the following: a first leakage barrier layer 2260 stacked before the first electrode layer, a second leakage barrier layer 2270 stacked between the second electrode layer and the first phase change memory layer, and a third leakage barrier layer 2280 stacked after the third electrode layer. The first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are used to reduce the transient inrush current formed when the first gate layer is turned on.

[0074] It should be noted that, according to the design, the first, second, and third leakage barrier layers have sufficient leakage current. This allows them not only to slow down the rate at which a large number of non-equilibrium carriers surge from the metal when the first gate layer is turned on, thus reducing the magnitude of the transient inrush current, but also to ensure the drive current required for the phase-change memory cell to perform programming or read operations. In other words, the first, second, and third leakage barrier layers provided in this embodiment will not be switched off or on during the entire operation of the phase-change memory (OTS activation, programming, or read operations), but will have sufficient leakage current throughout the entire process. Since even a large leakage current is limited, it is still much smaller than the transient inrush current. Therefore, by adding at least one of the first, second, and third leakage barrier layers, these layers act as a valve. This valve allows current to flow, but the current is limited (only by the magnitude of the leakage current), thus slowing down the rate at which non-equilibrium carriers surge into the metal and reducing the magnitude of the transient inrush current. Simultaneously, during programming or reading operations, the leakage current is ensured to be sufficient to meet the required drive current, preventing any impact on subsequent programming or reading operations. In other words, the principle behind how these first, second, and third leakage barrier layers solve the technical problem of this application lies in the fact that although the first, second, and third leakage barrier layers are very thin, their large leakage current prevents severe band bending. Carriers are primarily transported via defect level jumps rather than tunneling. Furthermore, since leakage current has an upper limit and is much smaller than transient inrush current, it slows down the rate at which a large number of non-equilibrium carriers flow into the metal, thereby reducing the magnitude of the transient inrush current.

[0075] Based on the above requirements for the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer, in some embodiments, the bandgap width of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer is greater than the bandgap width of the first gate layer, and the thickness of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer is less than the thickness of the first gate layer.

[0076] It should be noted that the bandgap widths of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer should be much larger than the bandgap width when the first gate layer is turned off, and at least close to the bandgap width of the first phase change storage layer in the crystalline state (for example, the bandgap width of the first phase change storage layer in the crystalline state is about 0.5 electron volts (eV)).

[0077] In practical applications, increasing the bandgap width of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer can be achieved by at least one of the following: reducing the thickness of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer; increasing the number of defects contained in the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer; or using a wide bandgap material.

[0078] Based on this, in some embodiments, the materials constituting the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer include wide bandgap semiconductor materials.

[0079] Here, the thickness and defects contained in the wide bandgap semiconductor material should satisfy the requirement that the bandgap width of the wide bandgap semiconductor material can reduce the transient inrush current formed when the gate layer is turned on, and that the leakage current of the wide bandgap semiconductor material can meet the driving requirements of the first phase change memory layer.

[0080] In some embodiments, the wide bandgap semiconductor material may include at least one of the following: silicon oxide; silicon nitride; silicon carbide; carbonitride. Furthermore, the wide bandgap semiconductor material can be formed by controlling the timing and / or reactants of the process.

[0081] It should be noted that, based on the above description of the requirements that the first, second, and third leakage barrier layers must meet, a wide bandgap semiconductor material is used in the first, second, and third leakage barrier layers. The thickness and defects contained in this wide bandgap semiconductor material should be such that the bandgap width of the wide bandgap semiconductor material can reduce the transient inrush current generated when the gate layer is turned on, and that the leakage current of the wide bandgap semiconductor material can meet the driving requirements of the first phase-change memory layer. In some embodiments, the thickness of the wide bandgap semiconductor material is on the nanometer scale.

[0082] In practical applications, due to the relatively small thickness of wide bandgap semiconductor materials, their formation can be achieved by controlling the processing time and / or reactants. In other words, because of the small thickness of wide bandgap semiconductor materials, the thickness of a film intentionally grown specifically for this material often cannot meet the requirements. Therefore, the film of this wide bandgap semiconductor material is not specifically manufactured, but rather its formation is assisted by controlling the processing time and / or reactants during the manufacturing process.

[0083] Furthermore, the formation of this wide-bandgap semiconductor material thin film primarily depends on the matching process technology, ensuring compatibility with the deposition and etching processes of other film layers within the cell, while also meeting the cross-contamination restrictions of the production line. Therefore, this wide-bandgap semiconductor material can be formed using semiconductor processes. Moreover, this wide-bandgap semiconductor material can utilize materials such as silicon, oxygen, carbon, and nitrogen. Thin films formed from these materials exhibit different etching selectivity ratios compared to films formed from other materials, which is beneficial for improving the controllability of the etching process, resulting in a more stable structure, reducing the likelihood of element diffusion, providing greater elemental versatility, lowering the risk of cross-contamination, and enhancing stress control capabilities.

[0084] Specifically, see Figure 7 shown Figure 6 The band structure of a phase-change memory. In the interconnected structure of Metal-OTS-Metal, a very thin, wide-bandgap material is added as a stabilizing barrier to block / limit the inrush current formed by the influx of non-equilibrium carriers, thereby controlling the formation of the inrush current.

[0085] Theoretically, multiple locations can be used to set the first, second, and third leakage barrier layers. However, in practical applications, setting multiple leakage barrier layers increases additional resistance, which reduces the resistance window and detection sensitivity of the memory cell; it also increases the overall voltage signal detection range, interfering with the design of the logic circuit; and because the operating current of the phase-change memory cell is high, the barrier layer resistance is prone to heating, significantly increasing the power consumption of the memory chip and potentially enhancing thermal crosstalk, thus affecting the chip's reliability. Therefore, within a reasonable range, it is preferable to select only one location to set the leakage barrier layer. According to experimental results, the first leakage barrier layer is more effective than the second and third leakage barrier layers in reducing inrush current.

[0086] In some embodiments, the phase-change memory 2000 further includes:

[0087] Substrate;

[0088] A first isolation structure is alternately disposed on the substrate surface along a first direction, alongside the first conductive line and the first phase change memory cell stacked thereon; wherein, the first direction is parallel to the substrate surface;

[0089] The second isolation structure is alternately disposed on the substrate surface alongside the first phase change memory cell and the second conductive line stacked together along the second direction; wherein the second direction is parallel to the substrate and perpendicular to the first direction.

[0090] For example, the substrate refers to a material on which subsequent material layers are added. The substrate may include semiconductor materials, such as silicon, germanium, or gallium arsenide.

[0091] Here, the first isolation structure is used to electrically isolate adjacent first phase-change memory cells 2200 in a first direction. The first isolation structure is also used to electrically isolate adjacent first conductive lines 2100 in the first direction. It should be noted that during the phase change process of the first phase-change memory layer 2250, a significant amount of heat is generated. Therefore, to reduce crosstalk between adjacent first phase-change memory cells 2200, the first isolation structure is also used for thermal isolation. Figure 6 The phase-change memory shown has a first direction parallel to the x-axis and a second direction parallel to the y-axis (not shown). The y-axis is perpendicular to the zox plane.

[0092] In some embodiments, the first isolation structure includes: a first isolation layer disposed perpendicular to the first direction, covering the sidewall of the third electrode layer and the sidewall of the first phase change storage layer;

[0093] The second isolation layer is disposed perpendicular to the first direction and covers the sidewall of the second electrode layer, the sidewall of the first gate layer, the sidewall of the first electrode layer, and the sidewall of the first conductive line.

[0094] Exemplarily, a first isolation layer is located between the second isolation layer and the third electrode layer 2260, and between the second isolation layer and the phase change memory layer 2250. The first isolation layer can be used to encapsulate the sidewalls of the first phase change memory cell 2200 parallel to the second direction. Exemplarily, the first isolation layer may include a first insulating nitride layer and a first oxide layer, wherein the first insulating nitride is located between the first oxide layer and the third electrode layer 2260, and between the first insulating oxide layer and the first phase change memory layer 2250. The second isolation layer can be used to thermally isolate adjacent first phase change memory cells 2200. Exemplarily, the second isolation layer may include a second insulating nitride layer and a second oxide layer with lower thermal conductivity, wherein the second insulating nitride layer is located between the second oxide layer and the first isolation layer, and the second insulating nitride layer is located between the second oxide layer and the second electrode layer 2240, the first gate layer 2230, the first electrode layer 2220, and the first conductive line 2100, respectively.

[0095] Here, the second isolation structure is used to electrically isolate adjacent memory cells 1200 in the second direction. The second isolation structure is also used to electrically isolate adjacent second conductive lines 1300 in the second direction. It should be noted that during the phase change process of the phase change memory layer 1250, a significant amount of heat is generated. Therefore, to reduce crosstalk between adjacent memory cells 1200, the second isolation structure is also used for thermal isolation. It should also be noted that the second isolation structure and the first isolation structure may contain the same constituent materials. The constituent materials of the second isolation structure and the first isolation structure may include materials with low thermal conductivity.

[0096] In some embodiments, the second isolation structure may include:

[0097] A third isolation layer is disposed perpendicular to the second direction and covers the sidewall of the third electrode layer and the sidewall of the first phase change storage layer;

[0098] A fourth isolation layer is disposed perpendicular to the second direction and covers the sidewall of the second electrode layer, the sidewall of the first gate layer, the sidewall of the first electrode layer, and the sidewall of the second conductive line.

[0099] Here, a third isolation layer can be used to encapsulate the sidewalls of the first phase-change memory cell 2200 parallel to the first direction. Exemplarily, the third isolation layer may include a third insulating nitride layer and a third oxide layer, wherein the third insulating nitride layer is located between the third oxide layer and the second conductive line 2300, the third electrode layer 2260, and the first phase-change memory layer 2250, respectively. A fourth isolation layer can be used to thermally isolate adjacent first phase-change memory cells 2200. Exemplarily, the fourth isolation layer may include a fourth insulating nitride layer and a fourth oxide layer with lower thermal conductivity, wherein the fourth insulating nitride layer is located between the fourth oxide layer and the third isolation layer, and the fourth insulating nitride layer is located between the fourth oxide layer and the second electrode layer 2240, the first gate layer 2230, and the first electrode layer 2220, respectively.

[0100] It should be noted that, since the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are also layers stacked in the phase change memory cell, the first isolation structure includes the first isolation layer and the second isolation layer; and the second isolation structure includes the third isolation layer and the fourth isolation layer, which also cover the sidewalls of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer.

[0101] In some embodiments, the phase-change memory further includes:

[0102] Along a direction parallel to the extension of the first conductive line, the first phase change storage layer has a first width, and the second electrode layer has a second width; wherein the second width is greater than the first width;

[0103] And / or,

[0104] Along the extension direction parallel to the second conductive line, the first phase change storage layer has a third width, and the second electrode layer has a fourth width; wherein the fourth width is greater than the third width.

[0105] For example, the first conductive line extends in a direction parallel to the second direction, and the second conductive line extends in a direction parallel to the first direction. The bottom of the phase-change memory layer is in contact with the top of the second electrode layer. It is understood that for each phase-change memory cell, in a direction parallel to the substrate surface, the bottom area of ​​the phase-change memory layer is smaller than the top area of ​​the second electrode layer. For phase-change memory layers of the same thickness, compared to a phase-change memory layer with a bottom area greater than or equal to the top area of ​​the second electrode layer, the phase-change memory cell provided in this embodiment reduces the bottom area of ​​the phase-change memory layer, thereby reducing the volume of the phase-change memory layer and consequently reducing the energy required for the phase-change memory layer to undergo a phase change, which is beneficial for reducing the power consumption of the phase-change memory.

[0106] In some embodiments, the phase change memory 2000 includes at least two phase change memory arrays stacked together, each phase change memory array including a plurality of phase change memory cells; wherein a first conductive line or a second conductive line is disposed between two adjacent phase change memory arrays.

[0107] Therefore, in order to solve the technical problems provided by the embodiments of this application, in some embodiments, such as Figure 8 Another type of phase-change memory (PCM) is shown. This PCM 2000 may further include: a third conductive line 2500 and a second PCM storage unit 2400 between the second conductive line and the third conductive line; wherein the third conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the second PCM storage unit is perpendicular to both the second conductive line and the third conductive line; and the second PCM storage unit 2400 includes: a fourth electrode layer 2410, a second gate layer 2420, a fifth electrode layer 2430, a second PCM storage layer 2440, and a sixth electrode layer 2450 stacked sequentially; wherein...

[0108] The second phase change memory cell further includes at least one of the following: a fourth leakage barrier layer 2460 stacked before the fourth electrode layer, a fifth leakage barrier layer 2470 stacked between the fifth electrode layer and the second phase change memory layer, and a sixth leakage barrier layer 2480 stacked after the sixth electrode layer; the fourth leakage barrier layer, the fifth leakage barrier layer, and the sixth leakage barrier layer are used to reduce the transient inrush current formed when the second gate layer is turned on.

[0109] here, Figure 8 The second phase-change memory cell shown is similar to the one described above. Figure 6 The structure and function of the first phase change memory unit are the same as those of the first phase change memory unit. Therefore, the second phase change memory unit can be understood by referring to the first phase change memory unit described above. Its specific functions and structure will not be repeated here.

[0110] Based on the same inventive concept, embodiments of this application also provide a method for manufacturing a phase-change memory, specifically as follows: Figure 9 As shown, the manufacturing method may include:

[0111] S901: Form the first conductive line;

[0112] S902: Forming a first phase-change memory cell; wherein the formed first phase-change memory cell includes: a first electrode layer, a first gate layer, a second electrode layer, a first phase-change memory layer, and a third electrode layer stacked sequentially; and the first phase-change memory cell further includes at least one of the following: a first leakage barrier layer stacked before the first electrode layer, a second leakage barrier layer stacked between the second electrode layer and the first phase-change memory layer, and a third leakage barrier layer stacked after the third electrode layer; the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are used to reduce the transient inrush current formed when the first gate layer is turned on;

[0113] S903: Forms a second conductive line.

[0114] It should be noted that,

[0115] In some embodiments, such as Figure 10 As shown, the manufacturing method may further include:

[0116] S904: Form a second phase-change memory cell; wherein the formed second phase-change memory cell includes: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer stacked sequentially; and the second phase-change memory cell further includes at least one of the following: a fourth leakage barrier layer stacked before the fourth electrode layer, a fifth leakage barrier layer stacked between the fifth electrode layer and the second phase-change memory layer, and a sixth leakage barrier layer stacked after the sixth electrode layer; the fourth leakage barrier layer, the fifth leakage barrier layer, and the sixth leakage barrier layer are used to reduce the transient inrush current formed when the second gate layer is turned on;

[0117] S905: Forms the third conductive line.

[0118] It should be noted that the fabrication method described here is based on the aforementioned structure, and any process capable of achieving the above-mentioned technical effects is acceptable. Semiconductor processes are preferred based on the foregoing description. Specific process parameters, such as duration and reactants, can be adjusted according to actual circumstances.

[0119] Based on the same inventive concept, embodiments of this application also provide a memory system, including: one or more of the aforementioned phase change memories and a memory controller coupled to the phase change memories.

[0120] The memory system described here belongs to the same inventive concept as the aforementioned manufacturing method and phase-change memory. The terms and operations mentioned here have been described in detail above and will not be repeated here.

[0121] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those applicable to a person skilled in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined to simplify the application. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of this application should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A phase-change memory, characterized in that, include: A first conductive line, a second conductive line, and a first phase-change memory unit between the first conductive line and the second conductive line; wherein the first conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the first phase-change memory unit is perpendicular to both the first conductive line and the second conductive line; and the first phase-change memory unit includes: a first electrode layer, a first gate layer, a second electrode layer, a first phase-change memory layer, and a third electrode layer stacked sequentially; wherein... The first phase-change memory cell further includes at least one of the following: a first leakage barrier layer stacked before the first electrode layer, a second leakage barrier layer stacked between the second electrode layer and the first phase-change memory layer, and a third leakage barrier layer stacked after the third electrode layer; the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are used to reduce the transient inrush current formed when the first gate layer is turned on; the bandgap width of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer is greater than the bandgap width of the first gate layer, and the thickness of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer is less than the thickness of the first gate layer.

2. The phase-change memory according to claim 1, characterized in that, The materials constituting the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer include wide bandgap semiconductor materials.

3. The phase-change memory according to claim 2, characterized in that, The wide bandgap semiconductor material includes at least one of the following: silicon oxide; silicon nitrides; Silicon carbide; Carbon and nitride compounds.

4. The phase-change memory according to claim 2, characterized in that, The thickness and defects contained in the wide bandgap semiconductor material should be such that the bandgap width of the wide bandgap semiconductor material can reduce the transient inrush current formed when the gate layer is turned on, and that the leakage current of the wide bandgap semiconductor material can meet the driving requirements of the first phase change memory layer.

5. The phase-change memory according to claim 4, characterized in that, The wide bandgap semiconductor material is formed by controlling the timing and / or reactants of the process.

6. The phase-change memory according to claim 1, characterized in that, The phase-change memory further includes: a third conductive line and a second phase-change memory unit between the second conductive line and the third conductive line; wherein the third conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the second phase-change memory unit is perpendicular to both the second conductive line and the third conductive line; and the second phase-change memory unit includes: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer stacked sequentially; wherein... The second phase change memory cell further includes at least one of the following: a fourth leakage barrier layer stacked before the fourth electrode layer, a fifth leakage barrier layer stacked between the fifth electrode layer and the second phase change memory layer, and a sixth leakage barrier layer stacked after the sixth electrode layer; the fourth leakage barrier layer, the fifth leakage barrier layer, and the sixth leakage barrier layer are used to reduce the transient inrush current formed when the second gate layer is turned on.

7. The phase-change memory according to claim 1, characterized in that, The phase-change memory further includes: Substrate; A first isolation structure is alternately disposed on the substrate surface along a first direction, alongside the first conductive line and the first phase change memory cell stacked thereon; wherein, the first direction is parallel to the substrate surface; The second isolation structure is alternately disposed on the substrate surface alongside the first phase change memory cell and the second conductive line stacked together along the second direction; wherein the second direction is parallel to the substrate and perpendicular to the first direction.

8. The phase-change memory according to claim 7, characterized in that, The first isolation structure includes: a first isolation layer, disposed perpendicular to the first direction, covering the sidewall of the third electrode layer and the sidewall of the first phase change storage layer; The second isolation layer is disposed perpendicular to the first direction and covers the sidewall of the second electrode layer, the sidewall of the first gate layer, the sidewall of the first electrode layer, and the sidewall of the first conductive line.

9. The phase-change memory according to claim 7, characterized in that, The second isolation structure includes: A third isolation layer is disposed perpendicular to the second direction and covers the sidewall of the third electrode layer and the sidewall of the first phase change storage layer; A fourth isolation layer is disposed perpendicular to the second direction and covers the sidewall of the second electrode layer, the sidewall of the first gate layer, the sidewall of the first electrode layer, and the sidewall of the second conductive line.

10. The phase-change memory according to claim 1, characterized in that, The phase-change memory further includes: Along the extension direction parallel to the first conductive line, the first phase change storage layer has a first width, and the second electrode layer has a second width; wherein the second width is greater than the first width; And / or, Along the extension direction parallel to the second conductive line, the first phase change storage layer has a third width, and the second electrode layer has a fourth width; wherein the fourth width is greater than the third width.

11. A method for manufacturing a phase-change memory, characterized in that, include: Form the first conductive line; The first phase-change memory cell is formed; Form a second conductive line; The first phase-change memory cell comprises: a first electrode layer, a first gate layer, a second electrode layer, a first phase-change memory layer, and a third electrode layer stacked sequentially; and the first phase-change memory cell further comprises at least one of the following: a first leakage barrier layer stacked before the first electrode layer, a second leakage barrier layer stacked between the second electrode layer and the first phase-change memory layer, and a third leakage barrier layer stacked after the third electrode layer; the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are used to reduce the transient inrush current formed when the first gate layer is turned on; the bandgap width of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer is greater than the bandgap width of the first gate layer, and the thickness of the first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer is less than the thickness of the first gate layer.

12. The manufacturing method according to claim 11, characterized in that, Also includes: Forming a second phase-change memory cell; Forming a third conductive line; The second phase-change memory cell includes: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer stacked sequentially; and the second phase-change memory cell further includes at least one of the following: a fourth leakage barrier layer stacked before the fourth electrode layer, a fifth leakage barrier layer stacked between the fifth electrode layer and the second phase-change memory layer, and a sixth leakage barrier layer stacked after the sixth electrode layer; the fourth leakage barrier layer, the fifth leakage barrier layer, and the sixth leakage barrier layer are used to reduce the transient inrush current formed when the second gate layer is turned on.

13. A memory system, characterized in that, include: One or more phase-change memories according to any one of claims 1 to 10 and a memory controller coupled to said phase-change memory.

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