Techniques for tracking modifications to contents of memory regions

Abstract

Address translation circuit (20) translates virtual addresses into physical addresses by referencing intermediate-level page tables and final-level page tables. Final-level descriptors within final-level page tables identify address translation data for associated memory regions. Intermediate-level descriptors within intermediate-level page tables identify intermediate address translation data for associated page tables at the next level below these page tables. Page table update circuit (35) maintains state information within each final-level and intermediate-level descriptor and updates this state information from a clean state to a dirty state: in these final-level descriptors, to indicate that modification of the contents of the associated memory region is permitted; in these intermediate-level descriptors, to indicate that an update from the clean state to the dirty state has occurred within the state information of any final-level descriptor accessed via this intermediate-level descriptor.

Description

Background Technology

[0001] This article describes a technique for tracking modifications to the contents of memory regions.

[0002] There are many situations where it can be useful to perform data processing operations to determine whether any modifications have been made to a memory region. For example, processing circuitry may be required to perform processing operations on data stored in a memory address range, and if it can be determined that the data has not changed since the last processing operation was performed on the data values ​​in that memory address range, a significant reduction in processing requirements may occur.

[0003] As a specific example, a graphics processing unit (GPU) may be instructed to perform graphics rendering operations on blocks of data identified by memory address ranges. Such a process can be used to generate one or more image frames for storage in an associated frame buffer. Typically, frames are divided into blocks and rendering is performed on individual blocks. Once a block is rendered, it can be determined whether the rendered block differs from the corresponding block rendered in a previous rendering cycle, and if so, some bandwidth savings can be achieved by not needing to write the newly rendered block to the associated frame buffer.

[0004] However, such methods still require rendering the input data in each rendering cycle, and it would be highly desirable to be able to detect whether any data in the input data has changed since the previous rendering cycle before rendering. Specifically, if such a determination can be made, in some cases rendering can be completely omitted, thus resulting in significant performance benefits and / or energy savings. Summary of the Invention

[0005] In one exemplary arrangement, an apparatus is provided, comprising: an address translation circuit for translating virtual addresses specified by a processing circuit into corresponding physical addresses of a memory system based on address translation data obtained from a hierarchical arrangement of page tables, the hierarchical arrangement of page tables including intermediate-level page tables and final-level page tables; each final-level page table including a plurality of final-level descriptors, each final-level descriptor identifying address translation data of an associated memory region; each intermediate-level page table including a plurality of intermediate-level descriptors, each intermediate-level descriptor identifying intermediate address translation data for identifying an associated page table at the next level in the hierarchical arrangement; and a page table update circuit for updating status information. The state information is maintained within each final-level descriptor, and the page table update circuitry is arranged to update the state information of a given final-level descriptor from a clean state to a dirty state to indicate that modification of the contents of the associated memory region is permitted; wherein the page table update circuitry is further arranged to maintain the state information within intermediate-level descriptors provided in at least a subset of intermediate-level page tables, such that for a given intermediate-level descriptor in which the state information is maintained, the page table update circuitry is arranged to update the state information of that given intermediate-level descriptor from a clean state to a dirty state to indicate that an update from a clean state to a dirty state has occurred in the state information of any final-level descriptor accessed via that intermediate-level descriptor.

[0006] In another exemplary arrangement, a method for tracking modifications to the contents of a memory region is provided, the method comprising: employing address translation circuitry to translate virtual addresses specified by processing circuitry into corresponding physical addresses of the memory system with reference to address translation data obtained from a hierarchical arrangement of page tables, the hierarchical arrangement of page tables including both intermediate-level page tables and final-level page tables; arranging each final-level page table to include a plurality of final-level descriptors, each final-level descriptor identifying address translation data of an associated memory region; arranging each intermediate-level page table to include a plurality of intermediate-level descriptors, each intermediate-level descriptor identifying intermediate address translation data used to identify an associated page table at the next level in the hierarchical arrangement; and employing... Page table update circuitry is used to maintain state information within each final-level descriptor. This circuitry is configured to update the state information of a given final-level descriptor from a clean state to a dirty state, indicating that modification of the contents of the associated memory region is permitted. The page table update circuitry is also configured to maintain state information within intermediate-level descriptors provided in at least a subset of intermediate-level page tables, such that for a given intermediate-level descriptor in which state information is maintained, the page table update circuitry is configured to update the state information of that given intermediate-level descriptor from a clean state to a dirty state, indicating that an update from a clean state to a dirty state has occurred in the state information of any final-level descriptor accessed via that intermediate-level descriptor.

[0007] In yet another exemplary arrangement, an apparatus is provided, comprising: an address translation device for translating virtual addresses specified by processing circuitry into corresponding physical addresses of a memory system by referring to address translation data obtained from a hierarchical arrangement of page tables, the hierarchical arrangement of page tables including both intermediate-level page tables and final-level page tables; each final-level page table including a plurality of final-level descriptors, and each final-level descriptor identifying address translation data of an associated memory region; each intermediate-level page table including a plurality of intermediate-level descriptors, and each intermediate-level descriptor identifying intermediate address translation data for identifying an associated page table at the next level in the hierarchical arrangement; and a page table updating device for... The page table update means maintains state information within each final-level descriptor and updates the state information of a given final-level descriptor from a clean state to a dirty state to indicate that modification of the contents of the associated memory region is permitted. The page table update means also maintains state information within intermediate-level descriptors provided in at least a subset of intermediate-level page tables, such that for a given intermediate-level descriptor in which state information is maintained, the page table update means is arranged to update the state information of that given intermediate-level descriptor from a clean state to a dirty state to indicate that an update from a clean state to a dirty state has occurred in the state information of any final-level descriptor accessed via that intermediate-level descriptor. Attached Figure Description

[0008] The present technology will be further described by way of illustration only, with reference to examples of the present technology shown in the accompanying drawings, wherein:

[0009] Figure 1 A data processing system according to an exemplary arrangement is shown;

[0010] Figure 2 It is a schematic diagram illustrating the process of translating virtual addresses into physical addresses;

[0011] Figure 3 This schematically illustrates a multi-level page table traversal that includes a single-level address translation process;

[0012] Figure 4A The illustration schematically shows information that can be provided within a descriptor according to an exemplary specific implementation, and Figure 4B Provides more detailed information on the update status that can be provided within such descriptors;

[0013] Figure 5 This is a flowchart illustrating the process performed according to the techniques described herein when a request is received to update a page in memory whose associated last-level descriptor indicates a clean state;

[0014] Figure 6 This is shown in more detail in an exemplary specific implementation to achieve... Figure 5 The flowchart of the final step;

[0015] Figure 7 This is shown in more detail in an alternative exemplary implementation to achieve... Figure 5 The flowchart of the final step;

[0016] Figure 8 The illustration schematically shows a possible implementation according to an exemplary embodiment. Figure 1 Different cache structures are provided within the address translation cache;

[0017] Figure 9A and Figure 9B A flowchart is provided illustrating how a cached copy of a descriptor provided within an address translation cache can be used, according to an exemplary specific implementation, when determining which descriptors need to be updated;

[0018] Figure 10 This is a flowchart illustrating, according to an exemplary embodiment, how the techniques described herein can be used to help reduce the rendering workload of the graphics processing unit; and

[0019] Figure 11 This is a diagram based on an exemplary implementation of a data processing system. Detailed Implementation

[0020] According to one exemplary embodiment, an apparatus is provided having address translation circuitry for translating a virtual address specified by processing circuitry into a corresponding physical address in a memory system. The address translation circuitry performs the translation with reference to address translation data obtained from a hierarchical arrangement of page tables, the hierarchical arrangement of which includes both intermediate-level page tables and final-level page tables.

[0021] Each final-level page table includes multiple final-level descriptors, and each final-level descriptor identifies address translation data for an associated memory region. The associated memory region can be defined in various ways, but in one exemplary implementation, each region of memory may include a memory page.

[0022] Each intermediate-level page table includes multiple intermediate-level descriptors, and each intermediate-level descriptor identifies intermediate address translation data used to identify the associated page table at the next level in the hierarchical layout.

[0023] Using the provided virtual address, the address translation circuit can thus be arranged to traverse multiple different levels of the hierarchical arrangement of the page table, starting from the lowest level (often called L0 level) and continuing until the last level page table is identified, where a portion of the virtual address is used to identify a specific last-level descriptor within that last-level page table, thus identifying a specific region of the memory.

[0024] According to the techniques described herein, page table update circuitry is arranged to maintain state information within each last-level descriptor. This state information may take various forms, but according to the techniques described herein, it provides information about whether any modifications have been made to the contents of the associated memory region identified by the last-level descriptor. The page table update circuitry is arranged to update the state information of a given last-level descriptor from a clean state to a dirty state to indicate that modification of the contents of the associated memory region is permitted. When a write is permitted to be performed in the associated memory region, an update of the state information to a dirty state may be performed, for example, and the precise timing of the update from a clean state to a dirty state may vary depending on the specific implementation. For example, the update to a dirty state may occur before the write is performed, or it may occur as a result of the write being performed.

[0025] A clean state can take many forms, but in one exemplary implementation, when the status information indicates a clean state, it means that the associated memory region is currently read-only, but this can be changed to allow writing to the associated memory region upon receiving a request from the processing circuitry. Therefore, once such a request is received, this can be used to trigger a transition of the status information from a clean state to a dirty state.

[0026] Returning to the previously discussed problem of determining when the contents of a memory block (e.g., a memory block that the GPU can reference when attempting to render an image frame) have been modified, in principle, address translation circuitry could be used to traverse the hierarchical layout of the page table to identify each last-level descriptor associated with a memory region within the total address range of interest. However, traversing the entire hierarchical layout of the page table to reach the last-level descriptors is time-consuming, and there may be situations where a large number of last-level descriptors need to be accessed to cover the entire address range of interest and determine whether any of these last-level descriptors has status information indicating a dirty state.

[0027] However, according to the technique described herein, the page table update circuitry is further arranged to maintain state information within intermediate-level descriptors provided in at least a subset of intermediate-level page tables. Specifically, for a given intermediate-level descriptor in which state information is maintained, the page table update circuitry may be arranged to update the state information of that given intermediate-level descriptor from a clean state to a dirty state, indicating that an update from a clean state to a dirty state has occurred in the state information of any final-level descriptor accessed via that intermediate-level descriptor.

[0028] It should be understood that when an intermediate-level descriptor is in the penultimate level of a hierarchical arrangement, the final-level descriptor can be accessed via the intermediate-level descriptor, and thus the final-level page table including that final-level descriptor is identified. However, when an intermediate-level descriptor is in another lower level of a hierarchical structure separated from the final level by one or more intermediary levels, the final-level descriptor can also be considered to be accessed via the intermediate-level descriptor. By way of example only, if a given intermediate-level descriptor within a given lower-level page table identifies a higher-level intermediate page table, and that higher-level intermediate page table provides an intermediate-level descriptor that subsequently identifies the final-level page table including the given final-level descriptor, then the given final-level descriptor is still accessed via the given intermediate-level descriptor, albeit through one or more intermediary levels of the hierarchical arrangement of page tables.

[0029] By propagating this state information back via one or more intermediate descriptors, the speed at which such state information can be referenced to determine whether any data within a specified memory address range has been modified is significantly increased. Consider an earlier GPU example where, during the current rendering cycle, the GPU is attempting to read the input data needed to render one or more image frames, which might require considering a relatively large address range (including multiple pages in memory). However, by propagating the state information back to a specific number of intermediate descriptors, a relatively small number of intermediate descriptors that need to be reviewed can be identified, and specifically, if the state information of any of those identified intermediate descriptors does not indicate a clean state, it can be determined that rendering is required. Conversely, if all relevant intermediate descriptors covering a specified address range indicate a clean state, it is known that no updates have been performed within the specified memory address range, and in this case, rendering can be omitted.

[0030] Therefore, it has been found that propagating back state information via one or more intermediate descriptors can provide an effective mechanism for checking whether content in a relatively large address range has been modified, and thus reference to such state information is a practical suggestion in various exemplary scenarios when attempting to detect whether content in a memory address range has been modified.

[0031] In one exemplary embodiment, the hierarchical arrangement of page tables includes multiple levels of page tables, and the page table update circuitry is arranged therein to maintain at least a subset of intermediate-level page tables containing state information, including intermediate-level page tables at at least one level of the hierarchical arrangement. Therefore, in such embodiments, the page table update circuitry may be arranged to maintain state information at some, but not necessarily all, intermediate levels within the hierarchical structure. For example, in some cases, it may be considered inappropriate to maintain state information at the lowest level (i.e., L0 level) because it is possible that if an attempt is made to maintain state information at that level, the state information will very quickly transition to a dirty state and thus provide no useful information. Therefore, the level at which state information is maintained can be tuned for a particular embodiment. For example, in some embodiments, it may be decided to maintain state information at only a single intermediate level, while in other embodiments, it may be decided to maintain state information at multiple, but not necessarily all, intermediate levels. When state information is maintained at multiple intermediate levels, these multiple intermediate levels may be adjacent levels within the hierarchical arrangement, but alternatively, non-adjacent levels may be selected.

[0032] There are various ways in which page table update circuitry can determine when to transition state information within an intermediate-level descriptor from a clean state to a dirty state, particularly regarding the timing of updating the associated final-level descriptor from a clean state to a dirty state. According to a first exemplary embodiment, which may be referred to as a top-down approach, the page table update circuitry can be arranged to maintain state information within intermediate-level descriptors such that an indication of a dirty state within the state information of a given intermediate-level descriptor allows modification of the contents of the associated page table at the next level in the hierarchical arrangement. As a result, the page table update circuitry is arranged to update the state information of a given final-level descriptor from a clean state to a dirty state, indicating that modification of the contents of the associated memory region is permitted once each intermediate-level descriptor, in which state information is maintained, identifies a dirty state within that state information. Therefore, according to such methods, it should be understood that setting the dirty state within a given intermediate-level descriptor is a prerequisite for allowing a transition from a clean state to a dirty state in any descriptor at a higher level in the hierarchical structure, including the relevant final-level descriptor and any intermediary-level descriptors between the given intermediate-level descriptor and that final-level descriptor.

[0033] However, according to an alternative implementation, which may be referred to as a bottom-up approach, the page table update circuitry may be arranged to perform the following actions in response to updating the state information of a given final-level descriptor from a clean state to a dirty state: indicating that modification of the contents of the associated memory region is permitted; tracing back through the levels in the hierarchical arrangement to identify each intermediate-level descriptor used to identify the final-level descriptor; and for each identified intermediate-level descriptor in which state information is held, updating the state information to indicate a dirty state if necessary. At one or more intermediate levels, it should be understood that if the relevant intermediate-level descriptor already indicates a dirty state, no update is required.

[0034] In one exemplary embodiment, the apparatus may further include an address translation cache storage for storing copies of one or more descriptors retrieved from the hierarchical arrangement of page tables. This improves performance when attempting to perform an address translation operation when the relevant descriptors are already cached in the address translation cache storage, thus eliminating the need to perform a page table traversal process in memory to identify the required descriptor. In such an embodiment, page table update circuitry may be arranged to refer to the address translation cache storage when determining which page table descriptors need to be updated when attempting to update the contents of a memory region associated with a given last-level descriptor.

[0035] In one exemplary implementation, when the address translation cache storage device stores a copy of a given last-level descriptor whose status information indicates a dirty state, the page table update circuitry is arranged to determine that page table descriptors in the hierarchical arrangement of the page table do not need to be updated. Specifically, the update of the status information in the relevant intermediate-level descriptors is performed when the last-level descriptor transitions from a clean state to a dirty state, and therefore no update is needed when encountering a last-level descriptor that is already in a dirty state.

[0036] However, in the absence of an address translation cache storage device that stores a copy of a given final-level descriptor whose state information indicates a dirty state, the page table update circuitry can be arranged to determine the analysis operations required regarding the intermediate-level descriptors used to identify the given final-level descriptor, in order to determine whether it is necessary to update the state information held for any of those intermediate-level descriptors in addition to updating the state information of the given final-level descriptor from a clean state to a dirty state.

[0037] It should be understood that there are various situations that would result in the absence of a copy of a given last-level descriptor whose status information indicates a dirty state in the address translation cache storage. For example, there might be no cache copy of a given last-level descriptor stored in the address translation cache storage. However, another situation might be that a cache copy of a given last-level descriptor exists, but its status information indicates a clean state. When considering a page table update process performed by page table update circuitry, if the required given last-level descriptor exists in the address translation cache storage, but its status information indicates a clean state, this is effectively considered a miss within the address translation cache storage, and thus triggers the analysis operation described above.

[0038] To perform analysis operations, a page table traversal process may be required to access the necessary intermediate-level descriptors in memory. However, in some cases, at least part of the analysis operation can be performed using information held in an address translation cache.

[0039] In one exemplary embodiment, the address translation cache storage device includes a translation lookup buffer to store copies of one or more last-level descriptors. In some embodiments, only last-level descriptors may be cached, but in alternative embodiments, the address translation cache storage device may also include an intermediate descriptor cache (also known as a traversal cache) to store copies of intermediate-level descriptors from page tables at one or more intermediate levels in a hierarchical arrangement of page tables. When the address translation cache storage device does include an intermediate descriptor cache, at least a portion of the above-described analysis operations can be performed with reference to the contents of the address translation cache storage device.

[0040] Specifically, in one exemplary implementation, in the absence of a translation backing buffer storing a copy of a given final-level descriptor whose state information indicates a dirty state, the page table update circuit is arranged to perform a lookup operation in the intermediate descriptor cache to attempt to trace back to a level in the hierarchical arrangement until a copy of a non-clean intermediate-level descriptor used to identify a given final-level descriptor is detected, or a lookup operation has been performed for all levels in the hierarchical arrangement where intermediate-level descriptors are cached in the intermediate descriptor cache, the non-clean intermediate-level descriptor being the intermediate-level descriptor whose state information indicates a non-clean state.

[0041] A non-clean state can take many forms, but in one example it is the previously mentioned dirty state or untracked state. For instance, an untracked state can occur when pages in memory are always marked as readable and writable, and therefore the state information does not indicate whether a modification has actually been made. Specifically, one cannot infer from an untracked state whether an associated memory page has been modified, because any modification would not result in a change in the state information.

[0042] By attempting to reference the intermediate descriptor cache to determine whether the intermediate descriptor cache stores the relevant intermediate-level descriptor in a non-clean state, this can be used to reduce the number of levels that need to be considered when determining which intermediate-level descriptors need to update their state information. Specifically, when a copy of a non-clean-state intermediate-level descriptor used to identify a given final-level descriptor is detected during a lookup operation, the page table update circuitry is then arranged to identify any intermediate-level descriptors used to identify a given final-level descriptor existing in the level between the level containing the non-clean-state intermediate-level descriptor and the final level containing the given final-level descriptor, and subsequently identify the dirty state within the state information held by any of those identified intermediate-level descriptors.

[0043] Once the address translation cache contents have been used in the manner described above to attempt to identify which intermediate-level descriptors, besides the last-level descriptors, need to be updated, any cached copies of the descriptors whose state information is being updated will typically be updated or invalidated. This ensures that the address translation circuitry does not reference outdated descriptor information in any future references to the contents of the address translation cache. Furthermore, known consistency / synchronization techniques can be used to ensure that when the page table update circuitry updates the state information of those descriptors, cached copies of the relevant descriptors held elsewhere in the system are updated or invalidated. According to one exemplary scheme, the local cached copy of each updated descriptor (i.e., the copy in the address translation cache referenced by the page table update circuitry) is updated. Additionally, each updated descriptor is written to memory, and any other cached copies of each updated descriptor held elsewhere in the system are invalidated, so that the next time the descriptor is needed, the updated version is read from memory. The consistency protocol is arranged to implement a strict ordering of steps to ensure that updated descriptors are used in all cases.

[0044] As previously described, by maintaining state information within intermediate-level descriptors, this can be used to influence the operations performed by any processing circuitry that can access those descriptors. In one exemplary embodiment, the processing circuitry is arranged such that, when determining a data processing operation to be performed by the processing circuitry, a reference is maintained within one or more intermediate-level descriptors containing state information.

[0045] As a specific example, the processing circuitry may be arranged to periodically perform graphics rendering operations with respect to data blocks identified by a memory address range. In such an implementation, the processing circuitry may be arranged to perform the following operations, at least when the current rendering cycle meets a defined criterion: issue a request to the address translation circuitry to identify a set of memory regions covered by the memory address range; determine one or more intermediate-level descriptors for identifying the final-level descriptor of the set of memory regions; and refer to state information stored in those determined intermediate-level descriptors to determine whether any updates to the data blocks have occurred since the previous rendering cycle. If it is determined that no updates to the data blocks have occurred since the previous rendering cycle, the processing circuitry is arranged to use the output of the graphics rendering operation from the previous rendering cycle instead of re-executing the graphics rendering operation.

[0046] This approach can yield significant performance and energy savings. Specifically, it should be understood that significant performance and energy savings can be achieved when it is possible to avoid performing graphics rendering operations. This also has additional benefits, such as eliminating the need to read input data, which would otherwise be required in the current graphics rendering cycle.

[0047] As described above, in some implementations, if the current rendering cycle meets certain defined criteria, the processing circuitry may issue a request to the address translation circuitry solely for the current rendering cycle. For example, while the input data to be processed may be considered "indirect state" because it is not directly known to the processing circuitry and must be retrieved from memory before rendering can occur, other inputs of the current rendering cycle will be known to the processing circuitry, and those inputs may be referred to as "direct states." Such direct states may be specified, for example, by the input command that triggers the rendering operation, and / or provided in a register or command buffer before rendering begins. The distinction between direct and indirect states may vary depending on the GPU architecture, but by way of example, such direct states may be information describing how many rendering targets exist, how many samples are per pixel, a pointer to a source table containing pointers to buffers, etc. In one exemplary implementation, this direct state needs to match the direct state in the previous rendering cycle before the current rendering cycle is considered a candidate for skipping rendering operations, and therefore meeting the criteria defined above will involve determining whether the direct state matches the direct state of the previous rendering cycle.

[0048] The aforementioned state information may also include additional state items. For example, the state information within each final-level descriptor may also include an access flag set to indicate that an associated memory region has been accessed, and the state information maintained within a given intermediate-level descriptor may also include an access flag set whenever any final-level descriptor accessed via that intermediate-level descriptor has set its access flag to indicate access to an associated memory region. In some cases, it may be useful to propagate such access flag information back through intermediate-level descriptors.

[0049] To maintain state information, the specific level of the hierarchical arrangement of page tables used can be fixed or configurable. In one exemplary embodiment, the apparatus also includes storage means for maintaining control information referenced by the page table update circuitry to determine in which levels of the hierarchical arrangement the state information is maintained. This thus enables the configurability of the mechanism.

[0050] A specific example will now be described with reference to the accompanying drawings.

[0051] Figure 1 A data processing system, including processing circuitry 10 (which may be, for example, a central processing unit (CPU) or a graphics processing unit (GPU)), is schematically illustrated. This processing circuitry executes program instructions and performs data access (both instruction fetching and access to the data to be manipulated) using virtual addresses VA. These virtual addresses are translated to physical addresses PA via address translation circuitry 20. The physical addresses are used to control access to instructions and data in memory system 15. Memory system 15 may include a hierarchical memory structure, such as multi-level cache memory and main memory or other non-volatile storage devices.

[0052] like Figure 1 As shown, the address translation circuit 20 includes an address translation cache 30, which in one example may include at least a translation lookup buffer (TLB). The address translation cache 30 has multiple entries, each storing address translation data used when translating a virtual address into a corresponding physical address in the memory system. The address translation data is determined by performing a page table traversal operation with respect to page tables 35 stored within the memory system 15. (See reference later.) Figure 3As discussed, a multi-level page table traversal process can be used to obtain complete address translation data by referring to the final-level descriptor. This complete address translation data enables the virtual address to be translated into a physical address, and this complete address translation data can be stored within the address translation cache 30. Taking the address translation cache as an example, the TLB is generally used to store such complete address translation data. However, as will be discussed in more detail later, in an exemplary embodiment, the address translation cache may include another cache structure for storing partial address translation data (also referred to herein as intermediate address translation data) obtained by referring to one or more intermediate-level descriptors.

[0053] like Figure 1 As illustrated, when processing circuit 10 issues a virtual address to address translation circuit 20, control circuit 25 can perform a lookup operation within address translation cache 30 to determine whether a hit is detected in one of the entries in the address translation cache. In one embodiment, the address translation cache has a set-association structure, and certain bits of the virtual address can be used as an index into the address translation cache to identify a set, where entries within that set are audited to determine whether a hit is detected. If a hit is detected, the translation response can be returned directly to processor core 10, including the physical address bits and associated attributes of the hit entry stored in the address translation cache. Based on this information, the core can then generate a physical address to be output to memory system 15 for accessing the required instructions or data to be manipulated. If no hit is detected in the address translation cache, address translation circuit 20 initiates a page table traversal process to access the relevant page table 35 in the memory system, traversing the descriptor sequence until the last-level descriptor is obtained, at which point the complete address translation data can be determined, and the appropriate translation response can then be returned to the core. During this process, one or more entries may be allocated within the address translation cache 30 to store address translation data derived from the accessed descriptor. This may allow subsequent virtual addresses to cause a cache hit, thereby reducing access time.

[0054] Figure 2 This is a schematic diagram illustrating the address translation process. The virtual address 50 can be viewed as including multiple bits 55 identifying the virtual page number and some other bits 60 identifying the page offset. The number of bits forming the virtual page number and the number of bits forming the page offset will depend on the page size. The address translation operation performed by the address translation circuit 20 is... Figure 2 The element 65 shown is schematic and is used to obtain address translation information sufficient to enable the virtual page number bit 55 to be translated into an equivalent bit 70 that identifies the physical address 80 of the physical page number. The page offset bit is not changed, so the page offset bit 75 is determined directly from the page offset bit 60 in the virtual address.

[0055] Figure 3 This is a schematic illustration of a page table traversal operation assuming a single-level address translation mechanism. In this example, it is assumed that the virtual address is 48 bits, and therefore virtual address 100 has a series of 9-bit portions associated with different levels of the page table traversal process, where the 12 least significant bits represent the page offset.

[0056] At the start of the page table traversal process, the base address register is accessed to identify the base address 110 used to identify page table 115. Nine bits 105, associated with level 0 of the page table traversal process, are used to identify the index to page table 115, and thus identify intermediate level descriptor 117. This intermediate level descriptor 117 provides a base address 120 to identify another page table 130, where level 1 virtual address bits 125 are used to identify the index to that table. This identifies intermediate level descriptor 132, which provides another base address 135 to identify page table 145. Level 2 virtual address bits 140 are then used to provide an index to table 145 to identify intermediate level descriptor 147, which in turn provides a base address 150 to identify the final page table 160. Level 3 virtual address bits 155 are then used to provide an index to table 160, thus identifying the final level descriptor 162, also known as a page descriptor or leaf descriptor. Using the information provided by the page descriptor, address translation data for one of the entries stored in TLB 30 can then be generated, enabling the virtual page number 55 to be translated into a physical page number 70, and thus allowing the identification of the desired page in memory. This then allows the kernel 10 to access the specific data item (or instruction) corresponding to the virtual address, thereby issuing the required physical address to the memory system 15.

[0057] It should be noted that in some implementations, the final-level descriptor can be specified at an earlier level during the page table traversal process. For example, descriptor 147 may have a block field that, when set, indicates that the descriptor is a block descriptor, and that the block descriptor is a final-level descriptor rather than an intermediate-level descriptor. Therefore, in this case, the information within descriptor 147 can be used to generate complete address translation data.

[0058] As can be seen from the description above, page tables are organized hierarchically. Intermediate descriptors in level 0 page tables identify page tables at level 1, intermediate descriptors in level 1 page tables identify page tables at level 2, and so on, up to the penultimate level, where intermediate descriptors identify page tables at the final level. The final descriptors in these final-level page tables then identify the associated memory region, such as a page in memory.

[0059] Figure 4AThe information that can be provided within a descriptor is illustrated. Specifically, descriptor 200 may include a validity field 205 for identifying whether the descriptor content is valid, various attribute fields 210, and an address translation data field 230. For last-level descriptors, the address translation data 230 will identify the associated region in memory, such as an associated page in memory. For intermediate-level descriptors, the address translation data will be intermediate address translation data that can be used to identify the associated page table at the next level in the page table hierarchy.

[0060] In one exemplary embodiment, within the final-level descriptor, attribute 210 includes update status information 215, access status indication or flag 220, and one or more other attributes 225, such as access permission, memory type attributes, etc. In one exemplary embodiment, attributes 225 may be provided only in the final-level descriptor, or only a subset of them may be copied in intermediate-level descriptors. Additionally, according to the technology described herein, page table update circuitry 35 (see...) is provided. Figure 1 This allows the page table update circuitry to maintain, when necessary, access status indications within at least a subset of intermediate page tables (e.g., those page tables at one or more intermediate levels within a hierarchical arrangement of page tables) provided by intermediate-level descriptors. Specifically, the page table update circuitry is arranged to ensure that when certain changes are made to the status information in the final-level descriptor, those changes are also reflected in any intermediate-level descriptors arranged to maintain that status information and used when accessing the final-level descriptor.

[0061] Therefore, by way of example only, if the page table update circuitry determines that updating specific state information within the final-level descriptor 162 is appropriate, then if any or both of the intermediate-level descriptors 147, 132 are also configured to retain that state information, the page table update circuitry will determine whether any updates are needed to the corresponding states retained in those intermediate-level descriptors. This process can in principle be replicated all the way to level 0 intermediate-level descriptors, such as intermediate-level descriptor 117, but in some specific implementations, attempting to replicate such state information at such a low level within a hierarchical structure may be considered inappropriate.

[0062] Figure 4BThe form of update status information 215 used in a particular exemplary embodiment is shown. As shown, update status information 215 contains a two-bit field, the first bit being called the Dirty Modified (DBM) bit, and the second bit being called the Enable bit. When both the DBM bit and the Enable bit are at logic 0, it means that the associated memory region pointed to by the last-level descriptor containing this update status information is read-only. Conversely, if the Enable bit is set (i.e., at logic 1 in this exemplary embodiment) and the DBM bit is cleared (i.e., at logic 0 in this exemplary embodiment), it means that the associated memory region is readable and writable, but no tracking is performed regarding whether a write has actually been performed.

[0063] Now consider the case where the DBM bit is set. When the enable bit is 0, it means the associated memory region is read-only and considered to be in a clean state. Specifically, when the update status information has this form, it means the contents of the associated memory region have not yet been written to. However, in contrast to the "00" read-only state of the update status information, the clean state indicates a state in which the memory region is allowed to transition to a read-write state when a suitable request exists, such as a request issued by processing circuitry attempting to write to the associated memory region. In this case, the DBM bit remains set, but the enable bit transitions from the clean state to the set state, indicating that the memory page is now in a dirty state where it is both readable and writable. Therefore, the transition from the clean state to the dirty state indicates that modification of the contents of the associated memory region is now permitted, and it is assumed that the contents of the associated memory region were modified when it was in the dirty state.

[0064] The above description is made with reference to the meaning of the updated state information when it is provided in association with the final-level descriptor. As previously mentioned, according to the technology described herein, the page table update circuitry for managing the updated state information within the final-level descriptor is also capable of maintaining the corresponding state information within an intermediate-level descriptor provided in at least one intermediate level of the page table hierarchy. Of particular interest are clean and dirty states, and specifically, the page table update circuitry is arranged to update the state information of a given intermediate-level descriptor from a clean state to a dirty state, indicating that an update from a clean state to a dirty state has occurred in the state information of any final-level descriptor accessed via that intermediate-level descriptor.

[0065] Therefore, by way of example, consider the intermediate descriptor 147 used to point to page table 147 and thus to access any of the last-level descriptors in page table 160. If any of the last-level descriptors in page table 160 changes its state information from clean to dirty, the corresponding updated state information in page table 160 will be updated to indicate the dirty state.

[0066] This process can be repeated at any desired level within the hierarchical arrangement. Thus, consider the intermediate-level descriptor 132 used to identify page table 145, and therefore if any of the intermediate-level descriptors within page table 145 updates its state information from a clean state to a dirty state, then intermediate-level descriptor 132 also updates its state information from a clean state to a dirty state, assuming it is not yet in a dirty state.

[0067] Consider an access status flag 220 that can be associated with a final-level descriptor. This access status flag can be set to indicate that an associated memory region has been accessed. If needed, this status information can also be maintained within one or more intermediate-level descriptors, and in a manner similar to that described previously with reference to updated status information, the access flag within that intermediate-level descriptor can be set whenever any final-level descriptor accessed via a given intermediate-level descriptor has set its access flag to indicate access to an associated memory region. In some cases, it may be useful to maintain access status information within intermediate-level descriptors in addition to updating status information; however, in other implementations, only updating status information may be copied within intermediate-level descriptors. The following discussion describes in more detail how updated status information can be maintained within intermediate-level descriptors, but it should be understood that similar techniques can also be used to manage the maintenance of access status information within such intermediate-level descriptors.

[0068] Return to Figure 1 The address translation circuit 20 includes the aforementioned page table update circuit 35, which performs updates to the page table contents, including updates to update status information and optional access status information, which are maintained in the final-level descriptor and in intermediate-level descriptors at any level where such information is copied. In one exemplary embodiment, the intermediate levels at which the update status information is copied may be fixed, but in other examples, this may be configurable, for example, by referencing control information 40 stored in the system to identify in which intermediate levels the page table update circuit will maintain the update status information.

[0069] While for the purposes of this description it is assumed that the page table update circuitry 35 is a component provided within the address translation circuitry 20, in alternative embodiments, the page table update circuitry may be provided as a separate component from the address translation circuitry. However, providing the page table update circuitry 35 within the address translation circuitry 20 may be more efficient because the page table update circuitry is typically activated in response to a write operation to a page, and the address translation circuitry 20 receives requests from the processing circuitry 10 regarding write operations that can be used to trigger the activity of the page table update circuitry 35.

[0070] Figure 5This is a flowchart illustrating the status information update process performed according to the techniques described herein. At step 250, it is detected whether a request has been received from the processing circuitry to attempt to update a page whose associated last-level descriptor indicates a clean state. Such a request may be issued, for example, by software executing on the processing circuitry, and when the address translation circuitry 20 initially receives the request from the processing circuitry 10, it typically does not know what update status value is stored in the relevant last-level descriptor. Therefore, a lookup within the address translation cache 30 can be performed, followed by any page table traversal required to obtain the last-level descriptor of the relevant page being accessed. Once the last-level descriptor has been accessed, the update status information can be checked to determine whether the last-level descriptor indicates a clean state.

[0071] It should also be noted that additional checks may be performed at this stage to check whether the received write request is allowed to proceed relative to the identified memory page, and thus, for example, to check whether the processing circuitry in its current execution mode is allowed to access the identified memory address. However, for the purposes of the following discussion, it is assumed that all such additional checks have passed, and that it is determined at step 250 whether the final descriptor of the relevant page indicates a clean state.

[0072] If the final-level descriptor does indeed indicate a clean state, the process proceeds to step 260. Prior to this technique, such updated state information would typically reside only within the final-level descriptor, and the page table update circuitry would be arranged to change the state in that final-level descriptor from clean to dirty. However, as indicated in step 260, in addition to any such updates to the final-level descriptor, the page table update circuitry is also arranged to identify intermediate-level descriptors used to identify the final-level descriptor, and for each of those intermediate-level descriptors arranged to retain state information, the page table update circuitry ensures that the state information is set to indicate a dirty state. For some intermediate-level descriptors, this may involve changing the state from clean to dirty, but it should be understood that for some intermediate-level descriptors, updates may not be necessary because they may already indicate a dirty state, since the intermediate-level descriptor, which has previously been changed from clean to dirty, is also used to access different final-level descriptors.

[0073] Existence is realizable Figure 5 Step 260 can be performed in various ways, and specifically, the relative timing of updating intermediate descriptors can be changed relative to the updates made to the final descriptor.

[0074] Figure 6 This shows the implementation Figure 5 The flowchart for the first option in the final step, which can also be referred to as the top-down approach, shows that at step 300, parameter i is set to 0, and then at step 305, the i-level page table descriptor is identified. From the preceding discussion... Figure 3It is clear from the text that the base address of the i-level page table is used and the result is... Figure 5 The part of the provided virtual address specified in the request received at step 250 is used to perform the identification of the page table descriptor.

[0075] Subsequently, at step 310, it is determined whether the identified descriptor is configured to track update status information. In one exemplary implementation, it is common practice that such tracking will not be provided at level L0, but only at one or more higher levels. Furthermore, it should be understood that when the identified descriptor is a last-level descriptor, it will be configured to track update status information, but for various intermediate levels, this may depend on the predetermined configuration of the page table hierarchy, or on factors such as those specified by the page table hierarchy. Figure 1 The control information 40 shown here specifies the control data.

[0076] If it is determined at step 310 that the identified descriptor is configured to track update status information, then at step 315 it is determined whether the update status information currently indicates a clean state. If so, the update status information is updated at step 320 to indicate a dirty state. Conversely, if the update status information currently does not indicate a clean state, and therefore has been marked as dirty, or is in a non-tracking state, then the state is not changed and step 320 is bypassed. Similarly, if it is determined at step 310 that the identified descriptor is not tracking update status information, then steps 315 and 320 are bypassed.

[0077] At step 325, it is determined whether there are more levels to consider. If so, the parameter i is incremented by 1 at step 330, and the process then returns to step 305.

[0078] Once all levels have been considered, the page table descriptor update process is determined to be complete at step 335. In one exemplary implementation, once all page table descriptors have been updated, the initial request to update pages in memory is allowed to proceed. In some implementations, updates to pages in memory can be initiated at an earlier stage, while ensuring that page table descriptor updates complete before page updates are considered complete to avoid race conditions.

[0079] Figure 7 This shows what can be used to implement Figure 5 The flowchart illustrates an alternative method for the final step, also referred to herein as the bottom-up approach. At step 350, the state in the final-level descriptor is updated from clean to dirty.

[0080] After step 350, and then at step 355, the last-level descriptor is considered the current descriptor. At step 360, the page table update circuit is then arranged to identify the descriptor pointing to the next lowest level of the page table containing the current descriptor. Thus, by way of example, if the last-level descriptor whose state changes from clean to dirty at step 350 is descriptor 162, then step 360 will be used to identify the intermediate-level descriptor 147 pointing to the page table 160 containing the last-level descriptor 162.

[0081] At step 365, it is then determined whether the identified descriptor is configured to track update status information, and if so, at step 370, it is determined whether the update status information within that descriptor currently indicates a clean state. If so, the status is updated to a dirty state at step 375. (This is consistent with the previously discussed...) Figure 6 Similarly, if it is determined at step 370 that the update status information does not currently indicate a clean state (e.g., because it is already in a dirty or untracked state), then step 375 is bypassed. Likewise, if it is determined that the identified descriptor is not configured to track update status information, then steps 370 and 375 are bypassed.

[0082] At step 380, it is determined whether the identified descriptor is in a level 0 page table. If not, the descriptor identified at step 385 is considered the current descriptor, and processing returns to step 360. However, once it is determined at step 380 that the currently identified descriptor is in a level 0 page table, the process proceeds to step 390, which considers the page table descriptor update process complete. In an alternative implementation, if configuration information can be used to indicate the lowest level of tracking dirty / clean status information, it can be referenced at step 380, and once the identified descriptor is at the lowest level, a "yes" path from step 380 can be followed, thereby allowing in such implementations... Figure 7 The process was completed relatively early.

[0083] and Figure 6 Similar to the discussion above, once all page table descriptors have been updated, initial requests to update pages in memory are allowed to proceed. In some implementations, updates to pages in memory can be initiated at an earlier stage, while ensuring that page table descriptor updates complete before page updates are considered finished to avoid race conditions.

[0084] Figure 8 In an exemplary specific implementation, it is shown Figure 1 The address translation cache is in the form of 30. For example... Figure 8As shown, the address translation cache includes a TLB 400 for caching final-level descriptors obtained from page table 35 within memory system 15. Optionally, however, the address translation cache 30 may also include an intermediate descriptor cache 410 for caching intermediate-level descriptors retrieved from page table 35 within memory system 15, also referred to herein as a traversal cache. As previously stated, the use of the address translation cache 30 can accelerate the process of performing virtual address to physical address translation in response to a request from processing circuitry 10. Additionally, references... Figure 9A and Figure 9B As detailed, it can also be used by the page table update circuit 35 when attempting to determine which descriptors require their state information to be updated.

[0085] like Figure 9A As shown, the page table update circuit 35 can cause a lookup to be performed within the address translation cache, specifically within TLB 400, to determine if there is a hit for the identified last-level descriptor (i.e., the last-level descriptor pointing to the memory page that is being accessed by a request from the processing circuitry). If a hit is found, it is determined at step 425 whether the cache copy has state information indicating it is dirty. If so, the process proceeds to step 430, where it is determined that no page table descriptor update is required. Specifically, since the last-level descriptor is already in a dirty state, it can be assumed that any necessary updates to the intermediate-level descriptors have already been performed.

[0086] However, if it is determined at step 425 that the cache copy does not indicate a dirty state, or if a TLB miss is detected at step 420, the process proceeds to step 435. Specifically regarding the "No" path from step 425, it should be noted that if a cache copy of the last-level descriptor is detected, but its state indicates a clean state, this is effectively considered a miss for the purposes of the page table update process, because in addition to the update performed on the last-level descriptor, it is necessary to determine which intermediate-level descriptors might also need to have their state information updated to a dirty state.

[0087] At step 435, it is determined whether a cache traversal exists, and if not, the process proceeds to step 440, where the previously described page table traversal process is used to analyze intermediate-level descriptors and update their state as necessary, as well as update the state of the final-level descriptors. In implementing step 440, the previously referenced... Figure 6 or Figure 7 Any of the methods described herein.

[0088] However, if a traversal cache is determined at step 435, then at step 445, the last-level descriptor is treated as the current descriptor. Then, at step 450, a lookup is performed within the traversal cache to see if a copy of the descriptor pointing to the next lowest level of the page table containing the current descriptor exists. This next lowest-level descriptor is referred to herein as the identified descriptor.

[0089] After step 450, as Figure 9B As shown, at step 455, it is determined whether a hit occurred at step 450, and if a hit occurs, it is determined that the identified descriptor has a state indicating a dirty or untracked state. If so, the process can proceed to step 460, where it is determined that no lower-level descriptors need to be considered. Instead, the page table traversal process can be used to analyze any intermediate-level descriptors between the identified descriptor and the last-level descriptor and update their states if necessary, as well as update the state of the last-level descriptor. As with step 440, the previously described... Figure 6 or Figure 7 The process.

[0090] If the descriptor identified at step 455 does not have a state indicating a dirty or untracked state, then at step 465 it is determined whether the identified descriptor is in a level 0 page table, and if not, the descriptor identified at step 470 is considered the current descriptor, and the process then returns to step 450.

[0091] However, if the identified descriptor is in a level 0 page table, the process proceeds to step 475, whereby the process then proceeds to... Figure 9A Step 440 in the process. Specifically, at this point, a complete page table traversal will be required to analyze the intermediate-level descriptors and update their state as necessary.

[0092] As can be seen from the above description, by using the reference address translation cache, the page table update circuit 35 can reduce the amount of analysis required to determine which intermediate level descriptors need to be updated, and thus reduce the number of levels that need to be traversed during the page table traversal performed to update the relevant descriptors.

[0093] Once the address translation cache contents have been used in this way to attempt to identify which intermediate descriptors, besides the last-level descriptors, need to be updated, in an exemplary implementation, any cached copies of those descriptors whose state information is being updated can be updated or invalidated to ensure that the address translation circuitry does not accidentally refer to outdated descriptor information when performing future address translations, and to ensure that the page table update circuitry 35 does not refer to outdated cached information when attempting to determine any subsequent page table descriptor updates required.

[0094] Furthermore, in some systems, it should be understood that such address translation information may be cached by multiple entities within the system, and in such cases, any suitable consistency technique can be used to ensure that when the page table update circuitry updates the state information of the relevant descriptors that may be stored elsewhere in the system, the cached copies of those descriptors are updated or invalidated.

[0095] By maintaining state information within intermediate-level descriptors, this can be used by processing circuitry to influence certain operations it is performing. A particular exemplary use case is the use of graphics rendering operations, where the processing circuitry can be a GPU and can be arranged to periodically perform graphics rendering operations with respect to blocks of data identified by memory address ranges. Memory address ranges can be relatively large and, specifically, can span a large number of memory pages. Therefore, attempting to perform page table traversal operations to identify each final-level descriptor and, by referring to the state information maintained within the final-level descriptors, determine whether any data within the memory address range is indicated as modified might be considered impractical. However, by maintaining such information in intermediate-level descriptors in the manner described herein, it becomes economically feasible for the graphics processing unit to request the address translation circuitry 20 to attempt to determine this information. Specifically, the address translation circuitry is able to identify a relatively small number of intermediate-level descriptors covering the address range of interest and is able to examine the updated state information maintained in those intermediate-level descriptors. If the update status information in all relevant intermediate descriptors indicates a clean state, it is known that no update was performed, and in some cases, this allows the rendering operation to be canceled and the rendering output from the previous rendering cycle to be used instead.

[0096] Figure 10 This is a flowchart illustrating the processes that can be performed in an exemplary implementation when a new graphics rendering cycle is encountered. At step 500, when a new graphics rendering cycle is encountered, the graphics processing unit determines at step 505 whether the direct state of the new graphics rendering cycle is the same as the direct state of the previous rendering cycle. The direct state is a state that is directly available to the GPU, for example, it may be provided in one or more registers or command buffers before rendering begins. Examples of such a direct state could be information describing how many rendering targets exist, how many samples are in each pixel, etc.

[0097] If the direct state used for the new graphics rendering cycle does not match the direct state used for the previous cycle, it does not matter whether the input data to be processed is different; instead, the process proceeds to step 530, where it is determined that rendering needs to be performed in the current graphics rendering cycle for the range of memory addresses of interest. Therefore, the required data is read from memory, and then the direct state is used to render that data to control the operations performed.

[0098] However, if the immediate state of the new graphics rendering cycle is the same as that of the previous cycle, then if it can be determined that the data to be processed since the previous rendering cycle has not changed, the new graphics rendering cycle is a candidate for not performing rendering.

[0099] Therefore, if a direct state match occurs at step 505, the GPU may request a specified memory address range from the address translation circuit 20. At step 510, the address translation circuit 20 may subsequently identify a set of memory regions that cover the memory address range. It should be noted that while in one exemplary implementation there may only be one input buffer for the graphics rendering cycle, in some implementations there may be multiple input buffers. Typically, a contiguous address range will be associated with each input buffer, and therefore step 510 may be performed for the memory address range associated with each input buffer.

[0100] At step 515, the address translation circuit 20 may then determine intermediate-level descriptors covering the identified set of regions, and specifically may search for the lowest-level intermediate-level descriptor that holds state information and covers the identified set of regions. Then, at step 520, the intermediate-level descriptors may be retrieved and their state information referenced. At step 525, it may then be determined whether any of these intermediate-level descriptors has marked its state information as dirty or untracked. If so, the process proceeds to step 530, where it is determined that rendering is required for the relevant memory address range in the current graphics rendering cycle. However, if, conversely, all relevant intermediate-level descriptors have marked their state information as clean, it is determined at step 535 that rendering is not required for the memory address range of interest in the current graphics rendering cycle. This results in significant performance benefits by eliminating the need to perform intensive rendering tasks. It also results in energy savings. Furthermore, in addition to not performing rendering in this case, there are cases where data does not need to be read from memory, providing further efficiency savings.

[0101] It should be noted that the number of frames processed in each rendering cycle can vary depending on the specific implementation. For example, while each rendering cycle may perform rendering on one frame, modern operating systems allow double or triple buffering of display output, and therefore a rendering cycle can handle two frames in a double-buffered system, three frames in a triple-buffered system, and so on. Furthermore, it is common to use multiple rendering passes (a concept from standardized graphics APIs) within each frame.

[0102] Figure 11This is a block diagram illustrating an exemplary system including multiple CPUs 600, 615, and a GPU 620. These components may be coupled via interconnect 635 to a memory 645 that may contain the previously mentioned page table 650. The aforementioned address translation circuitry 20 may take the form of a memory management unit (MMU) provided at one or more locations within the system. For example, considering CPU 600, this may include processing circuitry 605 having an associated MMU 610 for performing address translation on behalf of the processing circuitry. CPU 615 may also be arranged in a similar manner, but for simplicity, the internal details of CPU 615 are omitted. On the other hand, GPU 620 may utilize a system MMU (SMMU) 625, and the SMMU may again be arranged to incorporate the page table update functionality discussed earlier. In some specific implementations, the GPU may also include its own internal MMU 630, and MMU 630 may be used in conjunction with SMMU 625 to perform address translation on behalf of the GPU. For example, the GPU can use a multi-stage address translation process, each stage comprising multiple levels, and in this case, stage one address translation can be performed by MMU 630 to translate the virtual address into an intermediate physical address, and SMMU 625 can subsequently be used to perform stage two address translation to translate the intermediate physical address into a final physical address within memory 645.

[0103] For example Figure 11 As shown, some of the components may have their own local caches, such as caches 612 and 617 associated with CPUs 600 and 615 respectively, and one or more shared caches 640 may also be provided, for example, within interconnect 635. The interconnect may also include sniffing circuitry, which, in one exemplary embodiment, may be considered as part of the shared cache 640 for maintaining consistency between cache contents within the various caches of the system.

[0104] As mentioned earlier, when updating the state information held in the various intermediate and final descriptors within page table 650, it may be necessary to invalidate or update any cached contents of those related descriptors in the address translation cache unit of any of the MMUs to ensure that outdated descriptor information is not accidentally referenced. This functionality can be implemented using any suitable consistency mechanism.

[0105] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0106] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, features of the dependent claims can be combined with features of the independent claims in various ways without departing from the scope of the invention.

Claims

1. An apparatus for tracking modifications to the contents of a memory region, the apparatus comprising: Address translation circuit, which is used to translate the virtual address specified by the processing circuit into the corresponding physical address of the memory system by referring to the address translation data obtained from the hierarchical arrangement of the page table. The hierarchical arrangement of the page table includes both intermediate-level page tables and final-level page tables. Each last-level page table includes multiple last-level descriptors, and each last-level descriptor identifies the address translation data of the associated memory region; Each intermediate-level page table includes multiple intermediate-level descriptors, and each intermediate-level descriptor identifies intermediate address translation data used to identify the associated page table at the next level in the hierarchical arrangement; Page table update circuitry, which is configured to maintain state information within each final descriptor, updates the state information of a given final descriptor from a clean state to a dirty state to indicate that modification of the contents of the associated memory region is permitted. The page table update circuitry is further arranged to maintain the state information within the intermediate-level descriptors provided in at least a subset of the intermediate-level page tables, such that for a given intermediate-level descriptor in which the state information is maintained, the page table update circuitry is arranged to update the state information of the given intermediate-level descriptor from the clean state to the dirty state, indicating that an update from the clean state to the dirty state has occurred in the state information of any final-level descriptor accessed via the intermediate-level descriptor.

2. The apparatus of claim 1, wherein the hierarchical arrangement of the page tables includes multiple levels of page tables, and the page table update circuitry is arranged therein to maintain the state information therein. The at least subset of the intermediate-level page tables includes the intermediate-level page tables at at least one level of the hierarchical arrangement.

3. The apparatus of claim 2, wherein the at least subset of the intermediate-level page tables includes the intermediate-level page tables within one or more adjacent levels of the hierarchical arrangement.

4. The apparatus according to any one of claims 1 to 3, wherein: The page table update circuit is arranged to maintain the state information within the intermediate level descriptor, such that an indication of the dirty state within the state information of the given intermediate level descriptor allows modification of the contents of the associated page table at the next level in the hierarchical arrangement; The page table update circuit is thus arranged to update the state information of the given final-level descriptor from the clean state to the dirty state, indicating that modification of the contents of the associated memory region is permitted once each intermediate-level descriptor used to identify the state information of the given final-level descriptor identifies the dirty state within the state information.

5. The apparatus according to any one of claims 1 to 3, wherein: The page table update circuitry is configured to perform the following operations in response to updating the state information of the given final-level descriptor from the clean state to the dirty state: indicating that modification of the contents of the associated memory region is permitted; tracing back the levels in the hierarchical arrangement to identify each intermediate-level descriptor used to identify the final-level descriptor; and for each identified intermediate-level descriptor in which state information that does not indicate the dirty state is held, updating the state information to indicate the dirty state.

6. The apparatus according to any one of claims 1 to 3, further comprising: Address translation cache storage device for storing copies of one or more descriptors retrieved from the hierarchical arrangement of the page table; The page table update circuitry is configured to refer to the address translation cache storage device when determining which page table descriptors need to be updated when attempting to update the contents of the memory region associated with the given final-level descriptor.

7. The apparatus of claim 6, wherein when the address translation cache storage device stores a copy of the given last-level descriptor whose state information indicates the dirty state, the page table update circuitry is arranged to determine that it is not necessary to update the page table descriptors in the hierarchical arrangement of the page tables.

8. The apparatus of claim 6, wherein, in the absence of the address translation cache storage means storing a copy of the given final-level descriptor whose state information indicates the dirty state, the page table update circuitry is arranged to determine the need for analysis operations with respect to the intermediate-level descriptors used to identify the given final-level descriptor, in order to determine whether, in addition to updating the state information of the given final-level descriptor from the clean state to the dirty state, it is also necessary to update the state information held for any of those intermediate-level descriptors.

9. The apparatus of claim 6, wherein the address translation cache storage means includes a translation backup buffer for storing copies of one or more final-level descriptors.

10. The apparatus of claim 9, wherein the address translation cache storage means further comprises an intermediate descriptor cache to store copies of intermediate-level descriptors from page tables at one or more intermediate levels in a hierarchical arrangement of the page tables.

11. The apparatus of claim 10, wherein in the absence of the translation backup buffer storing a copy of the given final-level descriptor whose state information indicates the dirty state, the page table update circuitry is arranged to perform a lookup operation in the intermediate descriptor cache to attempt to trace back the level in the hierarchical arrangement until a copy of a non-clean intermediate-level descriptor for identifying the given final-level descriptor is detected, or the lookup operation has been performed for all levels in the intermediate descriptor cache for the intermediate-level descriptors in the hierarchical arrangement, the non-clean intermediate-level descriptor being an intermediate-level descriptor whose state information indicates a non-clean state.

12. The apparatus of claim 11, wherein the non-clean state is one of a dirty state or a non-tracking state.

13. The apparatus of claim 11, wherein when a copy of a non-clean state intermediate level descriptor for identifying the given final level descriptor is detected during the lookup operation, the page table update circuit is subsequently arranged to identify any intermediate level descriptor for identifying the given final level descriptor existing in the level containing the non-clean state intermediate level descriptor and the final level containing the given final level descriptor, and subsequently identify the dirty state within the state information held by any of those identified intermediate level descriptors.

14. The apparatus according to any one of claims 1 to 3, wherein the processing circuitry is arranged to retain the state information within one or more intermediate level descriptors in the intermediate level descriptors when determining a data processing operation to be performed by the processing circuitry.

15. The apparatus according to claim 14, wherein: The processing circuitry is arranged to periodically perform graphics rendering operations with respect to data blocks identified by memory address ranges; The processing circuitry is configured to perform the following operation at least when the defined criteria are met in the current rendering cycle: issue a request to the address translation circuitry to identify the set of memory regions covered by the memory address range; Determine one or more intermediate-level descriptors for identifying the final-level descriptor of the set of memory regions; And referencing the state information stored in one or more of those determined intermediate-level descriptors to determine whether any updates to the data block have occurred since the previous rendering cycle; and If it is determined that no update of the data block has occurred since the previous rendering cycle, the processing circuitry is configured to use the output of the graphics rendering operation in the previous rendering cycle instead of re-executing the graphics rendering operation.

16. The apparatus according to any one of claims 1 to 3, wherein the memory region is a memory page.

17. The apparatus of any one of claims 1 to 3, wherein the status information within each final-level descriptor further includes an access flag set to indicate that the associated memory region has been accessed, and the status information maintained within the given intermediate-level descriptor further includes an access flag set whenever any final-level descriptor accessed via the intermediate-level descriptor has set its access flag to indicate access to the associated memory region.

18. The apparatus of claim 3, further comprising a storage means for maintaining control information referenced by the page table update circuitry to determine in which levels of the hierarchical arrangement the state information is maintained.

19. A method for tracking modifications to the contents of a memory region, the method comprising: An address translation circuit is used to translate the virtual address specified by the processing circuit into the corresponding physical address of the memory system by referring to the address translation data obtained from the hierarchical arrangement of the page table. The hierarchical arrangement of the page table includes both intermediate-level page tables and final-level page tables. Each final-level page table is arranged to include multiple final-level descriptors, each final-level descriptor identifying the address translation data of the associated memory region; Each intermediate-level page table is arranged to include multiple intermediate-level descriptors, each intermediate-level descriptor identifying intermediate address translation data used to identify the associated page table at the next level in the hierarchical arrangement; A page table update circuit is employed to maintain state information within each final-level descriptor. The page table update circuit is arranged to update the state information of a given final-level descriptor from a clean state to a dirty state, indicating that modification of the contents of the associated memory region is permitted. The page table update circuitry is arranged to further maintain the state information within the intermediate-level descriptors provided in at least a subset of the intermediate-level page tables, such that for a given intermediate-level descriptor in which the state information is maintained, the page table update circuitry is arranged to update the state information of the given intermediate-level descriptor from the clean state to the dirty state, indicating that an update from the clean state to the dirty state has occurred in the state information of any final-level descriptor accessed via the intermediate-level descriptor.

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