Shift register unit, gate drive circuit, and display device

Abstract

A shift register unit, a gate driving circuit, and a display device are disclosed, belonging to the field of display technology. They can solve the problem of unstable threshold voltage and easy leakage current in thin-film transistors in existing shift register units. The shift register unit includes: an input sub-circuit (101), an output sub-circuit (102), a pull-down control sub-circuit (103), a pull-down sub-circuit (104), a first noise reduction sub-circuit (105), a first auxiliary control sub-circuit (108), and a second auxiliary control sub-circuit (109). The first auxiliary control sub-circuit (108) is configured to write a third reference level signal into the pull-down control node (PC) when the pull-down node (PD) is a first reference level signal, and control the pull-down sub-circuit (104) to close, so as to control the first noise reduction sub-circuit (105) to turn off. The second auxiliary control sub-circuit (109) is configured to write a first reference level signal into the pull-down control node (PC) when the pull-down node (PD) is a first power supply voltage signal, and control the pull-down sub-circuit (104) to turn off, so as to control the first noise reduction sub-circuit (105) to perform noise reduction on the pull-up node (PU) through the second reference level signal.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register unit, a gate driving circuit, and a display device. Background Technology

[0002] GOA (Gate Driver on Array) technology integrates the gate driver circuit onto the array substrate of the display panel. Compared with the traditional COF (Chip On Film) or COG (Chip On Glass) processes, it not only saves costs but also allows for a symmetrical and aesthetically pleasing design on both sides of the panel. It also eliminates the need for the bonding area of ​​the gate driver circuit and the surrounding wiring space, thereby enabling a narrow bezel design for the display device and improving the production capacity and yield of the display device.

[0003] The thin-film transistors (TFTs) used in GOA circuits can have amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), or metal-oxide semiconductors (MOS), such as the typical material IGZO (Indium Gallium Zinc Oxide). Large-size displays typically use MOS TFTs (such as IGZO TFTs) as the TFTs in the GOA circuit. However, as display size and resolution increase, TFTs with higher mobility are required for the GOA circuit. When using TFTs with higher mobility, the threshold voltage of the TFT becomes unstable, prone to negative bias fluctuations, causing leakage current and affecting the performance of the GOA circuit. This can lead to display defects in the driven display panel. Summary of the Invention

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a shift register unit, a gate drive circuit, and a display device.

[0005] In a first aspect, embodiments of this disclosure provide a shift register unit, the shift register unit comprising: an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a first auxiliary control sub-circuit, and a second auxiliary control sub-circuit;

[0006] The input sub-circuit is configured to pull up the potential of the pull-up node in response to an input signal at the signal input terminal; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously.

[0007] The output sub-circuit is configured to output a signal through the signal output terminal in response to the potential of the pull-up node being pulled high.

[0008] The pull-down control sub-circuit is configured to respond to a first power supply voltage signal and control the potential of the pull-down node using the first power supply voltage signal; the pull-down node is connected to at least the pull-down control sub-circuit, the pull-down sub-circuit, and the first noise reduction sub-circuit simultaneously.

[0009] The pull-down sub-circuit is configured to pull down the potential of the pull-down node via a first reference level signal in response to the potential of the pull-down control node; the pull-down control node is connected to at least the pull-down sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit simultaneously.

[0010] The first noise reduction sub-circuit is configured to reduce the noise of the pull-up node's potential in response to the potential of the pull-down node using a second reference level signal;

[0011] The first auxiliary control sub-circuit is configured to write a third reference level signal into the pull-down control node when the pull-down node is a first reference level signal, and control the pull-down sub-circuit to close, so as to control the first noise reduction sub-circuit to turn off.

[0012] The second auxiliary control sub-circuit is configured to write a first reference level signal into the pull-down control node when the pull-down node is a first power supply voltage signal, and control the pull-down sub-circuit to turn off, so as to control the first noise reduction sub-circuit to perform noise reduction on the pull-up node through the second reference level signal.

[0013] Optionally, the first auxiliary control sub-circuit includes: a first storage capacitor; one end of the first storage capacitor is connected to the pull-down control node, and the other end is connected to the first power supply voltage terminal; the pull-down control node is connected to the input sub-circuit;

[0014] The second auxiliary control sub-circuit includes a ninth transistor and a tenth transistor; the control electrode of the ninth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the tenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

[0015] Optionally, the first auxiliary control sub-circuit includes an eleventh transistor; the control electrode and the first electrode of the eleventh transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-down control node;

[0016] The second auxiliary control sub-circuit includes a twelfth transistor and a thirteenth transistor; the control electrode of the twelfth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the thirteenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

[0017] Optionally, the first auxiliary control sub-circuit includes: a fourteenth transistor; the control electrode and the first electrode of the fourteenth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down control node;

[0018] The second auxiliary control sub-circuit includes a fifteenth transistor and a sixteenth transistor; the control electrode of the fifteenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the sixteenth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

[0019] Optionally, the shift register unit further includes: a second noise reduction sub-circuit;

[0020] The second noise reduction sub-circuit is configured to reduce the noise of the signal output terminal by means of a second reference level signal in response to the potential of the pull-down node.

[0021] Optionally, the second noise reduction sub-circuit includes: a fourth transistor;

[0022] The control electrode of the fourth transistor is connected to the pull-down node, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the signal output terminal.

[0023] Optionally, the shift register unit further includes: a reset sub-circuit;

[0024] The reset sub-circuit is configured to reset the potential of the pull-up node via a second reference level signal in response to a reset signal.

[0025] Optionally, the reset sub-circuit includes: a second transistor;

[0026] The control electrode of the second transistor is connected to the reset signal terminal, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the pull-up node.

[0027] Optionally, the input sub-circuit includes: a first transistor;

[0028] The control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node.

[0029] Optionally, the output sub-circuit includes: a third transistor and a second storage capacitor;

[0030] The control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal.

[0031] One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal.

[0032] Optionally, the pull-down control sub-circuit includes: a fifth transistor;

[0033] The control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node.

[0034] Optionally, the pull-down sub-circuit includes: a sixth transistor and a seventh transistor;

[0035] The control electrode of the sixth transistor is connected to the pull-down control node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down node;

[0036] The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node.

[0037] Optionally, the first noise reduction sub-circuit includes: an eighth transistor;

[0038] The control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node.

[0039] Secondly, embodiments of this disclosure provide a shift register unit, the shift register unit comprising: an input sub-circuit, a reset sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, a first auxiliary control sub-circuit, and a second auxiliary control sub-circuit; a pull-up node is connected to at least simultaneously the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit; a pull-down node is connected to at least simultaneously the pull-down control sub-circuit, the pull-down sub-circuit, and the first noise reduction sub-circuit; and a pull-down control node is connected to at least simultaneously the pull-down sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit.

[0040] The input sub-circuit includes a first transistor; the reset sub-circuit includes a second transistor; the output sub-circuit includes a third transistor and a second storage capacitor; the second noise reduction sub-circuit includes a fourth transistor; the pull-down control sub-circuit includes a fifth transistor; the pull-down circuit includes a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes an eighth transistor; the first auxiliary control sub-circuit includes a first storage capacitor; the second auxiliary control sub-circuit includes a ninth transistor and a tenth transistor.

[0041] The control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously.

[0042] The control electrode of the second transistor is connected to the reset signal terminal, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the pull-up node;

[0043] The control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal.

[0044] One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal;

[0045] The control electrode of the fourth transistor is connected to the pull-down node, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the signal output terminal.

[0046] The control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node;

[0047] The control electrode of the sixth transistor is connected to the pull-down control node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down node;

[0048] The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node.

[0049] The control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node;

[0050] One end of the first storage capacitor is connected to the pull-down control node, and the other end is connected to the first power supply voltage terminal; the pull-down control node is connected to the second terminal of the first transistor;

[0051] The control electrode of the ninth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the tenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

[0052] Thirdly, embodiments of this disclosure provide a shift register unit, the shift register unit comprising: an input sub-circuit, a reset sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, a first auxiliary control sub-circuit, and a second auxiliary control sub-circuit; a pull-up node is connected to at least simultaneously the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit; a pull-down node is connected to at least simultaneously the pull-down control sub-circuit, the pull-down sub-circuit, and the first noise reduction sub-circuit; and a pull-down control node is connected to at least simultaneously the pull-down sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit.

[0053] The input sub-circuit includes a first transistor; the reset sub-circuit includes a second transistor; the output sub-circuit includes a third transistor and a second storage capacitor; the second noise reduction sub-circuit includes a fourth transistor; the pull-down control sub-circuit includes a fifth transistor; the pull-down circuit includes a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes an eighth transistor; the first auxiliary control sub-circuit includes an eleventh transistor; the second auxiliary control sub-circuit includes a twelfth transistor and a thirteenth transistor.

[0054] The control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously.

[0055] The control electrode of the second transistor is connected to the reset signal terminal, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the pull-up node;

[0056] The control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal.

[0057] One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal;

[0058] The control electrode of the fourth transistor is connected to the pull-down node, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the signal output terminal.

[0059] The control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node;

[0060] The control electrode of the sixth transistor is connected to the pull-down control node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down node;

[0061] The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node.

[0062] The control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node;

[0063] The control electrode and the first electrode of the eleventh transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-down control node.

[0064] The control electrode of the twelfth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the thirteenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

[0065] Fourthly, embodiments of this disclosure provide a shift register unit, the shift register unit comprising: an input sub-circuit, a reset sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, a first auxiliary control sub-circuit, and a second auxiliary control sub-circuit; a pull-up node is connected to at least simultaneously the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit; a pull-down node is connected to at least simultaneously the pull-down control sub-circuit, the pull-down sub-circuit, and the first noise reduction sub-circuit; and a pull-down control node is connected to at least simultaneously the pull-down sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit.

[0066] The input sub-circuit includes a first transistor; the reset sub-circuit includes a second transistor; the output sub-circuit includes a third transistor and a second storage capacitor; the second noise reduction sub-circuit includes a fourth transistor; the pull-down control sub-circuit includes a fifth transistor; the pull-down sub-circuit includes a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes an eighth transistor; the first auxiliary control sub-circuit includes a fourteenth transistor; the second auxiliary control sub-circuit includes a fifteenth transistor and a sixteenth transistor.

[0067] The control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously.

[0068] The control electrode of the second transistor is connected to the reset signal terminal, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the pull-up node;

[0069] The control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal.

[0070] One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal;

[0071] The control electrode of the fourth transistor is connected to the pull-down node, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the signal output terminal.

[0072] The control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node;

[0073] The control electrode of the sixth transistor is connected to the pull-down control node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down node;

[0074] The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node.

[0075] The control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node;

[0076] The control electrode and the first electrode of the fourteenth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down control node;

[0077] The control electrode of the fifteenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the sixteenth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

[0078] Fifthly, embodiments of this disclosure provide a gate driving circuit, the gate driving circuit including a plurality of cascaded shift register units as described above.

[0079] Optionally, the signal input terminal of this shift register unit is connected to the signal output terminal of the previous shift register unit;

[0080] The reset signal terminal of this level shift register unit is connected to the signal output terminal of the next level shift register unit;

[0081] The auxiliary control terminal of this level shift register unit is connected to the signal output terminal of the next level shift register unit.

[0082] In a sixth aspect, embodiments of this disclosure provide a display device, the display device including the gate driving circuit as described above.

[0083] In a seventh aspect, embodiments of this disclosure provide a method for driving a shift register unit, used to drive the shift register unit as described above, the method comprising:

[0084] When the pull-down node is the first reference level signal, the third reference level signal is written into the pull-down control node using the first auxiliary control sub-circuit, and the pull-down sub-circuit is closed to control the first noise reduction sub-circuit to turn off.

[0085] When the pull-down node is the first power supply voltage signal, the second auxiliary control sub-circuit is used to write the first reference level signal into the pull-down control node and control the pull-down sub-circuit to turn off, so as to control the first noise reduction sub-circuit to reduce noise on the pull-up node through the second reference level signal. Attached Figure Description

[0086] Figure 1 This is a schematic diagram of the circuit structure of an exemplary shift register unit;

[0087] Figure 2 A schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this disclosure;

[0088] Figure 3 A schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0089] Figure 4 A schematic diagram of the circuit structure of another shift register unit provided in this disclosure embodiment;

[0090] Figure 5 This is a schematic diagram of the gate drive circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0091] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0092] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0093] The transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors are symmetrical, there is no difference in their functions. In the embodiments of this disclosure, to distinguish the source and drain of the transistor, one of them is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use N-type transistors for illustration. When using an N-type transistor, the first terminal is the drain, the second terminal is the source, and when the gate input is high, the source and drain are conducting. The opposite is true for P-type transistors. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is also within the protection scope of the embodiments of this invention.

[0094] It should be noted that in this embodiment, the third reference level signal refers to a high-level signal, while the first reference level signal and the second reference level signal both refer to low-level signals. Correspondingly, the first power supply voltage terminal refers to the signal terminal VDD; the first reference level terminal refers to the first low-level terminal LVGL, and the first reference level signal refers to the first low-level signal; the second reference level terminal refers to the second low-level terminal VGL, and the second reference level signal refers to the second low-level signal, wherein the voltage of the first low-level signal is lower than the voltage of the second low-level signal.

[0095] Figure 1 This is a schematic diagram of the circuit structure of an exemplary shift register unit, such as... Figure 1As shown, the shift register unit includes an input sub-circuit 101, an output sub-circuit 102, a pull-down control sub-circuit 103, a pull-down sub-circuit 104, a first noise reduction sub-circuit 105, a second noise reduction sub-circuit 106, and a reset sub-circuit 107. Specifically, the input sub-circuit 101 includes a first transistor M1; the output sub-circuit 102 includes a third transistor M3 and a second storage capacitor C2; the pull-down control sub-circuit 103 includes a transistor M5; the pull-down sub-circuit 104 includes a sixth transistor M6 and a seventh transistor M7; the first noise reduction sub-circuit 105 includes an eighth transistor M8; the second noise reduction sub-circuit 106 includes a fourth transistor M4; and the reset sub-circuit 107 includes a second transistor M2.

[0096] Specifically, the gate and source of the first transistor M1 are connected to the signal input terminal Input, and its drain is connected to the pull-up node PU. The gate of the third transistor M3 is connected to the pull-up node PU, its source is connected to the clock signal terminal CLK, and its gate is connected to the signal output terminal Output. One end of the second storage capacitor C2 is connected to the pull-up node PU, and the other end is connected to the signal output terminal Output. The gate and source of the fifth transistor M5 are connected to the first power supply voltage terminal VDD, and its drain is connected to the pull-down node PD. The gate of the sixth transistor M6 is connected to the pull-up node PU, its source is connected to the first reference level terminal LVGL, and its drain is connected to the pull-down node PD. The gate of the seventh transistor M7 is connected to the signal input terminal Input, its source is connected to the first low-level terminal LVGL, and its drain is connected to the pull-down node PD. The gate of the eighth transistor M8 is connected to the pull-down node PD, its source is connected to the first low-level terminal LVGL, and its drain is connected to the pull-up node PU. The gate of the fourth transistor M4 is connected to the pull-down node PD, its source is connected to the second reference level terminal VGL, and its drain is connected to the signal output terminal Output. The gate of the second transistor M2 is connected to the reset signal terminal Reset, the source is connected to the first reference level terminal LVGL, and the drain is connected to the pull-up node PU.

[0097] for Figure 1 The shift register unit shown can be configured to perform the following steps in its operation:

[0098] Pre-charge stage: When a high-level signal is input to the signal input terminal Input, the first transistor M1 is turned on. At this time, the high-level signal input to the signal input terminal Input pulls up the potential of the pull-up node PU and stores it through the second storage capacitor C2.

[0099] Output Stage: A low-level signal is input to the Input terminal, turning off the first transistor M1. During this time, the second storage capacitor C2 is charged during the pre-charge stage, further pulling up the potential of the pull-up node PU. Since the gate of the third transistor M3 is connected to the pull-up node PU, the third transistor M3 is turned on, and the Output terminal outputs the clock signal from the clock signal terminal CLK. At this time, the clock signal is high, and the output signal is also high.

[0100] Reset Phase: A low-level signal is input to the Input terminal, turning off the first transistor M1. At this time, a high-level signal is input to the Reset terminal, turning on the second transistor M2. The first low-level signal is written to the first low-level terminal LVGL of the pull-up node PU, resetting the potential of the pull-up node PU.

[0101] Noise Reduction Stage: When a low-level signal is input to the Input terminal, the first transistor M1 is turned off. When a low-level signal is input to the Reset terminal, the second transistor M2 is turned off. At this time, the potential of the pull-up node PU remains at the reset stage potential, which is the second low-level potential. Meanwhile, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the pull-down node PD remain in the working state of the reset stage, and the pull-up node PU and the signal output terminal Output are continuously subjected to noise reduction.

[0102] In large-size and high-resolution displays, when oxide thin-film transistors (TFTs) with higher mobility are used, the Vth (threshold voltage) of the TFTs becomes unstable, and the Vg of the eighth transistor M8 is prone to negative bias fluctuations. When the eighth transistor M8 experiences negative bias fluctuations, it causes leakage current through the pull-up node PU via the eighth transistor M8, affecting the operating performance of the shift register unit circuit and making the driven display panel prone to display defects.

[0103] To at least solve one of the aforementioned technical problems, this disclosure provides a shift register unit, a gate driving circuit, and a display device. The shift register unit, gate driving circuit, and display device provided in this disclosure will be described in further detail below.

[0104] This disclosure provides a shift register unit. Figure 2 A circuit structure diagram of a shift register unit provided in an embodiment of this disclosure is shown below. Figure 2As shown, the shift register unit provided in this embodiment includes: an input sub-circuit 101, an output sub-circuit 102, a pull-down control sub-circuit 103, a pull-down sub-circuit 104, a first noise reduction sub-circuit 105, a first auxiliary control sub-circuit 108, and a second auxiliary control sub-circuit 109; the input sub-circuit 101 is configured to pull up the potential of the pull-up node PU in response to an input signal at the signal input terminal Input; the pull-up node PU is connected to at least the input sub-circuit 101, the output sub-circuit 102, and the first noise reduction sub-circuit 105 simultaneously; the output sub-circuit 102 is configured to output a signal through the signal output terminal Output in response to the potential of the pull-up node PU after it is pulled up; the pull-down control sub-circuit 103 is configured to control the potential of the pull-down node PD in response to a first power supply voltage signal; the pull-down node PD is connected to at least the pull-down control sub-circuit 103, the pull-down sub-circuit 104, and the first noise reduction sub-circuit 105 simultaneously; The pull-down sub-circuit 104 is configured to pull down the potential of the pull-down node PD by a first low-level signal in response to the potential of the pull-down control node PC. The pull-down control node PC is connected to at least the pull-down sub-circuit 104, the first auxiliary control sub-circuit 108, and the second auxiliary control sub-circuit 109 simultaneously. The first noise reduction sub-circuit 105 is configured to reduce the potential of the pull-up node PU by a second low-level signal in response to the potential of the pull-down node PD. The first auxiliary control sub-circuit 108 is configured to write a high-level signal to the pull-down control node PC when the pull-down node PD is at the first low-level signal, and control the pull-down sub-circuit 104 to close, thereby controlling the first noise reduction sub-circuit 105 to turn off. The second auxiliary control sub-circuit 109 is configured to write a first low-level signal to the pull-down control node PC when the pull-down node PD is at the first power supply voltage signal, and control the pull-down sub-circuit 104 to turn off, thereby controlling the first noise reduction sub-circuit 105 to reduce the noise of the pull-up node PU by the second low-level signal.

[0105] In the shift register unit provided in this embodiment, since a first auxiliary control sub-circuit 108 is added to the shift register unit, when the pull-up node PU is a high-level signal, the pull-down node PD is a first low-level signal, and the pull-down control node PC is a high-level signal, the pull-down sub-circuit 104 is continuously closed, so that the potential of the pull-down node PD is continuously pulled down by the first low-level signal, thereby ensuring that the first noise reduction sub-circuit 105 is fully turned off. Furthermore, the voltage of the first low-level signal and the second low-level signal can be used to control the first noise reduction sub-circuit 105 to be fully turned off, thereby avoiding the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, that is, avoiding leakage current in the pull-up node PU. Meanwhile, a second auxiliary control sub-circuit 109 is added to the shift register unit. When the pull-up node PU is a low-level signal, the pull-down node PD is a first power supply voltage signal (i.e., the pull-down node PD is a high-level signal, and the pull-down control node PC is a first low-level signal). At this time, the pull-down sub-circuit 104 remains off, allowing the pull-down node PD to be continuously written with the first power supply voltage signal. This ensures that the first noise reduction sub-circuit 105 is fully closed, thereby ensuring that the first noise reduction sub-circuit 105 continuously reduces noise at the pull-up node PU through the second low-level signal. It can be seen that, regardless of whether the first noise reduction sub-circuit 105 is off or closed, the potential of the pull-up node PU in the shift register unit provided in this embodiment can reach a preset potential, avoiding the influence of the first noise reduction sub-circuit 105 on the potential of the pull-up node PU. This ensures the stability of the output signal at the output terminal, thereby ensuring a good display effect on the driven display panel.

[0106] In some embodiments, such as Figure 2 As shown, the first auxiliary control sub-circuit 108 includes: a first storage capacitor C1; one end of the first storage capacitor C1 is connected to the pull-down control node PC, and the other end is connected to the first power supply voltage terminal VDD; the pull-down control node PC is connected to the input sub-circuit 101; the second auxiliary control sub-circuit 109 includes: a ninth transistor 109 and a tenth transistor M10; the gate of the ninth transistor M9 is connected to the auxiliary control terminal PA, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC; the gate of the tenth transistor M10 is connected to the pull-down node PD, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC.

[0107] When the first storage capacitor C1 and the pull-up node PU are simultaneously charged with a high-level signal, the high-level signal stored in the first storage capacitor C1 can pull up the potential of the pull-down control node PC to control the pull-down sub-circuit 104 to remain closed, so that the potential of the pull-down node PD is continuously pulled down by the first low-level signal, thereby ensuring that the first noise reduction sub-circuit 105 is fully turned off, and thus avoiding the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, that is, avoiding leakage of the pull-up node PU. When the auxiliary control node PA writes a high-level signal, the ninth transistor M9 turns on, the pull-up node PU is discharged to the second low-level potential, and the first storage capacitor C1 is discharged to the first low-level potential, making the pull-down control node PC the first low-level potential. The pull-down sub-circuit 104 turns off, and the pull-down node PD writes the first power supply voltage signal, i.e., the pull-down node PD is high-level. The tenth transistor M10 remains on, the pull-down sub-circuit 104 remains off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 remains closed, thereby continuously reducing noise for the pull-up node PU. It can be seen that, in the shift register unit provided in this embodiment, regardless of whether the first noise reduction sub-circuit 105 is turned off or closed, the potential of the pull-up node PU can reach the preset potential, avoiding the influence of the first noise reduction sub-circuit 105 on the potential of the pull-up node PU, thereby ensuring the stability of the output signal at the signal output terminal Output, and thus ensuring a good display effect of the driven display panel.

[0108] In some embodiments, Figure 3 A schematic diagram of the circuit structure of another shift register unit provided in this disclosure embodiment is shown below. Figure 3 As shown, the first auxiliary control sub-circuit 108 includes an eleventh transistor M11; the gate and source of the eleventh transistor M11 are both connected to the signal input terminal Input, and the drain is connected to the pull-down control node PC; the second auxiliary control sub-circuit 109 includes a twelfth transistor M12 and a thirteenth transistor M13; the gate of the twelfth transistor M12 is connected to the auxiliary control terminal PA, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC; the gate of the thirteenth transistor M13 is connected to the pull-down node PD, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC.

[0109] When both the pull-down control node PC and the pull-up node PU are simultaneously charged with a high-level signal, the pull-down sub-circuit 104 remains closed, causing the potential of the pull-down node PD to be continuously pulled low by the first low-level signal. This ensures that the first noise reduction sub-circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, i.e., preventing leakage of the pull-up node PU. When the auxiliary control node PA is written with a high-level signal, the twelfth transistor M12 turns on, the pull-down control node PC is pulled down to the first low level, the pull-down sub-circuit 104 is turned off, and the pull-down node PD is at the first low level. The thirteenth transistor M13 turns on, the pull-down node PD is continuously written with the first low-level signal, the pull-down sub-circuit 104 remains off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 remains closed, thereby continuously reducing noise for the pull-up node PU. As can be seen, in the shift register unit provided in this embodiment, regardless of whether the first noise reduction sub-circuit 105 is turned off or closed, the potential of the pull-up node PU can reach the preset potential, thus avoiding the influence of the first noise reduction sub-circuit 105 on the potential of the pull-up node PU, thereby ensuring the stability of the output signal of the signal output terminal Output, and thus ensuring the good display effect of the driven display panel.

[0110] In some embodiments, Figure 4 A schematic diagram of the circuit structure of another shift register unit provided in this disclosure embodiment is shown below. Figure 4 As shown, the first auxiliary control sub-circuit 108 includes: a fourteenth transistor M14; the gate and source of the fourteenth transistor M14 are connected to the first power supply voltage terminal VDD, and the drain is connected to the pull-down control node PC; the second auxiliary control sub-circuit 109 includes: a fifteenth transistor M14 and a sixteenth transistor M15; the gate of the fifteenth transistor M15 is connected to the pull-down node PD, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC; the gate of the sixteenth transistor M16 is connected to the auxiliary control terminal PA, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC.

[0111] When the pull-down control node PC and pull-down node PD are simultaneously written with the first power supply voltage signal, the pull-down sub-circuit 104 remains closed, causing the potential of pull-down node PD to be continuously pulled low by the first low-level signal. This ensures that the first noise reduction sub-circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, i.e., preventing leakage of the pull-up node PU. When the auxiliary control node PA is written with a high-level signal, the sixteenth transistor M16 turns on, the pull-down control node PC is pulled down to the first low level, the pull-down sub-circuit 104 is turned off, and the pull-down node PD is at the first low level. The fifteenth transistor M15 turns on, the pull-down node PD is continuously written with the first low-level signal, the pull-down sub-circuit 104 remains off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 remains closed, thereby continuously reducing noise for the pull-up node PU. As can be seen, in the shift register unit provided in this embodiment, regardless of whether the first noise reduction sub-circuit 105 is turned off or closed, the potential of the pull-up node PU can reach the preset potential, thus avoiding the influence of the first noise reduction sub-circuit 105 on the potential of the pull-up node PU, thereby ensuring the stability of the output signal of the signal output terminal Output, and thus ensuring the good display effect of the driven display panel.

[0112] In some embodiments, such as Figure 2 , Figure 3 ,and Figure 4 As shown, the shift register unit further includes a second noise reduction sub-circuit 106; the second noise reduction sub-circuit 106 is configured to reduce the noise of the signal output terminal Output by means of a second low-level signal in response to the potential of the pull-down node PD.

[0113] Specifically, the second noise reduction sub-circuit 106 includes: a fourth transistor M4; the gate of the fourth transistor M4 is connected to the pull-down node PD, the source is connected to the second low-level terminal VGL, and the drain is connected to the signal output terminal Output.

[0114] During the noise reduction stage, the pull-down node PD is at a high level, and the fourth transistor M4 is turned on. At this time, noise reduction can be performed on the signal output terminal Output through the second low-level signal.

[0115] In some embodiments, such as Figure 2 , Figure 3 and Figure 4 As shown, the shift register unit also includes a reset sub-circuit 107; the reset sub-circuit 107 is configured to reset the potential of the pull-up node PU by a second low-level signal in response to a reset signal.

[0116] Specifically, the reset sub-circuit 107 includes: a second transistor M2; the gate of the second transistor M2 is connected to the reset signal terminal Reset, the source is connected to the second low-level terminal VGL, and the drain is connected to the pull-up node PU.

[0117] At the reset terminal, a high-level signal is input to the Reset signal terminal, and the second transistor M2 is turned on. At this time, the pull-up node PU can be reset by the second low-level signal.

[0118] It should be noted that, within the same register, both the second noise reduction sub-circuit 106 and the reset sub-circuit 107 can be configured simultaneously, or only one of the second noise reduction sub-circuit 106 and the reset circuit 107 can be configured, for example... Figure 2 and Figure 4 The circuit shown includes a second noise reduction sub-circuit 106 and a reset sub-circuit 107. Figure 3 The circuit shown only includes the second noise reduction sub-circuit 106.

[0119] In some embodiments, such as Figure 2 , Figure 3 and Figure 4 As shown, the input sub-circuit 101 includes: a first transistor M1; the gate and source of the first transistor M1 are connected to the signal input terminal Input, and the drain is connected to the pull-up node PU.

[0120] During the input phase, a high-level signal is written to the input terminal, and the first transistor M1 is turned on. The pull-up node can be pre-charged by the high-level signal written to the input terminal.

[0121] In some embodiments, such as Figure 2 , Figure 3 and Figure 4 As shown, the output sub-circuit 102 includes: a third transistor M3 and a second storage capacitor C2; the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the signal output terminal Output; one end of the second storage capacitor C2 is connected to the pull-up node PU, and the other end is connected to the signal output terminal Output.

[0122] During the output phase, the potential of the pull-up node PU is high, the third transistor M3 is turned on, and the clock signal of the clock signal terminal CLK is output to the output signal terminal Output. The clock signal of the clock signal terminal CLK is high, and at this time the potential of the signal output terminal Output is pulled high, that is, a high-level signal is output.

[0123] In some embodiments, such as Figure 2 , Figure 3 and Figure 4As shown, the pull-down control sub-circuit 103 includes: a fifth transistor M5; the gate and source of the fifth transistor M5 are connected to the first power supply voltage terminal VDD, and the drain is connected to the pull-down node PD.

[0124] The gate and source of the fifth transistor M5 are connected to the first power supply voltage terminal VDD, which means that the first power supply voltage signal is written to it. At this time, the fifth transistor M5 is turned on, and the potential of the pull-down node PD is the potential of the first power supply voltage, that is, the potential of the pull-down node PD is high.

[0125] In some embodiments, such as Figure 2 and Figure 4 As shown, the pull-down sub-circuit includes: a sixth transistor M6 and a seventh transistor M7; the gate of the sixth transistor M6 is connected to the pull-down control node PC, the source is connected to the first reference level terminal LVGL, and the drain is connected to the pull-down node PD; the gate of the seventh transistor M7 is connected to the signal input terminal Input, the source is connected to the first power supply voltage terminal VDD, and the drain is connected to the pull-down node PD.

[0126] When a high-level signal is written to the input terminal, the seventh transistor M7 turns on, and the pull-down node PD is written with the first low-level signal. At the same time, when a high-level signal is written to the auxiliary control terminal, the sixth transistor M6 turns on, and the pull-down node can be continuously written with the first level signal, ensuring that the potential of the pull-down node PD is continuously pulled low.

[0127] In some embodiments, such as Figure 2 , Figure 3 and Figure 4 As shown, the first noise reduction sub-circuit 105 includes: an eighth transistor M8; the gate of the eighth transistor M8 is connected to the pull-down node PD, the source is connected to the second low-level terminal VGL, and the drain is connected to the pull-up node PU.

[0128] During the noise reduction stage, the pull-down node PD is at a high level, and the eighth transistor M8 is turned on. At this time, noise reduction can be performed on the pull-down node PU through the second low-level signal.

[0129] This disclosure also provides a gate driving circuit. Figure 5 This is a schematic diagram of the gate drive circuit provided in an embodiment of the present disclosure, as shown below. Figure 5 As shown, the gate drive circuit includes multiple cascaded shift register units as provided in any of the above embodiments; wherein, the signal input terminal Input of the current shift register unit is connected to the signal output terminal Output of the previous shift register unit; the reset signal terminal Reset of the current shift register unit is connected to the signal output terminal Output of the next shift register unit; and the auxiliary control terminal PA of the current shift register unit is connected to the signal output terminal Output of the next shift register unit.

[0130] The gate driving circuit provided in this embodiment can output scanning signals step by step to drive the display panel to perform line-by-line scanning to achieve the display function. Since a first auxiliary control sub-circuit 108 is added to the shift register unit, when the pull-up node PU is a high-level signal, the pull-down node PD is a first low-level signal, and the pull-down control node PC is a high-level signal, the pull-down sub-circuit 104 remains closed, causing the potential of the pull-down node PD to be continuously pulled low by the first low-level signal. This ensures that the first noise reduction sub-circuit 105 is fully turned off. Furthermore, the voltage of the first low-level signal and the second low-level signal can be used to control the first noise reduction sub-circuit 105 to be fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, i.e., preventing leakage current in the pull-up node PU. Meanwhile, a second auxiliary control sub-circuit 109 is added to the shift register unit. When the pull-up node PU is a low-level signal, the pull-down node PD is a first power supply voltage signal (i.e., the pull-down node PD is a high-level signal, and the pull-down control node PC is a first low-level signal). At this time, the pull-down sub-circuit 104 remains off, allowing the pull-down node PD to be continuously written with the first power supply voltage signal. This ensures that the first noise reduction sub-circuit 105 is fully closed, thereby ensuring that the first noise reduction sub-circuit 105 continuously reduces noise at the pull-up node PU through the second low-level signal. It can be seen that, regardless of whether the first noise reduction sub-circuit 105 is off or closed, the potential of the pull-up node PU in the shift register unit provided in this embodiment can reach a preset potential, avoiding the influence of the first noise reduction sub-circuit 105 on the potential of the pull-up node PU. This ensures the stability of the output signal at the output terminal, thereby ensuring a good display effect on the driven display panel.

[0131] This disclosure also provides a display device, which includes the gate driving circuit provided in any of the above embodiments. The display device can be a large-size television, monitor, vehicle navigation system, or other display device. Its implementation principle and technical effect are the same as those of the gate driving circuit provided in any of the above embodiments, and will not be repeated here.

[0132] This disclosure also provides a method for driving a shift register unit, driving the shift register unit as provided in any of the above embodiments. The method for driving the shift register unit includes:

[0133] When the pull-down node is the first reference level signal, the third reference level signal is written into the pull-down control node using the first auxiliary control sub-circuit, and the pull-down sub-circuit is closed to control the first noise reduction sub-circuit to turn off.

[0134] When the pull-down node is the first power supply voltage signal, the second auxiliary control sub-circuit is used to write the first reference level signal into the pull-down control node and control the pull-down sub-circuit to turn off, so as to control the first noise reduction sub-circuit to reduce noise on the pull-up node through the second reference level signal.

[0135] The following will combine Figure 2 , Figure 3 and Figure 4 The specific shift register unit shown will be used to illustrate the driving method of the shift register unit provided in this embodiment.

[0136] Figure 2 In the shift register shown, when the first storage capacitor C1 and the pull-up node PU are simultaneously charged with a high-level signal, the high-level signal stored in the first storage capacitor C1 can pull up the potential of the pull-down control node PC to control the pull-down sub-circuit 104 to remain closed, so that the potential of the pull-down node PD is continuously pulled down by the first low-level signal, thereby ensuring that the first noise reduction sub-circuit 105 is fully turned off, and thus avoiding the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, that is, avoiding leakage of the pull-up node PU. When the auxiliary control node PA writes a high-level signal, the ninth transistor M9 turns on, the pull-up node PU is discharged to the second low-level potential, the first storage capacitor C1 is discharged to the first low-level potential, making the pull-down control node PC the first low-level potential, the pull-down sub-circuit 104 turns off, the pull-down node PD writes the first power supply voltage signal, that is, the pull-down node PD is high-level, the tenth transistor M10 remains on, the pull-down sub-circuit 104 remains off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 remains closed, thereby continuously reducing noise for the pull-up node PU.

[0137] Figure 3 In the shift register shown, when both the pull-down control node PC and the pull-up node PU are simultaneously charged with a high-level signal, the pull-down sub-circuit 104 remains closed, causing the potential of the pull-down node PD to be continuously pulled low by the first low-level signal. This ensures that the first noise reduction sub-circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, i.e., preventing leakage of the pull-up node PU. When the auxiliary control node PA is written with a high-level signal, the twelfth transistor M12 turns on, the pull-down control node PC is pulled down to the first low level, the pull-down sub-circuit 104 is turned off, and the pull-down node PD is at the first low level. The thirteenth transistor M13 turns on, the pull-down node PD is continuously written with the first low-level signal, the pull-down sub-circuit 104 remains off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 remains closed, thereby continuously reducing noise for the pull-up node PU.

[0138] Figure 4In the shift register shown, when the pull-down control node PC and pull-down node PD are simultaneously written with the first power supply voltage signal, the pull-down sub-circuit 104 remains closed, causing the potential of pull-down node PD to be continuously pulled low by the first low-level signal. This ensures that the first noise reduction sub-circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, i.e., preventing leakage of the pull-up node PU. When the auxiliary control node PA is written with a high-level signal, the sixteenth transistor M16 turns on, the pull-down control node PC is pulled down to the first low level, the pull-down sub-circuit 104 is turned off, and the pull-down node PD is at the first low level. The fifteenth transistor M15 turns on, the pull-down node PD is continuously written with the first low-level signal, the pull-down sub-circuit 104 remains off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 remains closed, thereby continuously reducing noise for the pull-up node PU.

[0139] As can be seen, the driving method of the shift register unit provided in this embodiment can make the potential of the pull-up node PU reach the preset potential regardless of whether the first noise reduction sub-circuit 105 is turned off or closed, thus avoiding the influence of the first noise reduction sub-circuit 105 on the potential of the pull-up node PU, thereby ensuring the stability of the output signal of the signal output terminal Output, and thus ensuring the good display effect of the driven display panel.

[0140] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register unit, wherein, The shift register unit includes: an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a first auxiliary control sub-circuit, and a second auxiliary control sub-circuit; The input sub-circuit is configured to pull up the potential of the pull-up node in response to an input signal at the signal input terminal; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously. The output sub-circuit is configured to output a signal through the signal output terminal in response to the potential of the pull-up node being pulled high. The pull-down control sub-circuit is configured to respond to a first power supply voltage signal and control the potential of the pull-down node using the first power supply voltage signal; the pull-down node is connected to at least the pull-down control sub-circuit, the pull-down sub-circuit, and the first noise reduction sub-circuit simultaneously. The pull-down sub-circuit is configured to pull down the potential of the pull-down node via a first reference level signal in response to the potential of the pull-down control node; the pull-down control node is connected to at least the pull-down sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit simultaneously. The first noise reduction sub-circuit is configured to reduce the noise of the pull-up node's potential in response to the potential of the pull-down node using a second reference level signal; The first auxiliary control sub-circuit is configured to write a third reference level signal into the pull-down control node when the pull-down node is a first reference level signal, and control the pull-down sub-circuit to close, so as to control the first noise reduction sub-circuit to turn off. The second auxiliary control sub-circuit is configured to, in response to the control signal of the auxiliary control terminal, write a first reference level signal into the pull-down control node when the pull-down node is a first power supply voltage signal, and control the pull-down sub-circuit to turn off, so as to control the first noise reduction sub-circuit to perform noise reduction on the pull-up node through the second reference level signal; The first auxiliary control sub-circuit includes: a first storage capacitor; one end of the first storage capacitor is connected to the pull-down control node, and the other end is connected to the first power supply voltage terminal; the pull-down control node is connected to the input sub-circuit; The second auxiliary control sub-circuit includes a ninth transistor and a tenth transistor; the control electrode of the ninth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the tenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node. Alternatively, the first auxiliary control sub-circuit includes: an eleventh transistor; the control electrode and the first electrode of the eleventh transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-down control node; The second auxiliary control sub-circuit includes a twelfth transistor and a thirteenth transistor; the control electrode of the twelfth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the thirteenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node. Alternatively, the first auxiliary control sub-circuit includes: a fourteenth transistor; the control electrode and the first electrode of the fourteenth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down control node; The second auxiliary control sub-circuit includes a fifteenth transistor and a sixteenth transistor; the control electrode of the fifteenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the sixteenth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

2. The shift register unit according to claim 1, wherein, The shift register unit further includes: a second noise reduction sub-circuit; The second noise reduction sub-circuit is configured to reduce the noise of the signal output terminal by means of a second reference level signal in response to the potential of the pull-down node.

3. The shift register unit according to claim 2, wherein, The second noise reduction sub-circuit includes: a fourth transistor; The control electrode of the fourth transistor is connected to the pull-down node, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the signal output terminal.

4. The shift register unit according to claim 1, wherein, The shift register unit further includes: a reset sub-circuit; The reset sub-circuit is configured to reset the potential of the pull-up node via a second reference level signal in response to a reset signal.

5. The shift register unit according to claim 4, wherein, The reset sub-circuit includes: a second transistor; The control electrode of the second transistor is connected to the reset signal terminal, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the pull-up node.

6. The shift register unit according to claim 1, wherein, The input sub-circuit includes: a first transistor; The control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node.

7. The shift register unit according to claim 1, wherein, The output sub-circuit includes: a third transistor and a second storage capacitor; The control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal. One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal.

8. The shift register unit according to claim 1, wherein, The pull-down control sub-circuit includes: a fifth transistor; The control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node.

9. The shift register unit according to claim 1, wherein, The pull-down sub-circuit includes: a sixth transistor and a seventh transistor; The control electrode of the sixth transistor is connected to the pull-down control node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down node; The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node.

10. The shift register unit according to claim 9, wherein, The first noise reduction sub-circuit includes: an eighth transistor; The control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node.

11. A shift register unit, wherein, The shift register unit includes: an input sub-circuit, a reset sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, a first auxiliary control sub-circuit, and a second auxiliary control sub-circuit; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously; the pull-down node is connected to at least the pull-down control sub-circuit, the pull-down sub-circuit, and the first noise reduction sub-circuit simultaneously; the pull-down control node is connected to at least the pull-down sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit simultaneously. The input sub-circuit includes a first transistor; the reset sub-circuit includes a second transistor; the output sub-circuit includes a third transistor and a second storage capacitor; the second noise reduction sub-circuit includes a fourth transistor; the pull-down control sub-circuit includes a fifth transistor; the pull-down circuit includes a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes an eighth transistor; the first auxiliary control sub-circuit includes a first storage capacitor; the second auxiliary control sub-circuit includes a ninth transistor and a tenth transistor. The control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously. The control electrode of the second transistor is connected to the reset signal terminal, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the pull-up node; The control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal. One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal; The control electrode of the fourth transistor is connected to the pull-down node, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the signal output terminal. The control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node; The control electrode of the sixth transistor is connected to the pull-down control node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down node; The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node. The control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node; One end of the first storage capacitor is connected to the pull-down control node, and the other end is connected to the first power supply voltage terminal; the pull-down control node is connected to the second terminal of the first transistor; The control electrode of the ninth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the tenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

12. A shift register unit, wherein, The shift register unit includes: an input sub-circuit, a reset sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, a first auxiliary control sub-circuit, and a second auxiliary control sub-circuit; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously; the pull-down node is connected to at least the pull-down control sub-circuit, the pull-down sub-circuit, and the first noise reduction sub-circuit simultaneously; the pull-down control node is connected to at least the pull-down sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit simultaneously. The input sub-circuit includes a first transistor; the reset sub-circuit includes a second transistor; the output sub-circuit includes a third transistor and a second storage capacitor; the second noise reduction sub-circuit includes a fourth transistor; the pull-down control sub-circuit includes a fifth transistor; the pull-down circuit includes a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes an eighth transistor; the first auxiliary control sub-circuit includes an eleventh transistor; the second auxiliary control sub-circuit includes a twelfth transistor and a thirteenth transistor. The control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously. The control electrode of the second transistor is connected to the reset signal terminal, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the pull-up node; The control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal. One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal; The control electrode of the fourth transistor is connected to the pull-down node, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the signal output terminal. The control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node; The control electrode of the sixth transistor is connected to the pull-down control node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down node; The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node. The control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node; The control electrode and the first electrode of the eleventh transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-down control node. The control electrode of the twelfth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the thirteenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

13. A shift register unit, wherein, The shift register unit includes: an input sub-circuit, a reset sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, a first auxiliary control sub-circuit, and a second auxiliary control sub-circuit; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously; the pull-down node is connected to at least the pull-down control sub-circuit, the pull-down sub-circuit, and the first noise reduction sub-circuit simultaneously; the pull-down control node is connected to at least the pull-down sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit simultaneously. The input sub-circuit includes a first transistor; the reset sub-circuit includes a second transistor; the output sub-circuit includes a third transistor and a second storage capacitor; the second noise reduction sub-circuit includes a fourth transistor; the pull-down control sub-circuit includes a fifth transistor; the pull-down sub-circuit includes a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes an eighth transistor; the first auxiliary control sub-circuit includes a fourteenth transistor; the second auxiliary control sub-circuit includes a fifteenth transistor and a sixteenth transistor. The control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the pull-up node is connected to at least the input sub-circuit, the output sub-circuit, and the first noise reduction sub-circuit simultaneously. The control electrode of the second transistor is connected to the reset signal terminal, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the pull-up node; The control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal. One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal; The control electrode of the fourth transistor is connected to the pull-down node, the first electrode is connected to the second reference level terminal, and the second electrode is connected to the signal output terminal. The control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node; The control electrode of the sixth transistor is connected to the pull-down control node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down node; The control electrode of the seventh transistor is connected to the signal input terminal, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node. The control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node; The control electrode and the first electrode of the fourteenth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down control node; The control electrode of the fifteenth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node; the control electrode of the sixteenth transistor is connected to the auxiliary control terminal, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-down control node.

14. A gate driving circuit, wherein, The gate drive circuit includes a plurality of cascaded shift register units as described in any one of claims 1-13.

15. The gate drive circuit according to claim 14, wherein, The signal input terminal of this level shift register unit is connected to the signal output terminal of the previous level shift register unit; The reset signal terminal of this level shift register unit is connected to the signal output terminal of the next level shift register unit; The auxiliary control terminal of this level shift register unit is connected to the signal output terminal of the next level shift register unit.

16. A display device, wherein, The display device includes the gate driving circuit as described in any one of claims 14-15.

17. A method for driving a shift register unit, used to drive the shift register unit as described in any one of claims 1-13, wherein, The driving method for the shift register unit includes: When the pull-down node is the first reference level signal, the third reference level signal is written into the pull-down control node using the first auxiliary control sub-circuit, and the pull-down sub-circuit is closed to control the first noise reduction sub-circuit to turn off. When the pull-down node is the first power supply voltage signal, the second auxiliary control sub-circuit is used to write the first reference level signal into the pull-down control node and control the pull-down sub-circuit to turn off, so as to control the first noise reduction sub-circuit to reduce noise on the pull-up node through the second reference level signal.

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