Backplane with detection function and chip detection method

Abstract

The present application relates to a backboard with detection function and a chip detection method. The backboard comprises a substrate, a first electrode, a second electrode and a detection circuit. The first electrode and the second electrode are respectively arranged on one side of the substrate and used for binding a to-be-detected chip. The detection circuit comprises a resistor connected in series with the first electrode and a deformation part connected in parallel with the resistor. The deformation part is located between the first electrode and the second electrode. The deformation part is configured to be deformed in a power-on state, so that the abnormal chip is lifted by the deformation part when the to-be-detected chip is an abnormal chip. The backboard can simply determine the abnormal chip in the to-be-detected chip and facilitate the removal of the abnormal chip, thereby improving the chip detection efficiency and the chip transfer yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a backplane and chip testing method with detection function. Background Technology

[0002] Light-emitting diode (LED) display panels are widely used in display devices due to their advantages such as high brightness, wide dynamic range, long lifespan, and stability and reliability.

[0003] An LED display panel includes a driver backplane and LED chips arranged in an array on the driver backplane. Mass transfer of LED chips is a crucial step in the manufacturing process of an LED display panel. Mass transfer refers to the precise transfer of millions or even tens of millions of LED chips from the growth substrate to the driver backplane.

[0004] During the mass transfer process, some LED chips may be damaged, resulting in a low transfer yield. Therefore, identifying defective chips from the transferred LED chips in a timely manner is an urgent problem to be solved. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a backplane and chip detection method with detection function, which aims to solve the problem of how to identify abnormal chips in a timely manner from transferred LED chips.

[0006] A backplane with detection function includes: a substrate, a first electrode, a second electrode, and a detection circuit. The first electrode and the second electrode are respectively disposed on one side of the substrate for bonding a chip under test (DUT). The detection circuit includes: a resistor connected in series with the first electrode, and a deformation portion connected in parallel across the resistor. The deformation portion is located between the first electrode and the second electrode. The deformation portion is configured to deform when energized, so that when the DUT is a faulty chip, the faulty chip is lifted by the deformation portion.

[0007] In the aforementioned backplane with detection function, the detection circuit includes a resistor connected in series with the first electrode on the substrate, and a deformation section connected in parallel across the resistor. After the chip under test (DUT) is bonded to the corresponding first and second electrodes on the substrate, the deformation section in the detection circuit located between the first and second electrodes can deform under energized conditions, thus lifting up the faulty chip if it is faulty. This allows for a relatively simple identification of faulty chips within the DUT and facilitates their removal, thereby improving chip detection efficiency and chip transfer yield.

[0008] In some embodiments, the deformable portion includes a piezoelectric material portion; the piezoelectric material portion is configured to expand in an energized state.

[0009] The aforementioned deformation section is constructed using a piezoelectric material, which not only facilitates its fabrication but also allows for easy control of deformation by utilizing the current transmitted from the chip under test when the chip is lit.

[0010] In some embodiments, the deformation portion is further configured to deform under energized conditions, so that when the chip under test is a normal chip, the normal chip is lifted by the deformation portion. The deformation amount of the deformation portion corresponding to the abnormal chip is greater than the deformation amount of the deformation portion corresponding to the normal chip.

[0011] In the aforementioned backplane with detection function, the deformable portion may also push up a normal chip after deformation. This means that the control precision for the deformation of the deformable portion in this application can be relatively low, reducing the structural design and fabrication difficulty of the deformable portion. Furthermore, since the deformation amount of the deformable portion corresponding to the abnormal chip is greater than that of the deformable portion corresponding to the normal chip, even if the deformable portion also pushes up the normal chip after deformation, the abnormal chip can still be accurately identified from the chips under test by measuring the difference between the deformation amounts of the deformable portion corresponding to the abnormal chip and the deformation amounts of the deformable portion corresponding to the normal chip.

[0012] In some embodiments, the deformable portion has a gap between itself and the chip under test bonded to the first and second poles on the side opposite to the substrate in its natural state.

[0013] For example, the maximum deformation of the deformation part when the chip under test is a normal chip is less than the size of the gap in the corresponding deformation direction, and the minimum deformation of the deformation part when the chip under test is an abnormal chip is greater than the size of the gap in the corresponding deformation direction.

[0014] In the aforementioned backplane with detection function, a gap is provided between the deformable part and the chip under test. This gap can be used to match the deformation of the deformable part to that of a normal chip. This ensures that after deformation, the deformable part corresponding to a normal chip will not cause the normal chip to be lifted, while the deformable part corresponding to an abnormal chip can lift the abnormal chip. In this way, abnormal chips can be more easily identified and removed from the chips under test.

[0015] In some embodiments, the resistor is located on the side of the first electrode closer to the substrate, and the orthographic projection of the resistor on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate. This facilitates fabricating the resistor below the first electrode, for example, directly on the substrate, thereby simplifying the design of the resistor's placement and circuit connections.

[0016] In some embodiments, there is a gap between the deformable portion and the first electrode, and between the deformable portion and the second electrode, in a direction parallel to the substrate. This allows the deformable portion to maintain a certain distance from the first and second electrodes, so as to avoid friction or unnecessary electrical connection between the deformable portion and the first and second electrodes on its side when the deformable portion deforms in a direction perpendicular to the substrate.

[0017] In some embodiments, the two ends of the deformable portion along the direction perpendicular to the substrate are respectively connected to the two ends of the resistor via conductive portions. This facilitates the fabrication of an electrical connection between the deformable portion and the resistor.

[0018] In some embodiments, the backplate with detection function further includes an adsorption structure. The adsorption structure is located on the side of the chip under test away from the substrate, and is used to adsorb and remove the abnormal chip after the deformed portion lifts the abnormal chip.

[0019] The aforementioned backplate with detection function also includes an adsorption structure. This structure can adsorb the faulty chip after the deformed portion lifts it up, making it easier to remove.

[0020] Based on the same inventive concept, this application also provides a chip detection method, which is applied to a backplane with detection function in some of the foregoing embodiments.

[0021] The chip testing method includes the following steps: A chip under test (DUT) is provided and bonded to the side of the first and second electrodes facing away from the substrate. The DUT is then powered on. A deformation section deforms under power-on conditions to lift the faulty chip if it is faulty.

[0022] In the chip testing method described above, a chip under test (DUT) is provided and bonded to the side of the first and second electrodes facing away from the substrate. Next, the DUT can be powered on. This energizes the deformation section, causing it to deform and lift any faulty chips present. This testing method allows for relatively simple identification of faulty chips from the DUT and facilitates their removal, thereby improving chip testing efficiency and chip transfer yield.

[0023] In some embodiments, the backplane with detection function further includes an adsorption structure. The chip detection method further includes using the adsorption structure to adsorb and remove abnormal chips that have been lifted up by the deformed portion.

[0024] In the chip detection method described above, an adsorption structure can be used to remove abnormal chips that have been lifted up by the deformed part. This method is relatively simple and easy to implement. Attached Figure Description

[0025] Figure 1A cross-sectional schematic diagram of a backplate with detection function provided in an embodiment of this application;

[0026] Figure 2 A cross-sectional schematic diagram of a backplane with detection function and a chip under test provided in an embodiment of this application;

[0027] Figure 3 An equivalent circuit diagram showing the connection relationship between a resistor, a deformable part, and a chip under test, provided in an embodiment of this application;

[0028] Figure 4 A cross-sectional schematic diagram of another backplane and chip under test with detection function provided in an embodiment of this application;

[0029] Figure 5 A cross-sectional schematic diagram of a backplane with detection function and a chip under test provided in an embodiment of this application;

[0030] Figure 6 This is a schematic flowchart of a chip detection method provided in an embodiment of this application.

[0031] Explanation of reference numerals in the attached figures:

[0032] 1-Substrate; 11-First electrode; 12-Second electrode; 2-Detection circuit; 21-Resistor;

[0033] 22-Deformation section; 3-Chip under test; 31-Epipolar layer; 32-First pad; 33-Second pad;

[0034] 4-Conductive part; 5-Adsorption structure; 51-Adsorption head. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0037] LED display panels are widely used in display devices due to their advantages such as high brightness, wide dynamic range, long service life, and stability and reliability.

[0038] An LED display panel includes a driver backplane and LED chips arranged in an array on the driver backplane. Mass transfer of LED chips is a crucial step in the manufacturing process of an LED display panel. Mass transfer refers to the precise transfer of millions or even tens of millions of LED chips from the growth substrate to the driver backplane.

[0039] During the mass transfer process, some LED chips may be damaged. Damaged LED chips have lower impedance, which will cause them to have a larger operating current after being turned on on the driver backplane. This will result in them emitting brighter light than normal LED chips, thus affecting the light emission uniformity of the display panel where the driver backplane is located.

[0040] Therefore, this application aims to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in subsequent embodiments.

[0041] This application provides a backplane with detection function, which is suitable for detecting LED chips. For ease of understanding, the following description uses an LED chip as an example to illustrate the backplane with detection function in the embodiments of this application. It is understood that the LED chip can be a mini LED chip or a micro LED chip, and is not limited here.

[0042] Please see Figure 1 and Figure 2 The backplane with detection function includes: substrate 1 and detection circuit 2.

[0043] A first electrode 11 and a second electrode 12 are respectively disposed on one side of the substrate 1. The first electrode 11 and the second electrode 12 are used to bond the chip under test 3.

[0044] The detection circuit 2 includes a resistor 21 connected in series with the first electrode 11, and a deformation section 22 connected in parallel across the resistor 21. The deformation section 22 is located between the first electrode 11 and the second electrode 12. The deformation section 22 is configured to deform when energized, so that when the chip under test 3 is a faulty chip, the faulty chip is lifted up by the deformation section.

[0045] The aforementioned abnormal chip may be, for example, a chip that emits high brightness after being damaged.

[0046] like Figure 2 As shown, the chip under test 3 includes an epitaxial layer 31 and a first pad 32 and a second pad 33 disposed on one side of the epitaxial layer 31. The first pad 32 and the second pad 33 are respectively connected to a first electrode 11 and a second electrode 12 on the substrate 1, so that the chip under test 3 is bonded to the first electrode 11 and the second electrode 12, that is, the chip under test 3 is fixed on the substrate 1.

[0047] For example, the first electrode 11 can be a negative electrode, and the second electrode 12 can be a positive electrode.

[0048] In some examples, the materials for the first electrode 11 and the second electrode 12 can be selected from metals with good electrical conductivity, such as indium (In), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu).

[0049] For example, the first pad 32 can be the negative terminal of the chip under test 3, and the second pad 33 can be the positive terminal of the chip under test 3.

[0050] In some examples, the materials of the first pad 32 and the second pad 33 can be selected from metals with good electrical conductivity, such as indium (In), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu).

[0051] In some embodiments, the two ends of the deformable portion 22 along the direction perpendicular to the substrate 1 are respectively connected to the two ends of the resistor 21 via the conductive portion 4. This facilitates the fabrication of an electrical connection between the deformable portion 22 and the resistor 21.

[0052] For example, the deformable part 22 is connected to the resistor 21 via the conductive part 4 on the side close to the substrate 1, and the deformable part 22 is connected to the first electrode 11 via the conductive part 4 on the side away from the substrate 1, so that the deformable part 22 and the resistor 21 can be connected in parallel.

[0053] Optionally, the conductive part 4 can be a conductive wire or a conductive sheet.

[0054] The equivalent circuit diagram of the connection relationship between resistor 21, deformation part 22 and chip under test 3 in some of the aforementioned embodiments is as follows: Figure 3 As shown. After the chip under test 3 is turned on, the current flows out from the negative terminal of the chip under test 3 and splits into two paths, one flowing through resistor 21 and the other flowing through deformation section 22. In this way, deformation section 22 is also turned on, so that it can deform according to the current flowing through it when energized.

[0055] The aforementioned backplane with detection function includes a substrate 1 and a detection circuit 2. The detection circuit 2 includes a resistor 21 connected in series with a first electrode 11 of the substrate 1, and a deformation portion 22 connected in parallel across the resistor 21. After the chip under test (DUT) 3 is bonded to the first electrode 11 and the second electrode 12 on the substrate, the deformation portion 22 located between the first electrode 11 and the second electrode 12 in the detection circuit 2 can deform under energized conditions, thereby lifting up any faulty chips in the DUT 3. This allows for a relatively simple identification of faulty chips in the DUT 3 and facilitates their removal, thus improving chip detection efficiency and chip transfer yield.

[0056] Furthermore, it is understood that the aforementioned backplane refers to a driving backplane on substrate 1 that has driving circuitry and chip illumination functionality. This backplane can be the driving backplane for a display panel, meaning that after chip transfer and testing are completed, subsequent processes can be performed to fabricate the display panel. This also ensures that all chips in the display panel are functioning correctly, thereby improving the light emission uniformity of the display panel.

[0057] In some embodiments, the deformable portion 22 includes a piezoelectric material portion. The piezoelectric material portion is configured to expand in an energized state.

[0058] For example, the material of the piezoelectric material part can be: piezoelectric ceramic, piezoelectric crystal or polyvinylidene fluoride (PVDF).

[0059] In this embodiment, the direction of deformation of the piezoelectric material is consistent with the direction of the applied voltage. Thus, when a voltage is applied between the side of the piezoelectric material away from the substrate 1 and the side closer to the substrate 1, the piezoelectric material can expand along the direction of the voltage to lift up the faulty chip.

[0060] The aforementioned deformation part 22 is made of piezoelectric material, which is not only convenient to manufacture, but also easy to use the current transmitted from the chip under test 3 when the chip under test 3 is lit to control the deformation of the deformation part 22.

[0061] Please continue reading. Figure 3 After the deformation section 22 is energized, both the deformation section 22 corresponding to the normal chip and the deformation section 22 corresponding to the abnormal chip will deform. It can be understood that since the current flowing through the abnormal chip is greater than the current flowing through the normal chip, the current flowing through the deformation section 22 corresponding to the abnormal chip will also be greater than the current flowing through the deformation section 22 corresponding to the normal chip. Therefore, the deformation amount of the deformation section 22 corresponding to the abnormal chip will be greater than the deformation amount of the deformation section 22 corresponding to the normal chip.

[0062] It should be understood that the backplane with detection function in the embodiments of this application can detect multiple chips under test 3 at the same time, and each chip under test 3 will correspond to a deformation part 22.

[0063] For example, multiple deformation sections 22 correspond one-to-one with resistors 21, and the resistance values ​​of each resistor 21 are the same. In this way, it can be further ensured that the current flowing through the deformation section 22 corresponding to the abnormal chip is greater than the current flowing through the deformation section 22 corresponding to the normal chip.

[0064] Based on the above analysis, the embodiments of this application can determine the abnormal chip from the chip under test 3 by adopting different implementation methods according to the difference between the deformation of the deformation part 22 corresponding to the abnormal chip and the deformation of the deformation part 22 corresponding to the normal chip.

[0065] In some embodiments, the deformation portion 22 is further configured to deform in a powered state, so that when the chip under test 3 is a normal chip, the normal chip is lifted by the deformation portion 22. The deformation amount of the deformation portion 22 corresponding to the abnormal chip is greater than the deformation amount of the deformation portion 22 corresponding to the normal chip.

[0066] It should be noted that although the normal chip will be lifted by the deformation part 22, the height that the normal chip is allowed to be lifted is small and will not affect the normal use of the subsequent normal chip.

[0067] In the aforementioned backplane with detection function, the deformation portion 22 may also lift up a normal chip after deformation. This means that the control precision for the deformation of the deformation portion 22 in this application can be relatively low, reducing the structural design and fabrication difficulty of the deformation portion 22. Furthermore, since the deformation amount of the deformation portion 22 corresponding to the abnormal chip is greater than that of the deformation portion 22 corresponding to the normal chip, even though the deformation portion 22 will lift up a normal chip after deformation, the abnormal chip can still be accurately identified from the chip under test 3 by measuring the difference between the deformation amounts of the deformation portion 22 corresponding to the abnormal chip and the deformation amounts of the deformation portion 22 corresponding to the normal chip.

[0068] Please see Figure 4 In other embodiments, the deformable portion 22 has a gap between itself and the chip under test 3 bonded to the first electrode 11 and the second electrode 12 on the side opposite to the substrate 1 in its natural state.

[0069] For example, when the chip under test 3 is a normal chip, the maximum deformation of the deformation part 22 is less than the size of the gap in the corresponding deformation direction. When the chip under test 3 is an abnormal chip, the minimum deformation of the deformation part 22 is greater than the size of the gap in the corresponding deformation direction.

[0070] In the aforementioned backplane with detection function, a gap is provided between the deformable part 22 and the chip under test 3. This gap allows for matching the deformation of the deformable part 22 to that of a normal chip. This ensures that after deformation, the deformable part 22 corresponding to a normal chip will not cause the normal chip to be lifted, while the deformable part 22 corresponding to an abnormal chip can lift the abnormal chip. This makes it easier to identify and remove abnormal chips from the chip under test 3.

[0071] In this embodiment, the shape and size of the deformable part 22 can be selected and set according to actual needs.

[0072] For example, the shape of the deformable part 22 in its natural state includes: cuboid, cube, or cylinder.

[0073] For example, in the direction parallel to the substrate 1, there is a gap between the deformable portion 22 and the first electrode 11, and between the deformable portion 22 and the second electrode 12. In this way, the deformable portion 22 can be kept at a certain distance from the first and second electrodes to avoid friction or unnecessary electrical connection between it and the first and second electrodes on its side when the deformable portion 22 deforms in the direction perpendicular to the substrate 1.

[0074] In some embodiments, the deformable portion 22 can be fixed to the substrate 1. In this way, the deformable portion 22 can remain stable when it deforms.

[0075] In this embodiment, the resistance value and setting position of resistor 21 can be selected and set according to actual needs.

[0076] For example, the resistance value ranges from 0.5Ω to 3Ω, such as 0.5Ω, 1Ω, 1.5Ω, 2Ω, 2.5Ω or 3Ω.

[0077] In some embodiments, the resistor 21 is located on the side of the first electrode 11 closest to the substrate 1, and the orthographic projection of the resistor 21 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 11 on the substrate 1. This facilitates the fabrication of the resistor below the first electrode, for example, directly on the substrate, thereby simplifying the design of the resistor's placement and circuit connection.

[0078] In other embodiments, resistor 21 may be integrated into the drive circuit on substrate 1.

[0079] In the aforementioned backplane with detection function, when manufacturing substrate 1, resistor 21 can be pre-integrated into the driving circuit of substrate 1, thereby facilitating circuit design.

[0080] Please see Figure 5In some embodiments, the backplate with detection function further includes an adsorption structure 5. The adsorption structure 5 is located on the side of the chip under test 3 away from the substrate 1, and is used to adsorb and remove the abnormal chip after the deformed part 22 lifts the abnormal chip.

[0081] For example, the adsorption structure 5 includes an adsorption head 51.

[0082] Alternatively, the adsorption head 51 may be a vacuum adsorption head, an electrostatic adsorption head, or a polydimethylsiloxane (PDMS) adsorption head.

[0083] Optionally, the orthographic projection of the adsorption head 51 on the substrate 1 coincides with the orthographic projection of the chip under test 3 on the substrate 1. This allows the adsorption head 51 to be matched with the chip under test 3, giving the adsorption head 51 a larger adsorption area and making it easier to adsorb faulty chips. Furthermore, while adsorbing a faulty chip, it will not touch other faulty chips adjacent to it.

[0084] For example, there is a gap between the adsorption structure 5 and the chip under test 3. The value of this gap can be selected and set according to actual needs. However, the value of this gap needs to ensure that after the deformation part 22 deforms, the normal chip cannot touch the adsorption structure 5, while the abnormal chip can touch the adsorption structure 5.

[0085] The backplate with detection function described above is also equipped with an adsorption structure 5. The adsorption structure 5 can adsorb the abnormal chip after the deformable part 22 lifts it up, which makes it easier to remove the abnormal chip.

[0086] Based on the same inventive concept, this application also provides a chip detection method, applied to a backplane with detection function in some of the foregoing embodiments. The structure of the backplane can be referred to in the foregoing embodiments. Figure 1 , Figure 2 , Figure 4 and Figure 5 .

[0087] Please see Figure 2 and Figure 6 The chip detection method includes steps S10 to S30.

[0088] S10, provide the chip under test 3, and bind the chip under test 3 to the side of the first electrode 11 and the second electrode 12 away from the substrate 1.

[0089] The chip under test 3 includes an epitaxial layer 31 and a first pad 32 and a second pad 33 disposed on one side of the epitaxial layer 31. The first pad 32 and the second pad 33 are respectively connected to a first electrode 11 and a second electrode 12 on the substrate 1, so that the chip under test 3 is bonded to the first electrode 11 and the second electrode 12.

[0090] For example, the first electrode 11 can be a negative electrode, and the second electrode 12 can be a positive electrode. The first pad 32 can be the negative electrode of the chip under test 3, and the second pad 33 can be the positive electrode of the chip under test 3.

[0091] S20, turn on chip 3 under test.

[0092] It is understood that a driving circuit for driving the chip under test is provided on the substrate 1, and the driving circuit can light up the chip under test 3.

[0093] S30, the deformation part 22 deforms when energized, so that when the chip under test 3 is a faulty chip, the faulty chip is lifted by the deformation part 22.

[0094] For example, the deformable part 22 includes a piezoelectric material part. The piezoelectric material part is configured to expand in an energized state.

[0095] For example, the backplate also includes a resistor 21 connected in parallel with the deformation part 22. The resistor 21 and the deformation part 22 together constitute the detection circuit 2.

[0096] Optionally, the deformable part 22 is connected to the resistor 21 via the conductive part 4 on the side close to the substrate 1, and the deformable part 22 is connected to the first electrode 11 via the conductive part 4 on the side away from the substrate 1, so that the deformable part 22 and the resistor 21 can be connected in parallel.

[0097] For example, the material of the piezoelectric material part can be: piezoelectric ceramic, piezoelectric crystal or polyvinylidene fluoride (PVDF).

[0098] In this embodiment, the direction of deformation of the piezoelectric material is consistent with the direction of the applied voltage. Thus, when a voltage is applied between the side of the piezoelectric material away from the substrate and the side closer to the substrate, the piezoelectric material can expand along the direction of the voltage to lift up the malfunctioning chip.

[0099] In the above chip testing method, a chip under test (DUT) 3 can be provided and bonded to the side of the first electrode 11 and the second electrode 12 facing away from the substrate 1. Next, the DUT 3 can be powered on. This also energizes the deformation section 22, causing it to deform. If the DUT 3 is a faulty chip, the faulty chip is lifted by the deformation section 22. This testing method can relatively easily identify faulty chips from the DUTs and facilitates the removal of faulty chips, thereby improving chip testing efficiency and chip transfer yield.

[0100] Please see Figure 5 and Figure 6 In some embodiments, the backplate further includes an adsorption structure 5. The chip detection method further includes step S40.

[0101] S40, using adsorption structure 5, adsorbs and removes the abnormal chip that is lifted up by the deformed part 22.

[0102] In the chip detection method described above, the adsorption structure 5 can be used to remove abnormal chips that are lifted by the deformed part 22. This method is relatively simple and easy to implement.

[0103] In some embodiments, normal chips may be selected to fill the empty spaces left after removing abnormal chips, so as to ensure that each light-emitting area of ​​the display panel where the backplate is located is equipped with normal chips.

[0104] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A backplate with detection function, characterized in that, include: substrate; A first electrode and a second electrode, respectively disposed on one side of the substrate, are used to bond the chip under test. The detection circuit includes: a resistor connected in series with the first pole, and a deformation portion connected in parallel across the resistor; The deformation part is located between the first electrode and the second electrode; the deformation part is configured to deform in the energized state so that when the chip under test is a faulty chip, the faulty chip is lifted up by the deformation part. Specifically, the current flowing through the abnormal chip is greater than the current flowing through the normal chip, the current flowing through the deformed part corresponding to the abnormal chip is greater than the current flowing through the deformed part corresponding to the normal chip, and the deformation of the deformed part corresponding to the abnormal chip is greater than the deformation of the deformed part corresponding to the normal chip.

2. The backplate with detection function as described in claim 1, characterized in that, The deformable portion includes a piezoelectric material portion; the piezoelectric material portion is configured to expand in an energized state.

3. The backplate with detection function as described in claim 1, characterized in that, The deformable portion has a gap between itself and the chip under test, which is bonded to the first and second poles on the side opposite to the substrate, in its natural state.

4. The backplate with detection function as described in claim 3, characterized in that, The maximum deformation of the deformable part when the chip under test is a normal chip is less than the size of the gap in the corresponding deformation direction; The minimum deformation of the deformation part when the chip under test is an abnormal chip is greater than the size of the gap in the corresponding deformation direction.

5. The backplate with detection function as described in claim 1, characterized in that, The resistor is located on the side of the first electrode closer to the substrate, and the orthographic projection of the resistor on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate.

6. The backplate with detection function as described in claim 1, characterized in that, Along a direction parallel to the substrate, there is a gap between the deformed portion and the first electrode, and between the deformed portion and the second electrode.

7. The backplate with detection function as described in claim 1, characterized in that, The deformable portion is connected to the two ends of the resistor via conductive portions at both ends along the direction perpendicular to the substrate.

8. The backplate with detection function as described in claim 1, characterized in that, The back plate further includes: an adsorption structure; The adsorption structure is located on the side of the chip under test away from the substrate, and is used to adsorb and remove the abnormal chip after the deformed part lifts the abnormal chip.

9. A chip detection method, characterized in that, Applied to a backplane with detection function as described in any one of claims 1 to 8; the chip detection method includes: A chip under test is provided, and the chip under test is bonded to the side of the first electrode and the second electrode opposite to the substrate; Light up the chip under test; The deformation part deforms when energized, so that when the chip under test is a faulty chip, the faulty chip is lifted up by the deformation part.

10. The chip detection method as described in claim 9, characterized in that, The backplate further includes an adsorption structure; the chip detection method further includes: The abnormal chip, which was lifted up by the deformed part, is removed by adsorption using the adsorption structure.

Images