Multi-core processor exception detection method and apparatus, electronic device, and storage medium

Abstract

The application relates to an artificial intelligence technology and discloses a multi-core processor anomaly detection method, which comprises the following steps: acquiring a multivariate time sequence of an occupation rate sequence of a multi-core processor, generating an adjacency matrix of the multi-core processor according to the multivariate time sequence; performing graph Fourier transform and short-time Fourier transform on a graph signal of the adjacency matrix to obtain a frequency domain feature; generating a context feature of the frequency domain feature by using a preset attention mechanism, performing inverse Fourier transform on the context feature to obtain detection data of the context feature; determining abnormal data in the detection data according to a preset detection threshold, and determining an abnormal module in the multi-core processor according to the abnormal data. In addition, the application also relates to a blockchain technology, and a data list can be stored in a node of the blockchain. The application further provides a multi-core processor anomaly detection device, an electronic equipment and a storage medium. The application is applied to the field of digital medicine and can improve the efficiency of multi-core processor anomaly detection.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to a method, apparatus, electronic device, and computer-readable storage medium for detecting anomalies in multi-core processors. Background Technology

[0002] In medical systems, various programs are needed to record and process information. When there are too many background programs and applications, the processor will be under heavy load. Although multi-core processors can effectively improve processor performance through parallel processing compared to single-core processors, they also face huge challenges in terms of architecture, software, power consumption and security design. As one of the important indicators of normal server operation, processors often encounter abnormal or unexpected occupancy rates in daily production and life.

[0003] Most current methods define a pre-defined adjacency matrix. However, since the accurate relationship between multi-core processor utilization rates cannot be known in advance, the pre-defined adjacency matrix often fails to fully reflect the true dependencies between utilization rate sequences, resulting in poor algorithm results. Furthermore, multi-core processor utilization time series data exhibits strong regularity and anomalous mutations, while most current algorithms for multi-core processor utilization prediction are based on time-domain analysis, making them ill-suited to these characteristics. Moreover, convolution of time-domain data in graph neural network algorithms often consumes significant computational power and time. Therefore, improving the efficiency of multi-core processor anomaly detection has become an urgent problem to be solved. Summary of the Invention

[0004] This invention provides a method, apparatus, and computer-readable storage medium for detecting anomalies in multi-core processors, with the main objective of solving the problem of low efficiency in detecting anomalies in multi-core processors.

[0005] To achieve the above objectives, the present invention provides a method for detecting anomalies in a multi-core processor, comprising:

[0006] Obtain a multivariate time series of the utilization rate sequence of a multi-core processor, and generate an adjacency matrix of the multi-core processor based on the multivariate time series;

[0007] Perform a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal;

[0008] The frequency domain features of the spectral domain features are obtained by performing a short-time Fourier transform on the spectral domain features.

[0009] The contextual features of the frequency domain features are generated using a preset attention mechanism, and the contextual features are subjected to inverse Fourier transform to obtain the detection data of the contextual features.

[0010] Abnormal data in the detection data is determined based on a preset detection threshold, and abnormal modules in the multi-core processor are determined based on the abnormal data.

[0011] Optionally, generating the adjacency matrix of the multi-core processor based on the multivariate time series includes:

[0012] The graph nodes of the multi-core processor are generated based on the multivariate time series, and the graph nodes are initialized to obtain the node embedding matrix of the graph nodes.

[0013] The node embedding matrix is ​​regularized according to the preset activation function hyperparameters and preset linear transformation parameters to obtain the adjacency matrix of the multi-core processor.

[0014] Optionally, performing a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal includes:

[0015] The spatial data of the adjacency matrix is ​​generated based on the graph signal of the adjacency matrix;

[0016] A projection basis for the spatial data is generated using a preset Laplace matrix. A graph Fourier transform is then performed on the spatial data based on the projection basis to obtain the spectral domain features of the graph signal.

[0017] Optionally, performing a short-time Fourier transform on the spectral domain features to obtain the frequency domain features of the spectral domain features includes:

[0018] The temporal order of the spectral features is determined, and the spectral features are windowed according to the temporal order to obtain multiple sub-spectral features of the spectral features.

[0019] Perform Fourier transform on each of the sub-spectral domain features to obtain the sub-frequency domain features of the sub-spectral domain features;

[0020] The sub-frequency domain features are spliced ​​together according to the time sequence to obtain the frequency domain features of the spectral domain features.

[0021] Optionally, the step of windowing the spectral features according to the time sequence to obtain multiple sub-spectral features of the spectral features includes:

[0022] The spectral domain features are windowed using the following window function to obtain multiple sub-spectral domain features of the spectral domain features:

[0023]

[0024] Where x is the abscissa of the spectral domain feature, y is the ordinate of the spectral domain feature, G(x,y) is the window function value with respect to the abscissa and the ordinate, σ is the standard deviation, and e is the natural logarithm.

[0025] Optionally, generating the contextual features of the frequency domain features using a preset attention mechanism includes:

[0026] A feature matrix of the frequency domain features is generated using a preset attention mechanism, and a multi-head attention matrix of the frequency domain features is generated based on the feature matrix.

[0027] The frequency domain features are subjected to self-attention processing to obtain the self-attention matrix of the frequency domain features;

[0028] The multi-head attention matrix and the self-attention matrix are normalized to obtain the contextual features of the frequency domain features.

[0029] Optionally, performing an inverse Fourier transform on the contextual features to obtain the detection data of the contextual features includes:

[0030] The context features are subjected to inverse short-time Fourier transform to obtain the context spatial data of the context features.

[0031] The contextual spatial data is used to generate contextual frequency domain data of the contextual features. An inverse graphical Fourier transform is performed on the contextual frequency domain data to obtain contextual time domain data of the contextual frequency domain data. The contextual time domain data is then determined as the detection data of the contextual features.

[0032] To address the above problems, the present invention also provides a multi-core processor anomaly detection device, the device comprising:

[0033] The adjacency matrix module is used to obtain a multivariate time series of the utilization rate sequence of the multi-core processor, and generate the adjacency matrix of the multi-core processor based on the multivariate time series.

[0034] The spectral domain feature module is used to perform a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal.

[0035] The frequency domain feature module is used to perform a short-time Fourier transform on the spectral domain features to obtain the frequency domain features of the spectral domain features;

[0036] The detection data module is used to generate contextual features of the frequency domain features using a preset attention mechanism, and to perform inverse Fourier transform on the contextual features to obtain detection data of the contextual features.

[0037] An abnormal data module is used to determine abnormal data in the detection data according to a preset detection threshold, and to determine the abnormal module in the multi-core processor according to the abnormal data.

[0038] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0039] At least one processor; and,

[0040] A memory communicatively connected to the at least one processor; wherein,

[0041] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the multi-core processor anomaly detection method described above.

[0042] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one computer program, which is executed by a processor in an electronic device to implement the multi-core processor anomaly detection method described above.

[0043] This invention generates an adjacency matrix for a multi-core processor based on the multivariate time series, establishing hidden mutual influence relationships among the various utilization time series of the multi-core processor. The graph neural network-based time series algorithm demonstrates high capability in processing relationships between multivariate time series. Therefore, a graph Fourier transform is performed on the graph signal of the adjacency matrix. By performing a short-time Fourier transform on the spectral domain features, some temporal information is avoided. Compared to the Fourier transform, which can only analyze global features, the short-time Fourier transform is more efficient and less susceptible to the influence of distant sequence values. It can perform noise reduction processing on the local sequence of processor utilization while analyzing it. On the other hand, if processor utilization data is abnormal, it is mostly due to abrupt changes. For such abrupt anomalies and the regularity of the sequence, the windowed Fourier algorithm can effectively extract the features of the sequence within each window, identify the periodicity of processor utilization, and analyze local features in a targeted manner. Therefore, this invention proposes a multi-core processor anomaly detection method, device, electronic device, and computer-readable storage medium, which can solve the problem of low efficiency in multi-core processor anomaly detection. Attached Figure Description

[0044] Figure 1 This is a flowchart illustrating a multi-core processor anomaly detection method according to an embodiment of the present invention.

[0045] Figure 2 This is a schematic diagram of the process for generating frequency domain features according to an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the process for generating contextual features according to an embodiment of the present invention;

[0047] Figure 4 This is a functional block diagram of a multi-core processor anomaly detection device provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the structure of an electronic device that implements the multi-core processor anomaly detection method according to an embodiment of the present invention.

[0049] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0050] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0051] This application provides a method for detecting anomalies in multi-core processors. The execution entity of the multi-core processor anomaly detection method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the multi-core processor anomaly detection method can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0052] Reference Figure 1 The diagram shown is a flowchart illustrating a multi-core processor anomaly detection method according to an embodiment of the present invention. In this embodiment, the multi-core processor anomaly detection method includes:

[0053] S1. Obtain a multivariate time series of the utilization rate sequence of the multi-core processor, and generate the adjacency matrix of the multi-core processor based on the multivariate time series.

[0054] In this embodiment of the invention, the multi-core processor refers to a processor that integrates two or more complete computing engines. In this case, the processor can support multiple processors on the medical system bus, and all bus control signals and command signals are provided by the bus controller.

[0055] Furthermore, the performance of each processor in a multi-core processor is generally measured by the time required to complete a task. The shorter the task completion time in a medical system, the higher the processor performance. Tasks in a medical system include, but are not limited to: patient registration, patient payment information processing, patient medical record keeping, and patient history retrieval.

[0056] In detail, the utilization rate of the multi-core processor refers to the processor resources used by running programs in the medical system, indicating the running program status of the medical system server at a certain point in time. The higher the utilization rate, the more programs the server is running at that time, and vice versa. The utilization rate is directly related to the strength of the processor.

[0057] In detail, the multi-dimensional time series refers to the utilization rate data of the multi-core processor at different times. For example, assuming that the multi-core processor is a three-core processor, the utilization rate of the multi-core processor at a certain moment is 10%, 20%, and 30%, and the total utilization rate of the multi-core processor is 60%.

[0058] In detail, the adjacency matrix refers to a two-dimensional array that stores data on the relationships (edges or arcs) between vertices. It is a matrix that represents the adjacency relationships between vertices. The adjacency matrix is ​​further divided into directed graph adjacency matrix and undirected graph adjacency matrix.

[0059] Furthermore, since there are hidden mutual influences between the various utilization time series of the multi-core processor, an adjacency matrix of the multi-core processor is generated to characterize the relationship between the various utilization rates of the multi-core processor.

[0060] In this embodiment of the invention, generating the adjacency matrix of the multi-core processor based on the multivariate time series includes: generating graph nodes of the multi-core processor based on the multivariate time series; initializing the graph nodes to obtain a node embedding matrix of the graph nodes; and performing regularization processing on the node embedding matrix based on preset activation function hyperparameters and preset linear transformation parameters to obtain the adjacency matrix of the multi-core processor.

[0061] In detail, the graph node contains the utilization rate of the multi-core processor, which can be represented by the multivariate time series. The graph node is the target node in the graph neural network. The initialization process of the graph node is to randomly sample the neighbors of the graph node to obtain the node embedding matrix of the graph node. The random sampling can reduce the computational complexity. For example, according to the random sampling, the number of one-hop neighbors is 3 and the number of two-hop neighbors is 5.

[0062] In detail, the preset activation function hyperparameter refers to a parameter, not a known constant. The activation function hyperparameter is a configurable setting in a certain activation function, and the "correct" value is specified based on existing or current experience. It is not learned through training the model, such as the learning rate or the number of hidden layers in a deep neural network.

[0063] Furthermore, the linear transformation parameter is the medium for linear transformation of the matrix, and the node embedding matrix can be transformed into an adjacency matrix through the linear transformation parameter.

[0064] In detail, the regularization process involves adding constraints to the minimization of the empirical error function. These constraints can be interpreted as prior knowledge. The constraints have a guiding role, tending to choose the direction of gradient reduction that satisfies the constraints when optimizing the error function, so that the final solution tends to conform to the prior knowledge. For example, by aggregating the two-hop neighbor features, one-hop neighbor features are generated, and then the one-hop neighbor features are aggregated again to generate target node features, thereby obtaining two-hop neighbor information. This process is iterated continuously to obtain all target nodes. The aggregation is performed based on the regularization process.

[0065] S2. Perform a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal.

[0066] In this embodiment of the invention, the graph neural network-based time series algorithm demonstrates a high ability to process the relationships of multivariate time series, so a graph Fourier transform is performed on the graph signal of the adjacency matrix.

[0067] In this embodiment of the invention, for the graph signal, the Laplacian operator and the Laplacian matrix have the same function. The Laplacian operator is a second-order differential operator in n-dimensional Euclidean space, defined as the divergence of the gradient. The Laplacian operator has rotation invariance and can be used as the identification benchmark for the graph signal.

[0068] In detail, performing a graph Fourier transform on the graph signal of the adjacency matrix means using the eigenvectors of the Laplace matrix as the basis for the graph Fourier projection.

[0069] In this embodiment of the invention, performing a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal includes: generating spatial domain data of the adjacency matrix based on the graph signal of the adjacency matrix; generating a projection basis of the spatial domain data using a preset Laplace matrix; and performing a graph Fourier transform on the spatial domain data based on the projection basis to obtain the spectral domain features of the graph signal.

[0070] In detail, the spatial data is data represented by the graph signal and can be used to perform a graph Fourier transform.

[0071] In detail, the step of generating the projection basis of the spatial data using the preset Laplacian matrix involves first performing eigenvalue decomposition on the preset Laplacian matrix to obtain the diagonal matrix, the feature matrix, and the transpose of the feature matrix of the preset Laplacian matrix, and then generating the spectral domain features of the graph signal based on the spatial data and the feature matrix.

[0072] S3. Perform a short-time Fourier transform on the spectral domain features to obtain the frequency domain features of the spectral domain features.

[0073] In this embodiment of the invention, since the time series data of the utilization rate of multi-core CPUs has strong regularity and abnormal mutation, the detection of the utilization rate of multi-core processors is transformed from the time domain to the frequency domain by Fourier transform. However, Fourier transform performed on the entire time series is prone to ignoring the time information of the signal and has an inherent defect in processing non-stationary sequences. Therefore, a short-time Fourier transform is performed on the spectral domain features.

[0074] In detail, consider performing Fourier transform on the occupancy data of each processor in the medical system to extract the frequency domain features of the occupancy data. However, performing Fourier transform on the total occupancy of the processor will lose some time information. Short-time Fourier transform can extract the signal segment by windowing, divide the entire time domain into segments, and then perform Fourier transform on the local segments to analyze the frequency of the occupancy at a certain time point.

[0075] In this embodiment of the invention, the reference Figure 2 As shown, the step of performing a short-time Fourier transform on the spectral domain features to obtain the frequency domain features of the spectral domain features includes:

[0076] S21. Determine the temporal order of the spectral features, and perform windowing processing on the spectral features according to the temporal order to obtain multiple sub-spectral features of the spectral features;

[0077] S22. Perform Fourier transform on each of the sub-spectral domain features to obtain the sub-frequency domain features of the sub-spectral domain features;

[0078] S23. The sub-frequency domain features are spliced ​​together according to the time sequence to obtain the frequency domain features of the spectral domain features.

[0079] In detail, because a certain processor in different multi-core processors has different utilization rates at different times, the temporal order of the spectrum characteristics refers to the change in the utilization rate of a certain processor according to the temporal order.

[0080] In detail, the sub-spectral domain features are obtained by truncating the spectral domain features according to a window function.

[0081] Specifically, the step of windowing the spectral features according to the time sequence to obtain multiple sub-spectral features of the spectral features includes:

[0082] The spectral domain features are windowed using the following window function to obtain multiple sub-spectral domain features of the spectral domain features:

[0083]

[0084] Where x is the abscissa of the spectral domain feature, y is the ordinate of the spectral domain feature, G(x,y) is the window function value with respect to the abscissa and the ordinate, σ is the standard deviation, and e is the natural logarithm.

[0085] In detail, applying a window function to the spectral domain features means extracting time segments by moving the window to its position on the occupancy sequence time axis.

[0086] Furthermore, after short-time Fourier transform, the occupancy sequence of each processor is transformed from the spectral domain to the frequency domain.

[0087] S4. Generate contextual features of the frequency domain features using a preset attention mechanism, and perform inverse Fourier transform on the contextual features to obtain detection data of the contextual features.

[0088] In this embodiment of the invention, the relationship between the frequency domain features before and after the frequency domain features can be determined according to the preset attention mechanism, thereby eliminating the influence of the frequency domain features before and after the frequency domain features.

[0089] Furthermore, after introducing the attention mechanism, multiple independent attention mechanisms are adopted to capture information from neighbors. By calculating the attention score of each node relative to neighboring nodes, the node features can be updated according to the information of the learned adjacency matrix. The contextual features of the frequency domain features are generated by updating the node features with the information.

[0090] In this embodiment of the invention, the reference Figure 3 As shown, the generation of contextual features from the frequency domain features using a preset attention mechanism includes:

[0091] S31. Generate a feature matrix of the frequency domain features using a preset attention mechanism, and generate a multi-head attention matrix of the frequency domain features based on the feature matrix;

[0092] S32. Perform self-attention processing on the frequency domain features to obtain the self-attention matrix of the frequency domain features;

[0093] S33. Normalize the multi-head attention matrix and the self-attention matrix to obtain the contextual features of the frequency domain features.

[0094] In detail, generating the multi-head attention matrix of the frequency domain features based on the feature matrix refers to initializing the multi-head attention layer in the preset sequence labeling model to obtain initial parameters for multi-head attention; using the initial parameters for multi-head attention and the word vector matrix to obtain multiple multi-head attention parameter matrices of the frequency domain features; and performing weighted processing on the multi-head attention parameter matrices to obtain the multi-head attention matrix of the frequency domain features.

[0095] In this embodiment of the invention, the initial parameters of the multi-head attention include, but are not limited to, the initial number of multi-head attention, the vector dimension of each word output, a preset question matrix, a preset key matrix, and a preset value matrix.

[0096] In detail, the initialization of the multi-head attention layer in the preset sequence labeling model involves assigning values ​​to the parameters contained in the multi-head attention layer. Excellent initial parameters for multi-head attention can accelerate the convergence speed of the sequence labeling model, make the model more accurate, and reduce training and convergence time. Therefore, the sequence labeling model needs to be initialized reasonably.

[0097] In detail, the essence of multi-head attention is multiple independent attention computations that act as an integrated process to prevent overfitting, and multi-head attention helps the network capture richer features.

[0098] In this embodiment of the invention, the self-attention mechanism is used to reduce dependence on external information and is better at capturing the internal correlation of data or features. The application of the self-attention mechanism in text is mainly to solve the problem of long-distance dependence by calculating the mutual influence between words.

[0099] In detail, after the raw data undergoes data standardization, all indicators are on the same order of magnitude, making them suitable for comprehensive comparison and evaluation. The most typical example is data normalization. The purpose of normalization is to limit the preprocessed data to a certain range (such as [0,1] or [-1,1]), thereby eliminating the adverse effects caused by outlier data.

[0100] In detail, the step of performing an inverse Fourier transform on the context features to obtain the detection data of the context features includes: performing an inverse short-time Fourier transform on the context features to obtain the context spatial domain data of the context features; generating context frequency domain data of the context features based on the context spatial domain data; performing an inverse graphical Fourier transform on the context frequency domain data to obtain the context time domain data of the context frequency domain data; and determining the context time domain data as the detection data of the context features.

[0101] In detail, the inverse short-time Fourier transform converts the contextual features from the spectral domain form to the spatial domain form, and the inverse graphical Fourier transform converts the contextual frequency domain data from the frequency domain form to the time domain form.

[0102] In detail, the inverse short-time Fourier transform and the short-time Fourier transform are relative, and the inverse graphical Fourier transform and the graphical Fourier transform are relative.

[0103] S5. Determine abnormal data in the detection data according to a preset detection threshold, and determine abnormal modules in the multi-core processor according to the abnormal data.

[0104] In this embodiment of the invention, the step of determining abnormal data in the detection data according to a preset detection threshold is to compare the detection data with the detection threshold. For example, when the detection data is less than the preset detection threshold, the detection data is normal data. If the detection data is 10% and the preset detection threshold is 5%, then the detection data is abnormal data.

[0105] Furthermore, by determining which processor in the multi-core processor the abnormal data belongs to, the abnormal module in the multi-core processor can be identified; the abnormal module refers to a sub-processor in the multi-core processor whose occupancy is abnormal, and the sub-processor has a corresponding relationship with the program in the medical system.

[0106] Specifically, in medical software for tumor image analysis and diagnosis, multi-threaded processing is often used to accelerate the processing efficiency of tumor images. This requires the use of multi-core processors to improve program speed. For example, a target tumor image is divided into several parts, and tumor analysis is performed on each sub-image to obtain the analysis results of the sub-images. The analysis results of the sub-images are then combined to obtain the analysis results of the target tumor image. Although this method improves the speed of target tumor image analysis, any processor malfunction in any sub-image will cause the sub-image analysis speed to be slow, which in turn will cause the target tumor image analysis speed to be slow. When the abnormal module in the multi-core processor can be quickly detected, the abnormal processing speed of the target tumor image caused by the abnormal processing speed of a sub-image can be resolved. In detail, the target tumor image is input into the tumor image analysis and diagnosis medical software, which divides the target tumor image into multiple sub-images. Different processors in the tumor image analysis and diagnosis medical software are used to analyze the sub-images. At this time, different processors correspond to different multivariate time series with different occupancy rates. The multivariate time series are converted into data using graphical Fourier transform, short-time Fourier transform, and inverse Fourier transform. Assuming that the preset detection threshold is 1, when a certain processor in the tumor image analysis and diagnosis medical software cannot run or runs abnormally, it means that the converted data corresponding to this processor is greater than 1.

[0107] This invention generates an adjacency matrix for a multi-core processor based on the multivariate time series, establishing hidden mutual influence relationships among the various utilization time series of the multi-core processor. The graph neural network-based time series algorithm demonstrates high capability in processing relationships between multivariate time series. Therefore, a graph Fourier transform is performed on the graph signal of the adjacency matrix. By performing a short-time Fourier transform on the spectral domain features, some temporal information is avoided. Compared to the Fourier transform, which can only analyze global features, the short-time Fourier transform is more efficient and less susceptible to the influence of distant sequence values. It can perform noise reduction processing on the local sequence of processor utilization while analyzing the data. On the other hand, if processor utilization data is abnormal, it is often a sudden change. For such abrupt anomalies and the regularity of the sequence, the windowed Fourier algorithm can effectively extract the features of the sequence within each window, identify the periodicity of processor utilization, and analyze local features in a targeted manner. Therefore, this invention proposes a multi-core processor anomaly detection method that can solve the problem of low efficiency in multi-core processor anomaly detection.

[0108] like Figure 4 The diagram shown is a functional block diagram of a multi-core processor anomaly detection device provided in an embodiment of the present invention.

[0109] The multi-core processor anomaly detection device 100 of the present invention can be installed in an electronic device. Depending on the functions implemented, the multi-core processor anomaly detection device 100 may include an adjacency matrix module 101, a spectral domain feature module 102, a frequency domain feature module 103, a detection data module 104, and an anomaly data module 105. The module described in this invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0110] In this embodiment, the functions of each module / unit are as follows:

[0111] The adjacency matrix module 101 is used to obtain a multivariate time series of the occupancy rate sequence of the multi-core processor, and generate the adjacency matrix of the multi-core processor based on the multivariate time series.

[0112] The spectral domain feature module 102 is used to perform a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal.

[0113] The frequency domain feature module 103 is used to perform a short-time Fourier transform on the spectral domain features to obtain the frequency domain features of the spectral domain features.

[0114] The detection data module 104 is used to generate contextual features of the frequency domain features using a preset attention mechanism, and to perform inverse Fourier transform on the contextual features to obtain detection data of the contextual features.

[0115] The abnormal data module 105 is used to determine abnormal data in the detection data according to a preset detection threshold, and to determine the abnormal module in the multi-core processor according to the abnormal data.

[0116] like Figure 5 The diagram shown is a structural schematic of an electronic device that implements a multi-core processor anomaly detection method according to an embodiment of the present invention.

[0117] The electronic device may include a processor 10, a memory 11, a communication bus 12 and a communication interface 13, and may also include a computer program stored in the memory 11 and capable of running on the processor 10, such as a multi-core processor anomaly detection program.

[0118] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., executing multi-core processor anomaly detection programs) and calls data stored in the memory 11 to perform various functions of the electronic device and process data.

[0119] The memory 11 includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of an electronic device, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. Furthermore, the memory 11 can include both internal and external storage units of the electronic device. The memory 11 can be used not only to store application software and various types of data installed on the electronic device, such as the code of a multi-core processor anomaly detection program, but also to temporarily store data that has been output or will be output.

[0120] The communication bus 12 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0121] The communication interface 13 is used for communication between the aforementioned electronic device and other devices, including a network interface and a user interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, Bluetooth interface, etc.), typically used to establish communication connections between the electronic device and other electronic devices. The user interface may be a display, an input unit (such as a keyboard), or, optionally, a standard wired or wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device and to display a visual user interface.

[0122] The figure only shows an electronic device with components. Those skilled in the art will understand that the structure shown in the figure does not constitute a limitation on the electronic device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0123] For example, although not shown, the electronic device may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0124] It should be understood that the embodiments described are for illustrative purposes only and are not limited to this structure in the scope of the patent application.

[0125] The multi-core processor anomaly detection program stored in the memory 11 of the electronic device is a combination of multiple instructions. When run in the processor 10, it can achieve the following:

[0126] Obtain a multivariate time series of the utilization rate sequence of a multi-core processor, and generate an adjacency matrix of the multi-core processor based on the multivariate time series;

[0127] Perform a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal;

[0128] The frequency domain features of the spectral domain features are obtained by performing a short-time Fourier transform on the spectral domain features.

[0129] The contextual features of the frequency domain features are generated using a preset attention mechanism, and the contextual features are subjected to inverse Fourier transform to obtain the detection data of the contextual features.

[0130] Abnormal data in the detection data is determined based on a preset detection threshold, and abnormal modules in the multi-core processor are determined based on the abnormal data.

[0131] Specifically, the specific implementation method of the processor 10 for the above instructions can be referred to the description of the relevant steps in the corresponding embodiment of the accompanying drawings, and will not be repeated here.

[0132] Furthermore, if the modules / units integrated into the electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0133] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0134] Obtain a multivariate time series of the utilization rate sequence of a multi-core processor, and generate an adjacency matrix of the multi-core processor based on the multivariate time series;

[0135] Perform a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal;

[0136] The frequency domain features of the spectral domain features are obtained by performing a short-time Fourier transform on the spectral domain features.

[0137] The contextual features of the frequency domain features are generated using a preset attention mechanism, and the contextual features are subjected to inverse Fourier transform to obtain the detection data of the contextual features.

[0138] Abnormal data in the detection data is determined based on a preset detection threshold, and abnormal modules in the multi-core processor are determined based on the abnormal data.

[0139] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0140] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0141] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0142] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0143] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the invention. No appended diagram markings in the claims should be construed as limiting the scope of the claims.

[0144] The blockchain referred to in this invention is a novel application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and encryption algorithms. Essentially, a blockchain is a decentralized database, a chain of data blocks linked together using cryptographic methods. Each data block contains information about a batch of network transactions, used to verify the validity of the information (anti-counterfeiting) and generate the next block. A blockchain can include an underlying blockchain platform, a platform product service layer, and an application service layer.

[0145] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0146] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a system claim may also be implemented by a single unit or device through software or hardware. The terms "first," "second," etc., are used to indicate names and do not indicate any specific order.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for detecting anomalies in a multi-core processor, characterized in that, The method includes: Obtain a multivariate time series of the utilization rate sequence of a multi-core processor, and generate an adjacency matrix of the multi-core processor based on the multivariate time series; Perform a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal; The frequency domain features of the spectral domain features are obtained by performing a short-time Fourier transform on the spectral domain features. The contextual features of the frequency domain features are generated using a preset attention mechanism, and the contextual features are subjected to inverse Fourier transform to obtain the detection data of the contextual features. Abnormal data in the detection data is determined according to a preset detection threshold, and abnormal modules in the multi-core processor are determined according to the abnormal data. The step of performing a short-time Fourier transform on the spectral domain features to obtain the frequency domain features includes: determining the temporal order of the spectral domain features; performing windowing processing on the spectral domain features according to the temporal order to obtain multiple sub-spectral domain features of the spectral domain features; performing Fourier transform on each sub-spectral domain feature to obtain the sub-frequency domain features of the sub-spectral domain features; and concatenating the sub-frequency domain features according to the temporal order to obtain the frequency domain features of the spectral domain features. The step of generating contextual features of the frequency domain features using a preset attention mechanism includes: generating a feature matrix of the frequency domain features using a preset attention mechanism; generating a multi-head attention matrix of the frequency domain features based on the feature matrix; performing self-attention processing on the frequency domain features to obtain a self-attention matrix of the frequency domain features; and normalizing the multi-head attention matrix and the self-attention matrix to obtain contextual features of the frequency domain features.

2. The multi-core processor anomaly detection method as described in claim 1, characterized in that, The step of generating the adjacency matrix of the multi-core processor based on the multivariate time series includes: The graph nodes of the multi-core processor are generated based on the multivariate time series, and the graph nodes are initialized to obtain the node embedding matrix of the graph nodes. The node embedding matrix is ​​regularized according to the preset activation function hyperparameters and preset linear transformation parameters to obtain the adjacency matrix of the multi-core processor.

3. The multi-core processor anomaly detection method as described in claim 1, characterized in that, The step of performing a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal includes: The spatial data of the adjacency matrix is ​​generated based on the graph signal of the adjacency matrix; A projection basis for the spatial data is generated using a preset Laplace matrix. A graph Fourier transform is then performed on the spatial data based on the projection basis to obtain the spectral domain features of the graph signal.

4. The multi-core processor anomaly detection method as described in claim 1, characterized in that, The step of windowing the spectral features according to the time sequence to obtain multiple sub-spectral features of the spectral features includes: The spectral domain features are windowed using the following window function to obtain multiple sub-spectral domain features of the spectral domain features: in, It is the abscissa of the spectral domain feature. It is the ordinate of the spectral domain feature. These are window function values ​​related to the x-axis and y-axis. It is the standard deviation. It is the natural logarithm.

5. The multi-core processor anomaly detection method according to any one of claims 1 to 4, characterized in that, The step of performing an inverse Fourier transform on the context features to obtain the detection data of the context features includes: The context features are subjected to inverse short-time Fourier transform to obtain the context spatial data of the context features. The contextual spatial data is used to generate contextual frequency domain data of the contextual features. An inverse graphical Fourier transform is performed on the contextual frequency domain data to obtain contextual time domain data of the contextual frequency domain data. The contextual time domain data is then determined as the detection data of the contextual features.

6. A multi-core processor anomaly detection device, used to implement the multi-core processor anomaly detection method as described in any one of claims 1 to 5, characterized in that, The device includes: The adjacency matrix module is used to obtain a multivariate time series of the utilization rate sequence of the multi-core processor, and generate the adjacency matrix of the multi-core processor based on the multivariate time series. The spectral domain feature module is used to perform a graph Fourier transform on the graph signal of the adjacency matrix to obtain the spectral domain features of the graph signal. The frequency domain feature module is used to perform a short-time Fourier transform on the spectral domain features to obtain the frequency domain features of the spectral domain features; The detection data module is used to generate contextual features of the frequency domain features using a preset attention mechanism, and to perform inverse Fourier transform on the contextual features to obtain detection data of the contextual features. An abnormal data module is used to determine abnormal data in the detection data according to a preset detection threshold, and to determine the abnormal module in the multi-core processor according to the abnormal data.

7. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the multi-core processor anomaly detection method as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the multi-core processor anomaly detection method as described in any one of claims 1 to 5.

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