Chip register testing method and device, electronic equipment and storage medium

Abstract

The application provides a chip register test method and device, electronic equipment and storage medium. The method comprises the following steps: obtaining the bit number and starting address of a to-be-tested register, and a to-be-tested value; calculating the test number of the to-be-tested register according to the bit number of the to-be-tested register and the bit number of the to-be-tested value; performing a zero padding operation on the to-be-tested value according to the bit number of the to-be-tested register, the bit number of the to-be-tested value and the test number of the to-be-tested register, to obtain an initial to-be-tested value; splitting the initial to-be-tested value into at least one target to-be-tested value with the same bit number as the to-be-tested register; and testing the to-be-tested registers with the same number as the test number starting from the starting address through the target to-be-tested value. Through the method, multiple chip registers can be tested at the same time, so that the test efficiency of the chip register is improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically, to methods, apparatus, electronic devices, and storage media for testing chip registers. Background Technology

[0002] With the rapid development of the semiconductor chip industry, higher demands have been placed on semiconductor testing work, which is located downstream in the semiconductor chip industry chain. In the traditional semiconductor testing process, one important testing step is to test the chip registers. The general testing method is to write a binary number with the same number of bits as the register into a user-specified register, and then read it to complete the register test.

[0003] However, when testing registers using the above testing method, users can only test one register at a time, resulting in low testing efficiency. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a method, apparatus, electronic device and storage medium for testing chip registers, which can test multiple chip registers simultaneously to improve the testing efficiency of chip registers.

[0005] In a first aspect, embodiments of this application provide a method for testing chip registers, the method comprising:

[0006] Obtain the number of bits and starting address of the register to be tested, as well as the value to be tested;

[0007] Calculate the number of tests for the register to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested.

[0008] Based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests in the register to be tested, zero-padding is performed on the value to be tested to obtain the initial value to be tested.

[0009] The initial value to be tested is split into at least one target value to be tested, which has the same number of bits as the register to be tested.

[0010] Using the target value to be tested, test the same number of registers as the number of tests, starting from the starting address.

[0011] In one possible implementation, the number of tests for the register to be tested is calculated based on the number of bits in the register to be tested and the number of bits in the value to be tested, including:

[0012] The ratio of the number of bits in the value to be tested to the number of bits in the register to be tested is used as the initial number of tests.

[0013] If the initial number of tests is an integer, then the initial number of tests is set as the target number of tests;

[0014] If the initial number of tests is not an integer, then the initial number of tests will be rounded up to obtain the target number of tests.

[0015] In one possible implementation, the value to be tested is padded with zeros according to the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests performed on the register to be tested, to obtain an initial value to be tested, including:

[0016] Calculate the number of bits to be added based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of registers to be tested.

[0017] Add the same number of zeros to the beginning of the value to be tested to obtain the initial value to be tested.

[0018] In one possible implementation, the number of bits to be supplemented is calculated based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests conducted on the register to be tested, including:

[0019] The quantity to be replenished can be calculated using the following formula:

[0020] zeroNum=n*dataWidth-binartValue.length;

[0021] Where zeroNum is the number to be supplemented, n is the number of registers to be tested, dataWidth is the number of bits in the register to be tested, and binaryValue.length is the number of bits in the value to be tested.

[0022] In one possible implementation, splitting the initial test value into at least one target test value with the same number of bits as the register to be tested includes:

[0023] The initial test value is split into target test values ​​with the same number of bits as the test register, in order from left to right.

[0024] Secondly, embodiments of this application also provide a testing apparatus for chip registers, the testing apparatus for chip registers comprising:

[0025] The acquisition module is used to acquire the number of bits and starting address of the register to be tested, as well as the value to be tested;

[0026] The calculation module is used to calculate the number of tests for the register to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested.

[0027] The zero-padding module pads the value to be tested with zeros based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests to be performed on the register to be tested, thus obtaining the initial value to be tested.

[0028] The splitting module is used to split the initial value to be tested into at least one target value to be tested with the same number of bits as the register to be tested;

[0029] The test module is used to test a number of registers, starting from the starting address and matching the number of tests, using the target value to be tested.

[0030] In one possible implementation, the calculation module is specifically used to determine the initial test quantity by the ratio of the number of bits of the value to be tested to the number of bits of the register to be tested; if the initial test quantity is an integer, then the initial test quantity is determined as the target test quantity; if the initial test quantity is not an integer, then the initial test quantity is further processed to obtain the target test quantity.

[0031] In one possible implementation, the zero-padding module is specifically used to calculate the amount to be padded based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests in the register to be tested; and to padded the value to be tested with the same number of zeros as the amount to be padded to obtain the initial value to be tested.

[0032] In one possible implementation, the zero-padding module is also used to calculate the quantity to be padded using the following formula:

[0033] zeroNum=n*dataWidth-binaryValue.length;

[0034] Where zeroNum is the number to be supplemented, n is the number of registers to be tested, dataWidth is the number of bits in the register to be tested, and binaryValue.length is the number of bits in the value to be tested.

[0035] In one possible implementation, a splitting module is specifically used to split the initial test value into target test values ​​with the same number of bits as the test register, in a left-to-right order.

[0036] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a storage medium, and a bus. The storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the test method for the chip register of any of the first aspects.

[0037] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when run by a processor, executes the steps of the test method for the chip register of any of the first aspects.

[0038] This application provides a method, apparatus, electronic device, and storage medium for testing chip registers. The method includes: obtaining the number of bits and starting address of the register to be tested, and the value to be tested; calculating the number of registers to be tested based on the number of bits of the register to be tested and the number of bits of the value to be tested; padding the value to be tested with zeros based on the number of bits of the register to be tested, the number of bits of the value to be tested, and the number of registers to be tested, to obtain an initial value to be tested; splitting the initial value to be tested into at least one target value to be tested with the same number of bits as the register to be tested; and testing the number of registers to be tested, starting from the starting address, using the target value to be tested. This application improves the testing efficiency of chip registers by simultaneously testing multiple chip registers by splitting the zero-padded value to be tested into at least one target value with the same number of bits as the register to be tested, and then testing the number of registers to be tested, starting from the starting address. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating a chip register testing method provided in an embodiment of this application is shown;

[0041] Figure 2 A flowchart illustrating another chip register testing method provided in an embodiment of this application is shown;

[0042] Figure 3 This illustration shows a schematic diagram of the structure of a chip register testing device provided in an embodiment of this application;

[0043] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0045] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0046] To enable those skilled in the art to utilize the content of this application, and in conjunction with the specific application scenario of "chip testing technology," the following implementation methods are provided. For those skilled in the art, the general principles defined herein can be applied to other embodiments and application scenarios without departing from the spirit and scope of this application. Although this application is primarily described within the "chip testing technology field," it should be understood that this is merely an exemplary embodiment.

[0047] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0048] The following is a detailed description of a chip register testing method provided in the embodiments of this application.

[0049] Reference Figure 1 The diagram shown is a flowchart illustrating a chip register testing method provided in an embodiment of this application. The specific execution process of this chip register testing method is as follows:

[0050] S101. Obtain the number of bits and starting address of the register to be tested, as well as the value to be tested.

[0051] S102. Calculate the number of tests for the register to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested.

[0052] S103. Based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests in the register to be tested, zero-padding is performed on the value to be tested to obtain the initial value to be tested.

[0053] S104. Split the initial test value into at least one target test value with the same number of bits as the test register.

[0054] S105. Using the target value to be tested, test the number of registers to be tested, starting from the starting address, which is the same as the number of registers to be tested.

[0055] This application provides a method for testing chip registers. The method includes: obtaining the number of bits and starting address of the register to be tested, and the value to be tested; calculating the number of registers to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested; padding the value to be tested with zeros based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of registers to be tested, to obtain an initial value to be tested; splitting the initial value to be tested into at least one target value to be tested with the same number of bits as the register to be tested; and testing the number of registers to be tested, starting from the starting address, using the target values ​​to be tested. This application, by splitting the zero-padded value to be tested into at least one target value to be tested with the same number of bits as the register to be tested, and then testing the number of registers to be tested, starting from the starting address, can simultaneously test multiple chip registers, thereby improving the testing efficiency of chip registers.

[0056] The exemplary steps of the embodiments of this application are described below:

[0057] S101. Obtain the number of bits and starting address of the register to be tested, as well as the value to be tested.

[0058] In this embodiment, the starting address of the register to be tested, the value to be tested, and the number system type corresponding to the value to be tested are obtained from the user-sent register; the number of bits corresponding to the register to be tested are obtained from the register bit storage table; the register bit storage table stores the register to be tested and its corresponding number of bits; if the number system type is binary, the value to be tested is used as the final value to be tested; if the number system type is not binary, the value to be tested is converted into a binary value to obtain the final value to be tested.

[0059] The register to be tested refers to the register of the semiconductor chip that needs to be tested. The register to be tested can be 8-bit, 16-bit, or 32-bit, etc. The starting address of the register to be tested is the address of the first register to be tested among all the registers to be tested, and the value to be tested is the value used to test the register to be tested. The number system of the value to be tested can be binary, decimal, or hexadecimal, etc.

[0060] S102. Calculate the number of tests for the register to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested.

[0061] In this application's implementation, the number of registers to be tested refers to the number of registers that need to be tested, determined based on the number of bits in the user-inputted value to be tested. It also represents the number of target values ​​to be tested obtained after splitting the value to be tested. The number of bits in the value to be tested is its length.

[0062] If the value to be tested is 1111, then the number of digits in the value to be tested is 4.

[0063] Specifically, the ratio of the number of bits in the value to be tested to the number of bits in the register to be tested is determined as the initial test number; if the initial test number is an integer, it is determined as the target test number; if the initial test number is not an integer, it is further processed to obtain the target test number.

[0064] S103. Based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests in the register to be tested, zero-padding is performed on the value to be tested to obtain the initial value to be tested.

[0065] In this embodiment, padding the value to be tested with zeros is mainly to ensure that the number of bits in the initial value to be tested after padding is a multiple of the number of bits in the register to be tested; this multiple is an integer; the purpose of doing so is to facilitate subsequent splitting.

[0066] Specifically, the number of bits to be supplemented is calculated based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of registers to be tested.

[0067] In the embodiments of this application, the quantity to be supplemented refers to the number of zeros that need to be added to the value to be tested.

[0068] Here, the quantity to be replenished is calculated using the following formula:

[0069] zeroNum=n*dataWidth-binaryValue.length;

[0070] Where zeroNum is the number to be supplemented, n is the number of registers to be tested, dataWidth is the number of bits in the register to be tested, and binaryValue.length is the number of bits in the value to be tested.

[0071] For example, if the number of bits in the register to be tested is 16, the number of tests in the register to be tested is 2, the number of bits in the value to be tested is 30, and the number of bits to be supplemented is 12*16-30=2.

[0072] Specifically, the number of zeros to be added before the value to be tested is equal to the number of zeros to be added, thus obtaining the initial value to be tested.

[0073] For example, if the value to be tested is 101101110011011001001100111010, and the number to be supplemented is 2, then the initial value to be tested after supplementation is 00101101110011011001001100111010.

[0074] S104. Split the initial test value into at least one target test value with the same number of bits as the test register.

[0075] In this embodiment of the application, the number of target test values ​​obtained by splitting is the same as the number of test values ​​of the test register.

[0076] Specifically, the initial test value is split into target test values ​​with the same number of bits as the test register, in order from left to right.

[0077] For example, if the initial value to be tested is 00101101110011011001001100111010, and the number of bits in the register to be tested is 16, then the target values ​​to be tested include 0010110111001101 and 1001001100111010.

[0078] S105. Using the target value to be tested, test the number of registers to be tested, starting from the starting address, which is the same as the number of registers to be tested.

[0079] In this embodiment, each target test value is sequentially stored into each test register to obtain the stored content of each test register; after storage, the content of each test register is read to obtain the read content of each test register; if the stored content of the test register is the same as the read content, the test result is qualified; if the stored content of the test register is the same as the read content, the test result is unqualified.

[0080] For example, the target test values ​​include 0010110111001101 and 1001001100111010. If the starting address is n and the number of tests is the same (2), then the test registers include the test register at address n and the test register at address n+1. 0010110111001101 is stored in the test register at address n, and 1001001100111010 is stored in the test register at address n+1. After storage, the contents of the test registers at addresses n and n+1 are read. If the stored content of the test register is the same as the read content, the test result is qualified; otherwise, the test result is unqualified.

[0081] Reference Figure 2 The diagram shown is a flowchart illustrating a chip register testing method provided in an embodiment of this application. This method calculates the number of tests required for the register to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested. The exemplary steps of this embodiment are described below:

[0082] S201. The ratio of the number of bits in the value to be tested to the number of bits in the register to be tested is determined as the initial number of tests.

[0083] In this embodiment of the application, the initial test number is used to characterize the number of partitions that the value to be tested can be divided into, which is the same as the number of bits in the register to be tested. The number of partitions obtained here can be an integer or a non-integer.

[0084] Example 1: If the number of bits in the value to be tested is 30 and the number of bits in the register to be tested is 16, then the initial number of tests is 30 / 16 = 1.875.

[0085] Example 2: If the number of bits in the value to be tested is 32 and the number of bits in the register to be tested is 16, then the initial number of tests is 32 / 16 = 2.

[0086] S202. If the initial number of tests is an integer, then the initial number of tests shall be determined as the target number of tests.

[0087] In this embodiment, if the initial number of tests is an integer, it means that the value to be tested can be completely divided into at least one value with the same number of bits as the register to be tested. For example, if the initial number of tests is 2, then the target number of tests is 2.

[0088] S203. If the initial test quantity is not an integer, then the initial test quantity is rounded up to obtain the target test quantity.

[0089] In this embodiment, if the initial test number is an integer, it means that the value to be tested cannot be completely divided into at least one value with the same number of bits as the register to be tested. For example, if the initial test number is 1.875, then rounding up the initial test number results in a target test number of 2; if the initial test number is 3.22, then rounding up the initial test number results in a target test number of 4.

[0090] This application provides another method for testing chip registers. The method includes determining the initial test quantity as the ratio of the number of bits in the value to be tested to the number of bits in the register to be tested; if the initial test quantity is an integer, then the initial test quantity is determined as the target test quantity; if the initial test quantity is not an integer, then the initial test quantity is further processed to obtain the target test quantity. The method of this application can determine the target test quantity.

[0091] Based on the same inventive concept, this application also provides a chip register testing device corresponding to the chip register testing method. Since the principle of the device in this application is similar to the chip register testing method described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0092] Reference Figure 3 The diagram shown is a schematic of a chip register testing apparatus provided in an embodiment of this application. The chip register testing apparatus includes:

[0093] The acquisition module 301 is used to acquire the number of bits and the starting address of the register to be tested, as well as the value to be tested;

[0094] The calculation module 302 is used to calculate the number of tests for the register to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested.

[0095] The zero-padding module 303 performs zero-padding on the value to be tested based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests in the register to be tested, to obtain the initial value to be tested.

[0096] The splitting module 304 is used to split the initial test value into at least one target test value with the same number of bits as the test register;

[0097] Test module 305 is used to test a number of registers to be tested, starting from the starting address and matching the number of tests, using the target value to be tested.

[0098] In one possible implementation, the calculation module 302 is specifically used to determine the initial test quantity by the ratio of the number of bits of the value to be tested to the number of bits of the register to be tested; if the initial test quantity is an integer, the initial test quantity is determined as the target test quantity; if the initial test quantity is not an integer, the initial test quantity is further processed to obtain the target test quantity.

[0099] In one possible implementation, the zero-padding module 303 is specifically used to calculate the amount to be padded based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests in the register to be tested; and to padded the value to be tested with the same number of zeros as the amount to be padded to obtain the initial value to be tested.

[0100] In one possible implementation, the zero-padding module 303 is further configured to calculate the quantity to be padded using the following formula:

[0101] zeroNum=n*dataWidth-binaryValue.length;

[0102] Where zeroNum is the number to be supplemented, n is the number of registers to be tested, dataWidth is the number of bits in the register to be tested, and binaryValue.length is the number of bits in the value to be tested.

[0103] In one possible implementation, the splitting module 304 is specifically used to split the initial test value into target test values ​​with the same number of bits as the test register in a left-to-right order.

[0104] This application provides a chip register testing apparatus, comprising: an acquisition module 301 for acquiring the number of bits and starting address of the register to be tested, and the value to be tested; a calculation module 302 for calculating the number of registers to be tested based on the number of bits of the register to be tested and the number of bits of the value to be tested; a zero-padding module 303 for padding the value to be tested with zeros based on the number of bits of the register to be tested, the number of bits of the value to be tested, and the number of registers to be tested, to obtain an initial value to be tested; a splitting module 304 for splitting the initial value to be tested into at least one target value to be tested with the same number of bits as the register to be tested; and a testing module 305 for testing the number of registers to be tested, starting from the starting address, using the target value to be tested. This application improves the testing efficiency of chip registers by testing multiple chip registers simultaneously using at least one target value to be tested, split from the zero-padding value, with the same number of bits as the register to be tested, and then testing the number of registers to be tested, starting from the starting address.

[0105] like Figure 4 As shown in the embodiment of this application, an electronic device 400 includes a processor 401, a memory 402, and a bus. The memory 402 stores machine-readable instructions that can be executed by the processor 401. When the electronic device is running, the processor 401 communicates with the memory 402 through the bus. The processor 401 executes the machine-readable instructions to perform the steps of the test method for the chip register described above.

[0106] Specifically, the memory 402 and processor 401 mentioned above can be general-purpose memory and processor, without any specific limitations. When the processor 401 runs the computer program stored in the memory 402, it can execute the test method of the chip registers mentioned above.

[0107] Corresponding to the above-described chip register testing method, this application embodiment also provides a computer-readable storage medium storing a computer program, which is executed by a processor to perform the steps of the above-described chip register testing method.

[0108] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0109] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0110] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0111] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the information processing methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0112] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for testing chip registers, characterized in that, The testing method for the chip registers includes: Obtain the number of bits and starting address of the register to be tested, as well as the value to be tested; The number of tests for the register to be tested is calculated based on the number of bits in the register to be tested and the number of bits in the value to be tested. Based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests performed on the register to be tested, zero-padding is performed on the value to be tested to obtain the initial value to be tested. The initial test value is split into at least one target test value with the same number of bits as the test register; Using the target test value, test the same number of registers as the test quantity, starting from the starting address; The step of calculating the number of tests for the register to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested includes: determining the initial number of tests by the ratio of the number of bits in the value to the number of bits in the register to be tested; if the initial number of tests is an integer, then determining the initial number of tests as the target number of tests; if the initial number of tests is not an integer, then performing a further operation on the initial number of tests to obtain the target number of tests. The step of padding the value to be tested with zeros based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests in the register to be tested to obtain an initial value to be tested includes: calculating the amount to be padded based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests in the register to be tested; and padding the value to be tested with zeros equal to the amount to be padded to obtain the initial value to be tested. The step of calculating the quantity to be supplemented based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests conducted on the register to be tested includes: calculating the quantity to be supplemented using the following formula: ； in, The quantity to be replenished. The number of registers to be tested. The number of bits in the register to be tested. The number of digits in the value to be tested.

2. The test method for chip registers according to claim 1, characterized in that, The step of splitting the initial test value into at least one target test value with the same number of bits as the test register includes: The initial test value is sequentially split into target test values ​​with the same number of bits as the test register, from left to right.

3. A testing device for chip registers, characterized in that, The testing device for the chip register includes: The acquisition module is used to acquire the number of bits and starting address of the register to be tested, as well as the value to be tested; The calculation module is used to calculate the number of tests for the register to be tested based on the number of bits in the register to be tested and the number of bits in the value to be tested. The zero-padding module performs zero-padding on the value to be tested based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests performed on the register to be tested, to obtain the initial value to be tested. A splitting module is used to split the initial test value into at least one target test value with the same number of bits as the test register; The testing module is used to test a number of registers to be tested, starting from the starting address and equal to the number of tests, using the target test value. Specifically, the calculation module is used to determine the initial test quantity by the ratio of the number of bits in the value to be tested to the number of bits in the register to be tested; if the initial test quantity is an integer, then the initial test quantity is determined as the target test quantity; if the initial test quantity is not an integer, then the initial test quantity is further processed to obtain the target test quantity. Specifically, the zero-padding module is used to calculate the amount to be padded based on the number of bits in the register to be tested, the number of bits in the value to be tested, and the number of tests conducted on the register to be tested; and to pad the value to be tested with zeros equal to the number to be padded to obtain the initial value to be tested. The zero-padding module is further configured to calculate the quantity to be padded using the following formula: ； in, The quantity to be replenished. The number of registers to be tested. The number of bits in the register to be tested. The number of digits in the value to be tested.

4. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the chip register testing method as described in claim 1 or 2.

5. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the chip register testing method as described in claim 1 or 2.

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