Method, apparatus and electronic device for data transmission between central processing units

Abstract

This disclosure provides a method, apparatus, and electronic device for data transmission between central processing units (CPUs), relating to the field of communication technology. The specific steps are: receiving target data sent by a first application layer; creating a first socket channel in the kernel according to a preset socket; transmitting the target data to a pre-set first cache space via the first socket channel; determining a target CPU and triggering an interrupt signal to the target CPU; and receiving activation information sent by the target CPU and transmitting the target data to the target CPU according to the activation information. This disclosure, by creating a socket channel, enables the determination of whether the target data can be sent to the target CPU based on activation information, avoiding insufficient cache in the target CPU that would prevent it from carrying the target data, thus improving transmission efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a method, apparatus and electronic device for data transmission between CPUs. Background Technology

[0002] In related technologies, large-scale application systems typically contain thousands of CPUs (Central Processing Units), each running an operating system and various applications. Communication may occur between these operating systems and between these applications. In existing technologies, when multiple CPUs communicate, a cache space needs to be set up for each CPU. When sending a data packet, the sending CPU writes the data packet to be sent into the receiving CPU's cache space, and then generates an interrupt signal by setting the cache space, which is sent to the receiving CPU. Upon receiving the interrupt signal, the receiving CPU retrieves the data packet from its cache space. However, currently, the receiving CPU's cache space writes data quickly but reads data slowly, and the sending CPU cannot know the progress of reading data from the receiving CPU's cache space. This can lead to the receiving CPU's cache space being unable to hold the data packet, resulting in data loss and impacting system efficiency. Summary of the Invention

[0003] This disclosure provides a method, apparatus, and electronic device for inter-CPU data transmission, to at least solve the problem in related technologies where the sending CPU cannot know the progress of data reading from the receiving CPU's cache space. The technical solution of this disclosure is as follows:

[0004] According to a first aspect of the present disclosure, a method for inter-CPU data transmission is provided, applied to a main CPU, comprising:

[0005] Receive target data sent by the first application layer;

[0006] The first socket channel is created in the kernel according to the preset socket;

[0007] The target data is transmitted to a pre-set first buffer space according to the first Socket channel;

[0008] Identify the target CPU, trigger an interrupt signal to the target CPU, and transmit the target data to the target CPU based on the activation information sent by the target CPU.

[0009] Optionally, transmitting the target data to the target CPU includes:

[0010] Receive the free cache space size identifier sent by the target CPU;

[0011] A first write pointer and a first read pointer are created in the first cache space according to the free cache space size identifier;

[0012] The target data is sent from the first cache space to the second cache space according to the target data, wherein the second cache space belongs to the target CPU.

[0013] Optionally, sending the target data to the second cache space based on the space occupied by the target data in the first cache space includes:

[0014] If the target data occupies less than or equal to the free cache space between the first write pointer and the first read pointer in the first cache space, then the first write pointer position information is sent to the target CPU.

[0015] If the target data occupies more space in the first cache space than the free cache space between the first write pointer and the first read pointer, then the system enters a standby state.

[0016] Optionally, the method further includes:

[0017] The system receives the position update information of the second read pointer sent by the target CPU, and updates the first read pointer according to the position update information of the second read pointer.

[0018] Optionally, transmitting the target data to the target CPU based on the activation information includes:

[0019] In response to receiving the activation information sent by the target CPU, target data is sent to the second cache space.

[0020] According to a second aspect of the present disclosure, a method for inter-CPU data transmission is provided, applied to a target CPU, comprising:

[0021] A second socket channel is established in the kernel according to the preset socket;

[0022] In response to the interrupt signal of the main CPU, the system receives the target data sent by the main CPU and transfers the target data to the second cache space, wherein the second cache space belongs to the target CPU.

[0023] The target data in the second cache space is sent to the second application layer through the second Socket channel, wherein the second application layer belongs to the target CPU.

[0024] Optionally, the method further includes:

[0025] The system sends a free cache space size identifier to the main CPU based on the free cache space in the second cache space.

[0026] Optionally, the method further includes:

[0027] Receive the first write pointer position information sent by the main CPU, and update the second write pointer according to the first write pointer position information.

[0028] Optionally, after sending the target data in the second cache space to the second application layer via the second Socket channel, the method further includes:

[0029] The position update information of the second read pointer is sent to the main CPU, and the shadow pointer of the second read pointer is recorded, wherein the second write pointer and the second read pointer belong to the second cache space.

[0030] Optionally, receiving the target data sent by the main CPU and transferring the target data to the second cache space includes:

[0031] Obtain the free cache space corresponding to the second read pointer and the second write pointer, and the occupied cache space between the shadow pointer and the second write pointer;

[0032] If the free cache space corresponding to the second read pointer and the second write pointer is greater than or equal to the occupied cache space, then an activation message is sent to the main CPU and the target data is received.

[0033] If the free cache space corresponding to the second read pointer and the second write pointer is less than the occupied cache space, then no activation information is sent to the main CPU.

[0034] According to a third aspect of the present disclosure, an apparatus for inter-CPU data transmission is provided, applied to a main CPU, comprising:

[0035] The receiving module is used to receive target data sent by the first application layer;

[0036] The first channel creation module is used to create the first socket channel in the kernel based on the preset socket.

[0037] The first transmission module is used to transmit the target data to a pre-set first buffer space according to the first Socket channel;

[0038] The cross-CPU transmission module identifies the target CPU, triggers an interrupt signal to the target CPU, receives activation information sent by the target CPU, and transmits the target data to the target CPU according to the activation information.

[0039] Optionally, the cross-CPU transmission module includes:

[0040] The identification receiving submodule is used to receive the free cache space size identifier sent by the target CPU;

[0041] The pointer creation submodule is used to create a first write pointer and a first read pointer in the first cache space according to the free cache space size identifier;

[0042] The pointer position sending submodule is used to send first write pointer position information to the second cache space in the space occupied by the first cache space according to the target data, wherein the second cache space belongs to the target CPU.

[0043] Optionally, the pointer position sending submodule includes:

[0044] If the target data occupies less than or equal to the free cache space between the first write pointer and the first read pointer in the first cache space, the first transmission unit sends the first write pointer position information to the target CPU.

[0045] The second transmission unit enters a standby state if the space occupied by the target data in the first cache space is greater than the free cache space between the first write pointer and the first read pointer.

[0046] Optionally, the device further includes:

[0047] The pointer update module is used to receive the position update information of the second read pointer sent by the target CPU, and update the first read pointer according to the position update information of the second read pointer.

[0048] Optionally, the device further includes:

[0049] The target data transmission submodule is used to send target data to the second cache space in response to receiving activation information sent by the target CPU.

[0050] According to a fourth aspect of the present disclosure, an apparatus for inter-CPU data transmission is provided, applied to a target CPU, comprising:

[0051] The second channel creation module is used to establish a second socket channel in the kernel based on a preset socket.

[0052] The data receiving module, in response to the interrupt signal of the main CPU, receives the target data sent by the main CPU and transmits the target data to the second cache space, wherein the second cache space belongs to the target CPU;

[0053] The second transmission module sends the target data in the second cache space to the second application layer through the second Socket channel, wherein the second application layer belongs to the target CPU.

[0054] Optionally, the device further includes:

[0055] The free space identifier sending module is used to send a free cache space size identifier to the main CPU based on the free cache space in the second cache space.

[0056] Optionally, the device further includes:

[0057] The pointer position update module is used to receive the first write pointer position information sent by the main CPU and update the second write pointer according to the first write pointer position information.

[0058] Optionally, the second transmission module includes:

[0059] The pointer position sending submodule is used to send the position update information of the second read pointer to the main CPU and record the shadow pointer of the second read pointer, wherein the second write pointer and the second read pointer belong to the second cache space.

[0060] Optionally, the data receiving module includes:

[0061] The space acquisition submodule is used to acquire the free cache space corresponding to the second read pointer and the second write pointer, and the occupied cache space between the shadow pointer and the second write pointer;

[0062] The first activation information sending submodule sends activation information to the main CPU and receives the target data if the free cache space corresponding to the second read pointer and the second write pointer is greater than or equal to the occupied cache space.

[0063] If the free cache space corresponding to the second read pointer and the second write pointer is less than the occupied cache space, the second activation information sending submodule will not send activation information to the main CPU.

[0064] According to a fifth aspect of the present disclosure, an electronic device is provided, characterized in that it comprises:

[0065] processor;

[0066] Memory used to store the processor's executable instructions;

[0067] The processor is configured to execute the instructions to implement the inter-CPU data transfer method as described in any one of the first aspects above or the inter-CPU data transfer method as described in any one of the second aspects above.

[0068] According to a sixth aspect of the present disclosure, a computer-readable storage medium is provided, wherein when instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform an inter-CPU data transfer method as described in any one of the first aspects above or an inter-CPU data transfer method as described in any one of the second aspects above.

[0069] According to a seventh aspect of the present disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method as described in any one of the first aspects above or the method as described in any one of the second aspects above.

[0070] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects:

[0071] This disclosure, by creating a Socket channel, enables the determination of whether the target data can be sent to the target CPU based on the activation information, thereby avoiding the inability of the target CPU to carry the target data due to insufficient cache and improving transmission efficiency.

[0072] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0073] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0074] Figure 1 This is a flowchart illustrating a method for data transfer between CPUs according to an exemplary embodiment.

[0075] Figure 2 This is a flowchart illustrating a method for data transfer between CPUs according to an exemplary embodiment.

[0076] Figure 3 This is a flowchart illustrating a method for data transfer between CPUs according to an exemplary embodiment.

[0077] Figure 4 This is a flowchart illustrating a method for data transfer between CPUs according to an exemplary embodiment.

[0078] Figure 5 This is a system architecture diagram used to implement data transfer between CPUs.

[0079] Figure 6 This is a flowchart illustrating the DGRAM communication method implemented using Socket interface functions.

[0080] Figure 7 This is a flowchart illustrating the STREAM communication method implemented using Socket interface functions.

[0081] Figure 8 This is a flowchart of data transfer between CPUs in related technologies.

[0082] Figure 9 This is a flowchart of inter-CPU data transfer according to an exemplary embodiment.

[0083] Figure 10 This is a block diagram illustrating an apparatus for inter-CPU data transfer according to an exemplary embodiment.

[0084] Figure 11 This is a block diagram illustrating an apparatus for inter-CPU data transfer according to an exemplary embodiment.

[0085] Figure 12 This is a schematic block diagram of an example electronic device for implementing embodiments of the present disclosure. Detailed Implementation

[0086] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0087] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0088] In related technologies, large-scale application systems typically contain thousands of CPUs (Central Processing Units), each running an operating system and various applications. Communication may occur between these operating systems and between these applications. In existing technologies, when multiple CPUs communicate, a cache space needs to be set up for each CPU. When sending a data packet, the sending CPU writes the data packet to be sent into the receiving CPU's cache space, and then generates an interrupt signal by setting the cache space, which is sent to the receiving CPU. Upon receiving the interrupt signal, the receiving CPU retrieves the data packet from its cache space. However, currently, the receiving CPU's cache space writes data quickly but reads data slowly, and the sending CPU cannot know the progress of reading data from the receiving CPU's cache space. This can lead to the receiving CPU's cache space being unable to hold the data packet, resulting in data loss and impacting system efficiency.

[0089] Furthermore, when applications communicate between multiple CPUs, commands in the sending CPU need to be transmitted from the sending application to the sending kernel. The sending kernel then transmits the commands to the receiving CPU's kernel, which in turn transmits them to the receiving application. Since different interfaces are required for different commands during communication between the kernel and the application, multiple sets of interfaces need to be set up between the application and the interfaces when CPUs need to transmit various command data. This increases the complexity of the CPU's internal interface configuration.

[0090] Figure 1 This is a flowchart illustrating a method for inter-CPU data transfer according to an exemplary embodiment, such as... Figure 1 As shown, the method is used in the main CPU and includes the following steps.

[0091] Step 101: Receive the target data sent by the first application layer.

[0092] In this embodiment, the first application (APP) layer belongs to the main CPU, and the target CPU also includes a second application layer. One or more applications are running in both the first and second application layers. When an application in the first application layer needs to transmit data or commands (i.e., target data) to an application in the second application layer, the main CPU receives the target data. The main CPU and the target CPU belong to the same System on Chip (SoC). In a narrow sense, SoC is the core chip integration of an information system, integrating key system components onto a single chip. In a broader sense, SoC is a micro-system; if the CPU is the brain, then SoC is a system including the brain, heart, eyes, and hands. Related technologies generally define SoC as integrating a microprocessor, analog IP cores, digital IP cores, and memory or off-chip memory control interfaces onto a single chip; it is typically a customized or application-specific standard product.

[0093] Step 102: Create the first socket channel in the kernel according to the preset socket.

[0094] In this embodiment of the application, in the field of computer communication, a socket is a convention or method for communication between computers. Through the socket convention, a computer can receive data from other computers and send data to other computers. Socket originated from the Unix operating system, which treats everything on the computer as a file, and can operate on the file through reading and writing.

[0095] The main CPU described in this embodiment comprises three layers: an application layer, a kernel layer, and a network data exchange layer (Protocol). Data transmission between the main CPU and the target CPU is based on the Open Asymmetric Multiprocessing (OpenAMP) framework. The OpenAMP interface is located in the network data exchange layer. Typically, in an AMP (Asymmetric Multiprocessing) configuration, different software environments run on different processing cores, executing their respective code programs. These cores cooperate to improve processor performance. In an AMP system, the main CPU is usually the CPU that starts first and is primarily responsible for managing other CPUs and their software environments. The target CPU is the CPU controlled by the main CPU. The main software environment typically needs to manage remote cores and schedule tasks. When computational tasks need to be allocated, it selectively drives remote software environments on remote kernels and communicates task information. The OpenAMP software framework provides the necessary API functions for developing AMP systems. Cross-CPU communication can be achieved by developing OpenAMP code.

[0096] This application embodiment utilizes OpenAMP to develop multiple Socket interface functions based on the Socket concept, implementing the functionality of the required Socket modules. These include functions such as `socket()` for creating a Socket channel, `bind()` for binding a Socket to a port number, `listen()` for listening to the port number corresponding to the Socket, and `accept()` for receiving connection requests from clients. The `socket()` function creates the first Socket channel within the main CPU kernel. The first application layer within the main CPU can call these Socket interface functions to transmit the target data to the underlying layer of the main CPU, i.e., the network data exchange layer, through the first Socket channel. The network data exchange layer establishes rules, standards, or conventions for data exchange between different CPUs. It is used for communication between entities in different systems. For two entities to communicate, they must share a common language, and they must adhere to certain rules regarding the content, method, and timing of communication; these rules constitute the protocol. In other words, the network data exchange layer includes a set of rules controlling data exchange between two entities.

[0097] In one possible embodiment, the data transmission method for communication using a Socket channel includes:

[0098] 1) SOCK_STREAM: Connection-oriented data transmission method. Data can reach another CPU accurately. If it is corrupted or lost, it can be retransmitted, but the efficiency is relatively slow. The Hypertext Transfer Protocol (HTTP) uses SOCK_STREAM to transmit data because it is necessary to ensure the correctness of the data; otherwise, web pages cannot be parsed correctly.

[0099] 2) SOCK_DGRAM: Connectionless data transfer mode. The CPU is only responsible for transmitting data and does not perform data verification. If the data is corrupted during transmission or fails to reach the other CPU, there is no way to recover it. In other words, data cannot be retransmitted if errors occur. Because SOCK_DGRAM performs less verification work, it is more efficient than SOCK_STREAM.

[0100] This disclosure, by creating a Socket channel, enables the determination of whether the target data can be sent to the target CPU based on activation information, avoiding insufficient cache in the target CPU that would prevent it from carrying the target data, thus improving transmission efficiency. Step 103: The target data is transmitted to a pre-set first cache space according to the first Socket channel.

[0101] In this embodiment of the application, the main CPU allocates a portion of its memory as the first cache space to store the target data transmitted through the first Socket channel. The first cache space is a ring buffer.

[0102] Step 104: Determine the target CPU, trigger an interrupt signal to the target CPU, receive activation information sent by the target CPU, and transmit the target data to the target CPU according to the activation information.

[0103] In this embodiment, after the first cache space receives and stores the target data, the main CPU, after identifying the target CPU, notifies the target CPU to receive the target data by triggering an interrupt. The target CPU determines whether it can receive the target data. If it can receive the target data, it sends the activation information to the main CPU, and the main CPU can transmit the target data to the target CPU according to the activation information.

[0104] Figure 2 This is a flowchart illustrating a method for inter-CPU data transfer according to an exemplary embodiment, such as... Figure 2 As shown, the method is used in the main CPU, and step 104 above also includes the following steps.

[0105] Step 201: Receive the free cache space size identifier sent by the target CPU;

[0106] In this embodiment, the target CPU also allocates a portion of its memory as a second cache space to store the target data sent through the first cache space. The second cache space is a circular buffer. The main CPU receives a free cache space size identifier sent by the target CPU, and can obtain the size of the free space in the second cache space based on the free cache space size identifier.

[0107] In a circular buffer, data is written and read in a specific order. Once the buffer is full, new data is written to overwrite the old data sequentially from the beginning, rather than deleting data before writing it, thus improving data read / write efficiency. The circular buffer can contain write pointers and read pointers; the write pointer indicates the position reached during a write operation, and the read pointer indicates the position reached during a read operation.

[0108] Step 202: Create a first write pointer and a first read pointer in the first cache space according to the free cache space size identifier.

[0109] In this embodiment, when the second cache space begins receiving data transmitted from the first cache space, in order to synchronize the read / write status of the second cache space and the first cache space, the target CPU creates a second write pointer and a second read pointer in the second cache space and sends the free cache space size identifier. The main CPU creates a first write pointer and a first read pointer according to the free cache space size identifier, making the positions of the first write pointer and the second write pointer the same, and the positions of the first read pointer and the second read pointer the same. It should be noted that, in order to synchronize the read / write status of the second cache space and the first cache space, the second cache space and the first cache space have the same capacity.

[0110] In one possible embodiment, the size of the free cache space is the same as the total capacity of the second cache space, and the positions of the first read pointer and the first write pointer are both at the beginning of the first cache space; the positions of the second read pointer and the second write pointer are both at the beginning of the second cache space.

[0111] Step 203: Send the first write pointer position information to the second cache space according to the space occupied by the target data in the first cache space, wherein the second cache space belongs to the target CPU.

[0112] In this embodiment of the application, after the target data is transmitted and stored in the first cache space, the main CPU is written with the target data. The position of the first write pointer changes, and the latest position of the first write pointer needs to be sent to the target CPU so that the target CPU can determine whether the free cache space of the second cache space can accommodate the target data.

[0113] Optionally, the method further includes:

[0114] The system receives the position update information of the second read pointer sent by the target CPU, and updates the first read pointer according to the position update information of the second read pointer.

[0115] In this embodiment, the second cache space in the target CPU performs data write and read operations. Writing increases the data in the second cache space, while reading consumes the data in the second cache space. Since the data in the second cache space is solely provided by the data in the first cache space, after the main CPU sends the latest position of the first write pointer to the target CPU, the position of the second read pointer remains consistent with the position of the first write pointer. Similarly, the first cache space does not actively read data; only after the second cache space consumes data through read operations will the first read pointer update its position based on the position update information of the second read pointer.

[0116] Optionally, step 203, which involves sending the first write pointer position information to the second cache space based on the space occupied by the target data in the first cache space, includes:

[0117] If the target data occupies less than or equal to the free cache space between the first write pointer and the first read pointer in the first cache space, then the first write pointer position information is sent to the target CPU.

[0118] In this embodiment, the free cache space between the first write pointer and the first read pointer in the first cache space reflects the free cache space in the second cache space before the target data is sent. The size relationship between the space occupied by the target data in the first cache space and the free cache space between the first write pointer and the first read pointer can be used to determine whether the second cache space can accommodate the target data. However, the position update information of the second read pointer may not be sent in a timely manner, leading to errors in the judgment and causing the target data to be unable to be accommodated by the second cache space, resulting in data loss. To avoid the aforementioned data loss situation, this application, after writing the target data into the first cache space, and when the space occupied by the target data in the first cache space is less than or equal to the free cache space between the first write pointer and the first read pointer, sends the first write pointer position information to the target CPU, providing the latest first write pointer position information to update the second write pointer position information, allowing the target CPU to determine whether the free cache space in the second cache space can accommodate the target data.

[0119] If the target data occupies more space in the first cache space than the free cache space between the first write pointer and the first read pointer, then the system enters a standby state.

[0120] In this embodiment of the application, if the target data occupies more space in the first cache space than the free cache space between the first write pointer and the first read pointer, then the free space in the second cache space is likely unable to store the target data. The target CPU enters a standby state and waits to receive the position update information of the second read pointer sent by the target CPU before re-determining whether the first write pointer position information can be sent to the target CPU.

[0121] Optionally, the method further includes:

[0122] In response to receiving the activation information sent by the target CPU, target data is sent to the second cache space.

[0123] In this embodiment of the application, if the target CPU receives the activation information sent by the target CPU, it means that the target CPU determines that the free cache space in the second cache space can accommodate the target data, and the main CPU can then send the target data to the target CPU.

[0124] Figure 3 This is a flowchart illustrating a method for inter-CPU data transfer according to an exemplary embodiment, such as... Figure 3 As shown, the method is used in the target CPU and includes the following steps.

[0125] Step 301: Establish a second socket channel in the kernel according to the preset socket;

[0126] In this embodiment, based on the concept of Socket, multiple Socket interface functions are written using OpenAMP to implement the functionality of the required Socket modules. These include functions such as `socket()` for creating a Socket channel, `bind()` for binding a Socket and a port number, `listen()` for listening to the port number corresponding to the Socket, and `accept()` for receiving connection requests from clients. The `socket()` function can be used to create the second Socket channel in the kernel of the target CPU. The second application layer in the target CPU can call the Socket interface functions to transfer the target data from the second cache space to the application layer of the target CPU through the second Socket channel.

[0127] Step 302: In response to the interrupt signal of the main CPU, receive the target data sent by the main CPU and transfer the target data to the second cache space, wherein the second cache space belongs to the target CPU;

[0128] In this embodiment, the target CPU listens for interrupt signals from the main CPU using the listening interface function. Receiving an interrupt signal indicates that the main CPU wishes to transmit the target data. The target CPU needs to determine whether the free cache space in the second cache space can accommodate the target data based on the positions of the second write pointer and the second read pointer in the second cache space. If the free cache space in the second cache space can accommodate the target data, then the target data is received and written to the second cache space.

[0129] Step 303: Send the target data in the second cache space to the second application layer through the second Socket channel, wherein the second application layer belongs to the target CPU.

[0130] In this embodiment of the application, one or more applications are running in the first application layer and the second application layer. The application in the first application layer needs to transmit data or commands, i.e., the target data, to the application in the second application layer. After the target CPU receives the target data and stores it in the second cache space, it can transmit the target data to the second APP layer through the second Socket channel, where the application receives and processes the target data.

[0131] Optionally, the method further includes:

[0132] The system sends a free cache space size identifier to the main CPU based on the free cache space in the second cache space.

[0133] In this embodiment, the target CPU allocates a portion of its memory as a second cache space to store the target data sent through the first cache space. The second cache space is a circular buffer. The main CPU receives a free cache space size identifier sent by the target CPU, and can obtain the size of the free space in the second cache space based on the free cache space size identifier.

[0134] Optionally, the method further includes:

[0135] Receive the first write pointer position information sent by the main CPU, and update the second write pointer according to the first write pointer position information.

[0136] In this embodiment, the free cache space between the first write pointer and the first read pointer in the first cache space reflects the free cache space in the second cache space before the target data is sent. The size relationship between the space occupied by the target data in the first cache space and the free cache space between the first write pointer and the first read pointer can be used to determine whether the second cache space can accommodate the target data. However, the position update information of the second read pointer may not be sent in a timely manner, leading to errors in the judgment and causing the target data to be unable to be accommodated by the second cache space, resulting in data loss. To avoid the aforementioned data loss situation, this application sends the first write pointer position information to the target CPU after writing the target data into the first cache space, and when the space occupied by the target data in the first cache space is less than or equal to the free cache space between the first write pointer and the first read pointer, providing the latest first write pointer position information to update the second write pointer position information. The target CPU can then determine whether the free cache space in the second cache space can accommodate the target data based on the updated second write pointer position information.

[0137] Optionally, after sending the target data in the second cache space to the second application layer via the second Socket channel, the method further includes:

[0138] The position update information of the second read pointer is sent to the main CPU, and the shadow pointer of the second read pointer is recorded, wherein the second write pointer and the second read pointer belong to the second cache space.

[0139] In this embodiment, the first cache space does not actively read data. Only after the second cache space consumes data through a read operation will the first read pointer update its position according to the position update information of the second read pointer sent by the target CPU. Simultaneously, the target CPU records and uploads the position of the second read pointer, i.e., the shadow pointer. Before the next transmission of the second read pointer position update information, the positions of the first read pointer and the shadow pointer are the same.

[0140] Figure 4 This is a flowchart illustrating a method for inter-CPU data transfer according to an exemplary embodiment, such as... Figure 4 As shown, the method is used in the target CPU, and step 302 above also includes the following steps.

[0141] Step 401: Obtain the free cache space corresponding to the second read pointer and the second write pointer, and the occupied cache space between the shadow pointer and the second write pointer.

[0142] In this embodiment of the application, after updating the second write pointer according to the first write pointer position information, the cache space occupied between the position of the second write pointer and the shadow pointer is equal to the space occupied by the target data, and the free cache space corresponding to the second read pointer and the second write pointer is the existing free space in the second cache space.

[0143] Step 402a: If the free cache space corresponding to the second read pointer and the second write pointer is greater than or equal to the occupied cache space, then an activation message is sent to the main CPU and the target data is received.

[0144] Step 402b: If the free cache space corresponding to the second read pointer and the second write pointer is less than the occupied cache space, then no activation information is sent to the main CPU.

[0145] In this embodiment of the application, if the free cache space corresponding to the second read pointer and the second write pointer is greater than or equal to the occupied cache space, it means that the second cache space can accommodate the target data and can receive the target data. Therefore, the activation information can be sent to command the main CPU to send the target data.

[0146] Figure 5 This is a system architecture diagram used to implement data transfer between CPUs. For example... Figure 5 As shown, CPU0 is the main CPU, and CPU1 is the target CPU. The CPU includes an application layer (APP), a kernel layer (KERNEL), and a network data exchange layer (PROTCOL). The socket function in the kernel layer contains multiple socket interface functions written using OpenAMP based on the concept of sockets in this embodiment. These functions implement the required modules of a socket, such as the `socket()` function for creating a socket channel, the `bind()` function for binding a socket and a port number, the `listen()` function for listening to the port number corresponding to the socket, and the `accept()` function for receiving connection requests from clients. When the application in the first application layer needs to transmit data or commands (i.e., target data) to the application in the second application layer, CPU1 receives the target data through the first socket channel and transmits the target data to the target CPU through the underlying network data exchange layer. The target CPU can then transmit the target data to the second application layer through the second socket channel.

[0147] Figure 6 This is a flowchart illustrating the DGRAM communication method implemented using Socket interface functions. Figure 7This is a flowchart illustrating the STREAM communication method implemented using Socket interface functions. (For example...) Figure 6 and Figure 7 As shown in the figure, multiple Socket interface functions are written using OpenAMP in this embodiment of the application. The `deviced_created` interface corresponds to the `socket()` interface function, `create_ept` corresponds to the `bind()` interface function, and the `ns_callback` interface function corresponds to the `send()` or `recv()` interface function. These Socket interface functions enable DGRAM or STREAM communication, facilitating data transfer between CPUs within the application layer.

[0148] Figure 8 This is a flowchart of data transfer between CPUs in related technologies. For example... Figure 8 As shown, the receiver includes an RXbuffer receive buffer. Each time the sender sends data to be written to the receiver, the receiver replies with an ACKsent message to inform the sender how much data has been written to the receive buffer. If, upon receiving the ACKsent message, the data to be written in the receive buffer has been completely written, it means the receive buffer has remaining free buffer space and can continue writing data. If the data to be written in the receive buffer has not been completely written, it means the receive buffer has no remaining free buffer space and cannot continue writing data. The sender needs to enter a standby state, waiting for an activation message from the receiver before continuing to write the data to be written. If the data in the receive buffer has been consumed by read operations, data can continue to be written, and the receiver can send the activation message to continue receiving new data. In this method, the receiver cannot know the status of the sender, resulting in low data transmission efficiency.

[0149] Figure 9 This is a flowchart illustrating inter-CPU data transfer according to an exemplary embodiment. For example... Figure 9 As shown, the sending end is the main CPU, where RXbuffer is the first cache space; the receiving end is the target CPU, where RXbuffer is the second cache space. When creating the first Socket channel and the second Socket channel, the target CPU creates a second write pointer and a second read pointer in the second cache space, and sends the free cache space size identifier to the main CPU. Based on the free cache space size identifier, it creates a first write pointer and a first read pointer in the first cache space.

[0150] After receiving the target data, the first cache space checks the free cache space between the first write pointer and the first read pointer. If the space occupied by the target data in the first cache space is less than or equal to the free cache space between the first write pointer and the first read pointer, an interrupt is triggered, and the first write pointer position information is sent to the target CPU. Otherwise, it enters standby mode.

[0151] The target CPU will send the position update information of the second read pointer to the main CPU and record the shadow pointer of the second read pointer.

[0152] After detecting the interrupt, the target CPU receives the first write pointer position information and updates the position of the second write pointer. It then obtains the free cache space corresponding to the second read pointer and the second write pointer, and the occupied cache space between the shadow pointer and the second write pointer. If the free cache space is greater than or equal to the occupied cache space, it sends activation information to the main CPU and receives the target data.

[0153] Figure 10 This is a block diagram illustrating an inter-CPU data transfer apparatus 1000 according to an exemplary embodiment. Figure 10 As shown, the device is applied to the main CPU and includes:

[0154] The receiving module 1010 is used to receive target data sent by the first application layer;

[0155] The first channel creation module 1020 is used to create the first socket channel in the kernel according to the preset socket;

[0156] The first transmission module 1030 is used to transmit the target data to a pre-set first buffer space according to the first Socket channel;

[0157] The cross-CPU transmission module 1040 determines the target CPU, triggers an interrupt signal to the target CPU, receives activation information sent by the target CPU, and transmits the target data to the target CPU according to the activation information.

[0158] Optionally, the cross-CPU transmission module includes:

[0159] The identification receiving submodule is used to receive the free cache space size identifier sent by the target CPU;

[0160] The pointer creation submodule is used to create a first write pointer and a first read pointer in the first cache space according to the free cache space size identifier;

[0161] The pointer position sending submodule is used to send first write pointer position information to the second cache space in the space occupied by the first cache space according to the target data, wherein the second cache space belongs to the target CPU.

[0162] Optionally, the pointer position sending submodule includes:

[0163] If the target data occupies less than or equal to the free cache space between the first write pointer and the first read pointer in the first cache space, the first transmission unit sends the first write pointer position information to the target CPU.

[0164] The second transmission unit enters a standby state if the space occupied by the target data in the first cache space is greater than the free cache space between the first write pointer and the first read pointer.

[0165] Optionally, the device further includes:

[0166] The pointer update module is used to receive the position update information of the second read pointer sent by the target CPU, and update the first read pointer according to the position update information of the second read pointer.

[0167] Optionally, the device further includes:

[0168] The target data transmission submodule is used to send target data to the second cache space in response to receiving activation information sent by the target CPU.

[0169] Figure 11 This is a block diagram illustrating an inter-CPU data transfer apparatus 1100 according to an exemplary embodiment. Figure 11 As shown, the device is applied to the target CPU and includes:

[0170] The second channel creation module 1110 is used to create a second socket channel in the kernel according to a preset socket.

[0171] The data receiving module 1120, in response to the interrupt signal of the main CPU, receives the target data sent by the main CPU and transmits the target data to the second cache space, wherein the second cache space belongs to the target CPU;

[0172] The second transmission module 1130 sends the target data in the second cache space to the second application layer through the second Socket channel, wherein the second application layer belongs to the target CPU.

[0173] Optionally, the device further includes:

[0174] The free space identifier sending module is used to send a free cache space size identifier to the main CPU based on the free cache space in the second cache space.

[0175] Optionally, the device further includes:

[0176] The pointer position update module is used to receive the first write pointer position information sent by the main CPU and update the second write pointer according to the first write pointer position information.

[0177] Optionally, the second transmission module includes:

[0178] The pointer position sending submodule is used to send the position update information of the second read pointer to the main CPU and record the shadow pointer of the second read pointer, wherein the second write pointer and the second read pointer belong to the second cache space.

[0179] Optionally, the data receiving module includes:

[0180] The space acquisition submodule is used to acquire the free cache space corresponding to the second read pointer and the second write pointer, and the occupied cache space between the shadow pointer and the second write pointer;

[0181] The first activation information sending submodule sends activation information to the main CPU and receives the target data if the free cache space is greater than or equal to the occupied cache space.

[0182] The second activation information sending submodule does not send activation information to the main CPU if the free cache space is smaller than the occupied cache space.

[0183] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0184] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0185] Figure 12A schematic block diagram of an example electronic device 1200 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0186] like Figure 12 As shown, device 1200 includes a computing unit 1201, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1202 or a computer program loaded from storage unit 12012 into random access memory (RAM) 1203. The RAM 1203 may also store various programs and data required for the operation of device 1200. The computing unit 1201, ROM 1202, and RAM 1203 are interconnected via bus 1204. Input / output (I / O) interface 1205 is also connected to bus 1204.

[0187] Multiple components in device 1200 are connected to I / O interface 1205, including: input unit 1206, such as keyboard, mouse, etc.; output unit 1207, such as various types of monitors, speakers, etc.; storage unit 1208, such as disk, optical disk, etc.; and communication unit 1209, such as network card, modem, wireless transceiver, etc. Communication unit 1209 allows device 1200 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0188] The computing unit 1201 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1201 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1201 performs the various methods and processes described above, such as the inter-CPU data transfer method. For example, in some embodiments, the inter-CPU data transfer method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1208. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1200 via ROM 1202 and / or communication unit 1209. When the computer program is loaded into RAM 1203 and executed by the computing unit 1201, one or more steps of the inter-CPU data transfer method described above may be performed. Alternatively, in other embodiments, computing unit 1201 may be configured to perform the inter-CPU data transfer method by any other suitable means (e.g., by means of firmware).

[0189] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0190] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0191] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0192] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0193] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), the Internet, and blockchain networks.

[0194] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem, addressing the shortcomings of traditional physical hosts and VPS (Virtual Private Server, or simply "VPS") services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0195] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0196] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for data transmission between central processing units (CPUs), characterized in that, Applied to the main CPU, including: Receive target data sent by the first application layer; The first socket channel is created in the kernel according to the preset socket; The target data is transmitted to a pre-set first buffer space according to the first Socket channel; Identify the target CPU, trigger an interrupt signal to the target CPU, and receive activation information sent by the target CPU and transmit the target data to the target CPU according to the activation information; The steps of determining the target CPU, triggering an interrupt signal to the target CPU, and receiving activation information from the target CPU and transmitting the target data to the target CPU according to the activation information include: Receive the free cache space size identifier sent by the target CPU, and obtain the size of the free space in the second cache space according to the free cache space size identifier; Based on the free cache space size identifier, a first write pointer and a first read pointer are created in the first cache space, such that the positions of the first write pointer and the second write pointer are the same, and the positions of the first read pointer and the second read pointer are the same; Based on the target data, a first write pointer position information is sent to the second cache space in the space occupied by the first cache space, wherein the second cache space belongs to the target CPU, and the target CPU determines whether the free cache space of the second cache space can accommodate the target data; In response to receiving the activation information sent by the target CPU, the activation information indicating that the free cache space in the second cache space can accommodate the target data, the target data is sent to the second cache space.

2. The method according to claim 1, characterized in that, The step of sending the first write pointer position information to the second cache space based on the target data in the space occupied by the first cache space includes: If the target data occupies less than or equal to the free cache space between the first write pointer and the first read pointer in the first cache space, then the first write pointer position information is sent to the target CPU. If the target data occupies more space in the first cache space than the free cache space between the first write pointer and the first read pointer, then the system enters a standby state.

3. The method according to claim 2, characterized in that, The method further includes: The system receives the position update information of the second read pointer sent by the target CPU, and updates the first read pointer according to the position update information of the second read pointer.

4. A method for data transmission between CPUs, characterized in that, Applied to the target CPU, including: A second socket channel is established in the kernel according to the preset socket; In response to an interrupt signal from the main CPU, the system receives target data sent by the main CPU and transfers the target data to a second cache space, wherein the second cache space belongs to the target CPU. The target data in the second cache space is sent to the second application layer through the second Socket channel, wherein the second application layer belongs to the target CPU; The method further includes: receiving first write pointer position information sent by the main CPU, and updating the second write pointer according to the first write pointer position information; After sending the target data in the second cache space to the second application layer through the second Socket channel, the method further includes: sending the position update information of the second read pointer to the main CPU, and recording the shadow pointer of the second read pointer, wherein the second write pointer and the second read pointer belong to the second cache space; The step of receiving the target data sent by the main CPU and transferring the target data to the second cache space includes: Obtain the free cache space corresponding to the second read pointer and the second write pointer, and the occupied cache space between the shadow pointer and the second write pointer; If the free cache space corresponding to the second read pointer and the second write pointer is greater than or equal to the occupied cache space, then an activation message is sent to the main CPU to command the main CPU to send the target data and receive the target data; If the free cache space corresponding to the second read pointer and the second write pointer is less than the occupied cache space, then no activation information is sent to the main CPU.

5. The method according to claim 4, characterized in that, The method further includes: The system sends a free cache space size identifier to the main CPU based on the free cache space in the second cache space.

6. A device for inter-CPU data transmission, characterized in that, Applied to the main CPU, including: The receiving module is used to receive target data sent by the first application layer; The first channel creation module is used to create the first socket channel in the kernel based on the preset socket. The first transmission module is used to transmit the target data to a pre-set first buffer space according to the first Socket channel; The cross-CPU transmission module identifies the target CPU, triggers an interrupt signal to the target CPU, receives activation information sent by the target CPU, and transmits the target data to the target CPU according to the activation information. The cross-CPU transmission module includes: The identification receiving submodule is used to receive the free cache space size identifier sent by the target CPU, and obtain the size of the free space in the second cache space according to the free cache space size identifier; The pointer creation submodule is used to create a first write pointer and a first read pointer in the first cache space according to the free cache space size identifier, such that the positions of the first write pointer and the second write pointer are the same, and the positions of the first read pointer and the second read pointer are the same; The pointer position sending submodule is used to send first write pointer position information to the second cache space according to the space occupied by the target data in the first cache space, wherein the second cache space belongs to the target CPU, and the target CPU determines whether the free cache space of the second cache space can accommodate the target data; In response to receiving the activation information sent by the target CPU, the activation information indicating that the free cache space in the second cache space can accommodate the target data, the target data is sent to the second cache space.

7. A device for inter-CPU data transmission, characterized in that, Applied to the target CPU, including: The second channel creation module is used to establish a second socket channel in the kernel based on a preset socket. The data receiving module, in response to the interrupt signal of the main CPU, receives the target data sent by the main CPU and transmits the target data to the second cache space, wherein the second cache space belongs to the target CPU; The second transmission module sends the target data in the second cache space to the second application layer through the second Socket channel, wherein the second application layer belongs to the target CPU; The device further includes: a pointer position update module, used to receive first write pointer position information sent by the main CPU, and update the second write pointer according to the first write pointer position information; The second transmission module includes: a pointer position sending submodule, used to send the position update information of the second read pointer to the main CPU, and record the shadow pointer of the second read pointer, wherein the second write pointer and the second read pointer belong to the second cache space; The data receiving module includes: The space acquisition submodule is used to acquire the free cache space corresponding to the second read pointer and the second write pointer, and the occupied cache space between the shadow pointer and the second write pointer; The first activation information sending submodule sends activation information to the main CPU if the free cache space corresponding to the second read pointer and the second write pointer is greater than or equal to the occupied cache space, in order to command the main CPU to send the target data and receive the target data. If the free cache space corresponding to the second read pointer and the second write pointer is less than the occupied cache space, the second activation information sending submodule will not send activation information to the main CPU.

8. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the method for inter-CPU data transfer as described in any one of claims 1 to 3 or the method for inter-CPU data transfer as described in any one of claims 4 to 5.

9. A computer-readable storage medium, wherein instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the inter-CPU data transfer method as claimed in any one of claims 1 to 3 or the inter-CPU data transfer method as claimed in any one of claims 4 to 5.

10. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 3 or the method according to any one of claims 4 to 5.

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