A coding verification system, method, device and readable storage medium

Abstract

The application discloses a coding and decoding verification system, method, device and readable storage medium in the computer technology field. The coding and decoding verification system provided by the application can make the coding module and the decoding module run independently, and the completed coding module or decoding module can be independently deployed in the system, so that the corresponding coding module or decoding module is called alone in the system to perform chip verification work, thereby reducing the hysteresis of the chip verification work and shortening the overall time of chip development. Meanwhile, the comparison end provided by the system facilitates positioning of design loopholes existing in the coding module and / or the decoding module. Moreover, the system makes the coding module and the decoding module perform verification in the same environment, can realize reuse of the same test data in different modules, thereby simplifying the chip verification process and saving computer resources used for verification.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an encoding / decoding verification system, method, device, and readable storage medium. Background Technology

[0002] Currently, the completed encoding and decoding algorithm chips need to be verified. Generally, chip designers design the encoding and decoding logic in the chip based on RTL, forming an RTL module; algorithm engineers implement the encoding and decoding logic in the chip through software design, forming a software module, and then use the RTL module and the software module to verify the input data.

[0003] Typically, chip verification can only begin after the RTL and software modules are fully written. Furthermore, verifying the encoding and decoding logic in two separate environments results in the same test data being tested separately in each environment, wasting service resources. Chip verification also has a certain lag, which extends the overall chip development time.

[0004] Therefore, how to simplify the chip verification process, reduce the lag in chip verification work, and save the computer resources used for verification is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide an encoding / decoding verification system, method, device, and readable storage medium to simplify the chip verification process, reduce the lag in chip verification work, and save computer resources used for verification. The specific solution is as follows:

[0006] In a first aspect, this application provides an encoding / decoding verification system, comprising: an encoding end, a decoding end, and a comparison end;

[0007] The encoding end is used to acquire encoded data; if at least one encoding module is detected, the encoded data is transmitted to at least one encoding module, and the encoding result obtained by the encoding data of at least one encoding module is acquired; if at least one decoding module is detected, the encoded data is transmitted to the comparison end.

[0008] The decoding end is used to obtain the encoding result; if at least one decoding module is detected, any encoding result is transmitted to at least one decoding module, and the decoding result obtained by at least one decoding module from the corresponding encoding result is obtained, and the obtained decoding result is transmitted to the comparison end.

[0009] The comparison end is used to compare encoded data with arbitrary decoding results and record the comparison results.

[0010] Optionally, it also includes:

[0011] The data provider is used to generate encoded data, store arbitrary encoded results, and transmit arbitrary encoded results to the decoder.

[0012] Optionally, the encoding end includes: a first deployment unit, a first input unit, a first driving unit, a first monitoring unit, and a first comparison unit;

[0013] The first deployment unit is used to deploy at least one coding module according to user operations;

[0014] The first input unit is used to obtain encoded data from the data provider.

[0015] The first drive unit, using

[0016] The system detects the presence of an encoding module; if at least one encoding module is detected, the encoded data is transmitted to the at least one encoding module; it also detects the presence of a decoding module; if at least one decoding module is detected, the encoded data is transmitted to the comparison end.

[0017] The first listening unit is used to acquire and transmit the encoding result obtained by at least one encoding module to the data provider.

[0018] The first comparison unit is used to acquire and compare the encoding results obtained by encoding data from different encoding modules, and record the comparison results.

[0019] Optionally, the decoding end includes: a second deployment unit, a second input unit, a second driving unit, a second monitoring unit, and a second comparison unit;

[0020] The second deployment unit is used to deploy at least one decoding module according to user operations;

[0021] The second input unit is used to obtain arbitrary encoded results from the data provider.

[0022] The second driving unit is used to detect the presence of a decoding module; if at least one decoding module is detected, the arbitrary encoding result is transmitted to at least one decoding module.

[0023] The second monitoring unit is used to acquire and transmit the decoding result obtained by at least one decoding module from decoding arbitrary encoding results to the comparison end;

[0024] The second comparison unit is used to acquire and compare the decoding results obtained by different decoding modules decoding arbitrary encoding results, and record the comparison results.

[0025] Optionally, the first driving unit is specifically used to: detect whether the macros of the encoding module and / or the macros of the decoding module are enabled; if the macros of the encoding module and / or the macros of the decoding module are enabled, then determine that the encoding module and / or the decoding module are detected; otherwise, determine that no usable encoding module and / or decoding module is detected.

[0026] Accordingly, the second driving unit is specifically used to: detect whether the macro of the decoding module has been enabled; if the macro of the decoding module is enabled, then it is determined that the decoding module has been detected; otherwise, it is determined that no usable decoding module has been detected.

[0027] Optionally, the arbitrary encoding module and arbitrary decoding module are derived from the C, Perl, Python, Verilog and / or VHDL languages.

[0028] Optionally, it also includes:

[0029] The positioning end is used to obtain comparison results of decoding results obtained by different decoding modules decoding arbitrary encoding results, comparison results of encoding results obtained by different encoding modules encoding encoded data, and / or comparison results of encoded data and arbitrary decoding results, and to locate the problems in the corresponding encoding module and / or the corresponding decoding module based on the obtained comparison results.

[0030] Secondly, this application provides an encoding / decoding verification method, including:

[0031] Obtain encoded data;

[0032] If at least one encoding module is detected, the encoded data is transmitted to at least one encoding module, and the encoding result obtained by at least one encoding module encoding the encoded data is acquired.

[0033] If at least one decoding module is detected, any encoded result is transmitted to at least one decoding module, and the decoded result obtained by at least one decoding module from the corresponding encoded result is obtained.

[0034] Compare the encoded data with any decoded result, and record the comparison results.

[0035] Optionally, it also includes:

[0036] When there are at least two encoding modules, compare the encoding results obtained by encoding data by different encoding modules, and record the comparison results.

[0037] Optionally, it also includes:

[0038] With at least two decoding modules, compare the decoding results obtained by different decoding modules for decoding arbitrary encodings, and record the comparison results.

[0039] Optionally, detecting at least one encoding module includes: detecting that the macro of at least one encoding module is enabled;

[0040] Accordingly, at least one decoding module is detected, including: detecting that the macro of at least one decoding module is enabled.

[0041] Optionally, if it is detected that the macros of at least one encoding module and / or at least one decoding module are turned off, then it is determined that at least one encoding module and / or at least one decoding module does not exist.

[0042] Optionally, the arbitrary encoding module and arbitrary decoding module are derived from the C, Perl, Python, Verilog and / or VHDL languages.

[0043] Optionally, it also includes:

[0044] Based on the comparison results, locate the problems in the corresponding encoding module and / or the corresponding decoding module.

[0045] Thirdly, this application provides an electronic device, comprising:

[0046] Memory, used to store computer programs;

[0047] A processor is used to execute computer programs to implement the aforementioned disclosed encoding / decoding verification method.

[0048] Fourthly, this application provides a readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned encoding / decoding verification method.

[0049] As can be seen from the above scheme, this application provides an encoding / decoding verification system, including: an encoding end, a decoding end, and a comparison end; the encoding end is used to acquire encoded data; if at least one encoding module is detected, the encoded data is transmitted to at least one encoding module, and the encoding result obtained by at least one encoding module encoding the encoded data is acquired; if at least one decoding module is detected, the encoded data is transmitted to the comparison end; the decoding end is used to acquire the encoding result; if at least one decoding module is detected, any encoding result is transmitted to at least one decoding module, and the decoding result obtained by at least one decoding module decoding the corresponding encoding result is acquired, and the acquired decoding result is transmitted to the comparison end; the comparison end is used to compare the encoded data and any decoding result, and record the comparison result.

[0050] As can be seen, the encoding / decoding verification system provided in this application enables the encoding logic in the encoding / decoding algorithm to be an independent encoding module, and the decoding logic in the encoding / decoding algorithm to be an independent decoding module, with the encoding and decoding modules operating independently. Therefore, for an RTL module, it can consist of an RTL encoding module and an RTL decoding module, which operate independently. Thus, even if only the RTL encoding module is designed and completed, it can be used independently for verification without waiting for the RTL decoding module, thereby enabling design-while-verifying. Specifically, the designed encoding or decoding module can be deployed in the encoding / decoding verification system provided in this application, allowing it to be called independently within the system for chip verification, reducing the lag in chip verification and shortening the overall chip development time. Simultaneously, the comparison terminal provided by the system can compare the input encoded data with the decoding results output by any type of decoding module and record the comparison results, thereby facilitating the location of design flaws in the encoding and / or decoding modules. Moreover, the system enables the encoding and decoding modules to be verified in the same environment, allowing the reuse of the same test data (including the encoded data as input and related encoding and decoding results) in different modules, thereby simplifying the chip verification process and saving the computer resources used for verification.

[0051] Correspondingly, the encoding / decoding verification method, device, and readable storage medium provided in this application also have the above-mentioned technical effects. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of an encoding / decoding verification system disclosed in this application;

[0054] Figure 2 This is a schematic diagram of another encoding / decoding verification system disclosed in this application;

[0055] Figure 3 This is a schematic diagram of the first verification process disclosed in this application;

[0056] Figure 4 This is a schematic diagram of the second verification process disclosed in this application;

[0057] Figure 5 This is a schematic diagram of the third verification process disclosed in this application;

[0058] Figure 6 This is a schematic diagram of the fourth verification process disclosed in this application;

[0059] Figure 7 This is a schematic diagram of the fifth verification process disclosed in this application;

[0060] Figure 8 This is a schematic diagram of the sixth verification process disclosed in this application;

[0061] Figure 9 This is a flowchart of an encoding / decoding verification method disclosed in this application;

[0062] Figure 10 This is a schematic diagram of an electronic device disclosed in this application. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0064] Currently, because RTL modules and software modules are manually designed and written, errors and omissions may exist, directly affecting verification results. If the output of an RTL or software module is incorrect, it is difficult to determine whether the problem lies in the encoding or decoding logic. Chip verification can only proceed after both the RTL and software modules are fully written. Furthermore, the encoding and decoding logic of both RTL and software modules are verified in two separate environments, resulting in the same test data being tested separately in each environment, wasting service resources. Chip verification also suffers from a certain lag, which extends the overall chip development time. Therefore, this application provides an encoding / decoding verification scheme that simplifies the chip verification process, reduces the lag in chip verification, and saves computer resources used for verification.

[0065] See Figure 1 As shown in the figure, this application discloses an encoding and decoding verification system, including: an encoding end, a decoding end, a comparison end, and a data providing end.

[0066] The encoding end is used to acquire encoded data. If at least one encoding module is detected, the encoded data is transmitted to the at least one encoding module, and the encoding result obtained by the at least one encoding module is acquired. If at least one decoding module is detected, the encoded data is transmitted to the comparison end. This embodiment allows the encoding end to deploy multiple encoding modules, such as encoding modules based on C, Perl, Python, Verilog, and / or VHDL languages. Each deployed encoding module can be individually invoked to encode the data.

[0067] The decoding end is used to acquire the encoded result. If at least one decoding module is detected, any encoded result is transmitted to at least one decoding module, and the decoding result obtained by at least one decoding module from the corresponding encoded result is acquired. The obtained decoding result is then transmitted to the comparison end. This embodiment allows the decoding end to deploy multiple decoding modules, such as decoding modules based on C, Perl, Python, Verilog, and / or VHDL languages. Each deployed decoding module can be individually invoked to decode the encoded result output by any encoding module.

[0068] The comparison end is used to compare encoded data with arbitrary decoding results and record the comparison results.

[0069] The data provider is used to generate encoded data, store arbitrary encoded results, and transmit these results to the decoding end. This data provider allows encoded data and arbitrary encoded results to be reused across different modules, thereby saving resources.

[0070] In one embodiment, the encoding end includes: a first deployment unit, a first input unit (SQR0), a first driving unit (DRV0), a first monitoring unit (MON0), and a first comparison unit (SCB0); the first deployment unit is used to deploy at least one encoding module according to user operation; the first input unit is used to obtain encoded data from the data provider; the first driving unit detects whether an encoding module exists; if at least one encoding module is detected, the encoded data is transmitted to the at least one encoding module; detects whether a decoding module exists; if at least one decoding module is detected, the encoded data is transmitted to the comparison end; the first monitoring unit is used to acquire and transmit the encoding result obtained by encoding the encoded data of at least one encoding module to the data provider; the first comparison unit is used to acquire and compare the encoding results obtained by encoding the encoded data of different encoding modules, and record the comparison results. It can be seen that the first comparison unit can compare the encoding results obtained by different encoding modules encoding the same encoded data, thereby directly determining whether there are design flaws in different encoding modules, and facilitating the location of problems.

[0071] In one embodiment, the decoding end includes: a second deployment unit, a second input unit (SQR1), a second driving unit (DRV1), a second monitoring unit (MON1), and a second comparison unit (SCB1); the second deployment unit is used to deploy at least one decoding module according to user operation; the second input unit is used to obtain arbitrary encoding results from the data provider; the second driving unit detects whether a decoding module exists; if at least one decoding module is detected, the arbitrary encoding result is transmitted to the at least one decoding module; the second monitoring unit is used to obtain and transmit the decoding result obtained by the at least one decoding module from decoding the arbitrary encoding result to the comparison end; the second comparison unit is used to obtain and compare the decoding results obtained by different decoding modules from decoding the arbitrary encoding result, and record the comparison results. It can be seen that the second comparison unit can compare the decoding results obtained by different decoding modules from decoding the same encoding result, thereby directly determining whether there are design flaws in different decoding modules, and facilitating the location of problems.

[0072] Accordingly, the system provided in this embodiment also includes a positioning end, which is used to obtain comparison results of decoding results obtained by different decoding modules decoding arbitrary encoding results, comparison results of encoding results obtained by different encoding modules encoding encoded data, and / or comparison results of encoded data and arbitrary decoding results, and to locate problems in the corresponding encoding module and / or the corresponding decoding module based on the obtained comparison results.

[0073] It should be noted that deployed encoding modules have a switch to indicate whether they can be invoked. For example, when macros are used as the switch, if a macro in an encoding module is detected as enabled, the input encoded data can be transmitted to that module; if a macro in an encoding module is detected as disabled, the input encoded data will not be transmitted; if no encoding module is detected, it means that no encoding module has been deployed. Similarly, deployed decoding modules also have a switch to indicate whether they can be invoked. For example, when macros are used as the switch, if a macro in a decoding module is detected as enabled, the encoded result output from any encoding module in the system can be transmitted to that decoding module; if a macro in a decoding module is detected as disabled, no encoded result will be transmitted; if no decoding module is detected, it means that no decoding module has been deployed.

[0074] In one implementation, the first driving unit is specifically configured to: detect whether the macros of the encoding module and / or the macros of the decoding module are enabled; if the macros of the encoding module and / or the macros of the decoding module are enabled, then determine that the encoding module and / or the decoding module are detected; otherwise, determine that no usable encoding module and / or decoding module is detected; correspondingly, the second driving unit is specifically configured to: detect whether the macros of the decoding module are enabled; if the macros of the decoding module are enabled, then determine that the decoding module is detected; otherwise, determine that no usable decoding module is detected.

[0075] In one implementation, the arbitrary encoding module and arbitrary decoding module are derived from C, Perl, Python, Verilog, and / or VHDL languages.

[0076] As can be seen, the encoding / decoding verification system provided in this embodiment enables the encoding logic in the encoding / decoding algorithm to be an independent encoding module, and the decoding logic in the encoding / decoding algorithm to be an independent decoding module. Furthermore, the encoding and decoding modules operate independently. Therefore, for an RTL module, it can consist of an RTL encoding module and an RTL decoding module, which operate independently. Thus, even if only the RTL encoding module is designed and completed, it can be used independently for verification without waiting for the RTL decoding module, thereby enabling design-while-verifying. Specifically, the designed encoding or decoding module can be deployed in the encoding / decoding verification system provided in this application, allowing the corresponding encoding or decoding module to be called independently within the system for chip verification, reducing the lag in chip verification and shortening the overall chip development time. Simultaneously, the comparison terminal provided by the system can compare the input encoded data with the decoding results output by any type of decoding module and record the comparison results, thereby facilitating the location of design flaws in the encoding and / or decoding modules. Moreover, the system enables the encoding and decoding modules to be verified in the same environment, allowing the reuse of the same test data (including the encoded data as input and related encoding and decoding results) in different modules, thereby simplifying the chip verification process and saving the computer resources used for verification.

[0077] The following describes another encoding / decoding verification system provided in the embodiments of this application. The encoding / decoding verification system described below can be referred to in conjunction with the other embodiments described herein.

[0078] Please see Figure 2 , Figure 2`tb_top` is the top-level module of the system's verification environment. Within this top-level module, an RTL encoding module and an RTL decoding module are instantiated. If these two modules are not deployed in the system, empty modules can be used initially, and then uploaded to the system for deployment after the designers have completed the design. The RTL encoding module is an encoding module based on an RTL language (such as Verilog, VHDL, etc.), and the RTL decoding module is a decoding module based on an RTL language.

[0079] In the verification environment, the test component instantiates several components: agt0 (encoder), agt1 (decoder), SCB2 (comparison), and v_sequence (data provider). agt0 connects to the RTL encoding module, and agt1 connects to the RTL decoding module. SCB2 is used for result comparison, and v_sequence is responsible for generating test stimulus data.

[0080] In agt0, the following components are instantiated: SQR0 (first input unit), DRV0 (first driver unit), MON0 (first listening unit), RM0, and SCB0 (first comparison unit). SQR0 receives the stimulus data packet from port 5 and sends it to DRV0 via port 6. DRV0 checks if the RTL encoding module's macro RTL_ENC is defined; if so, it drives port 1 to input stimulus data to the RTL encoding module. It also checks if at least one of the RTL decoding module's macro RTL_DEC or the C decoding module's macro C_DEC is defined. If so, it sends the stimulus data to SCB2 via port 8. Further, it checks if the C encoding module's macro C_ENC is defined. If so, DRV0 sends the stimulus data to RM0 via port 7, enabling the C encoding module to encode the stimulus data and generate the desired data. The MON0 component continuously monitors the output port of the RTL encoding module. If a data packet (data generated by the RTL encoding module encoding the stimulus data) is received through port 2, MON0 will send the data packet to SCB0. Simultaneously, it will check if the macros RTL_DEC for the RTL decoding module and C_DEC for the C decoding module are defined. If at least one of these macros is defined, and the macro C_ENC is not defined, then a copy of the data packet generated by the RTL encoding module encoding the stimulus data will be forwarded to v_sequence for storage via port 10. The C encoding module is an encoding module based on the C language, and the C decoding module is a decoding module based on the C language.

[0081] The RM0 component instantiates a C encoding module. If the C encoding module is not ready, an empty function can be used temporarily, and it can be replaced later when the algorithm developers implement it. After receiving the stimulus data sent from port 7, RM0 calls the C encoding module to encode the stimulus data and generate an encoded result, forming a data packet. RM0 forwards the generated encoded result to SCB0 through port 11. At the same time, it checks whether at least one of the macros RTL_DEC in the RTL decoding module and C_DEC in the C decoding module is defined. If so, RM0 copies the encoding result from the C encoding module and forwards it to v_sequence for storage through port 12.

[0082] The data packets sent to SCB0 through port 9 are the encoding results output by the RTL encoding module, and the data packets sent to SCB0 through port 11 are the encoding results output by the C encoding module. After receiving the data packets from these two ports, SCB0 will automatically compare them to determine whether they are consistent, thereby determining whether there is a problem with the RTL encoding module and the C encoding module.

[0083] Specifically, when only one of the macros RTL_DEC or C_DEC is defined, port 10 or port 12 will send data packets to v_sequence. When the macro C_ENC is defined, port 12 sends data packets to v_sequence; when the macro C_ENC is not defined, port 10 sends data packets to v_sequence. After receiving data packets from port 10 or port 12, v_sequence will send them to SQR1 (second input unit) of agt1 via port 13.

[0084] After SQR1 receives a data packet (the encoded result output by the RTL encoding module and / or the encoded result output by the C encoding module) through port 13, it forwards it to DRV1 (the second driver unit) through port 14. DRV1 then checks if the macro RTL_DEC of the RTL decoding module is defined. If so, it drives port 3 to input data to the RTL decoding module. It also checks if the macro C_DEC of the C decoding module is defined. If so, DRV1 copies the data through port 15 and sends it to RM1, enabling RM1 to call the C decoding module to decode the data and produce the decoding result. The MON1 component continuously monitors the output port of the RTL decoding module. If it receives a data packet output by the RTL decoding module through port 4, MON1 sends the RTL decoding module's output data packet to SCB1, and simultaneously copies the RTL decoding module's output data packet and sends it to SCB2 through port 17.

[0085] The RM1 component instantiates a C decoding module. If the C decoding module is not ready, an empty function can be used temporarily, and it can be replaced later when the algorithm developers implement it. After receiving a data packet sent from port 15, RM1 calls the C decoding module to decode the data packet and obtain the result. RM1 will then forward the decoding result to SCB1 through port 18, and at the same time, it will copy the decoding result output by the C decoding module and send it to SCB2 through port 16.

[0086] The data packets sent to SCB1 through port 19 are the data packets output by the RTL decoding module, and the data packets sent to SCB1 through port 18 are the data packets output by the C decoding module. After receiving the data packets from these two ports, SCB1 will automatically compare them to determine whether they are consistent, thereby determining whether there is a problem with the RTL decoding module and the C decoding module.

[0087] After receiving data from port 8, the SCB2 component checks if the macro C_DEC is defined. If so, it compares the data packets received from port 8 with those received from port 16. It also checks if the macro RTL_DEC is defined; if so, it compares the data packets received from port 8 with those received from port 17.

[0088] exist Figure 2 In this context, ports 1, 2, 3, and 4 are virtual interfaces used to connect the RTL encoding module, RTL decoding module, and UVM environment. Ports 10 and 12 are ports connected through the uvm_event_pool component. All other ports use the analysis_port.

[0089] As can be seen, this embodiment instantiates four modules in the verification environment: a C encoding module, a C decoding module, an RTL encoding module, and an RTL decoding module. All four modules can be enabled or disabled in the system according to their design progress. This is achieved through four separate `define` macros: `C_ENC`, `C_DEC`, `RTL_ENC`, and `RTL_DEC`. To enable the C encoding module, `C_ENC` must be defined; to enable the C decoding module, `C_DEC` must be defined; to enable the RTL encoding module, `RTL_ENC` must be defined; and to enable the RTL decoding module, `RTL_DEC` must be defined.

[0090] Please see Figure 3If the algorithm developers have completed the C encoding and decoding modules, and the chip designers have completed the RTL encoding and decoding modules, then these modules can be enabled. The environment needs to define the macros C_ENC, C_DEC, RTL_ENC, and RTL_DEC. The data flow is as follows: randomly generated raw input data packets are input to the C encoding and RTL encoding modules respectively. The C encoding module outputs data packet E1, and the RTL encoding module outputs data packet E2. Data packet E1 is input to the C decoding and RTL decoding modules through interfaces p1 and p2, and data packet E2 is input to the C decoding and RTL decoding modules through interfaces p3 and p4. After decoding by the C decoding module, data packet D1 is output, and after decoding by the RTL decoding module, data packet D2 is output. After testing, compare whether data packets E1 and E2 are consistent, and also compare whether data packets D1, D2, and O are consistent to ensure that the RTL model or C model is correct. If D1 and O are inconsistent, it indicates a problem with the C model, and the C model problem should be addressed first. When E1 and E2 are inconsistent, it indicates a problem with the C encoding module or the RTL encoding module. Prioritize addressing the problems with these modules. When D1 and O are consistent, but E1 and E2 are inconsistent, and D2 and D1 are also inconsistent, the RTL encoding module and path P4 can be shut down (i.e., port 10 can be closed). This allows for parallel processing of the RTL decoding module's problems, thus accelerating problem localization.

[0091] To achieve Figure 3 The test scenario shown makes Figure 2 All ports in the diagram are active connections. Port 8 sends the stimulus data O, and port 17 sends the RTL decoding module's output data packet D2. Data packets O and D2 are automatically compared in the SCB2 component. Port 16 sends the C decoding module's output data packet D1, and data packets O and D1 are automatically compared in the SCB2 component. Port 9 sends the RTL encoding module's output data packet E2, and port 11 sends the C encoding module's output data packet E1. Data packets E1 and E2 are automatically compared in the SCB0 component. Port 19 sends the RTL decoding module's output data packet D2, and port 18 sends the C decoding module's output data packet D1. Data packets D1 and D2 are automatically compared in the SCB1 component.

[0092] Please see Figure 4If the C encoding and decoding modules are complete, but the RTL encoding and decoding modules are not, then enable the C encoding and decoding modules (i.e., define the macros C_ENC and C_DEC), and disable the macros for the RTL encoding and decoding modules. In this case, the corresponding data flow is as follows: stimulus data O is input to the C encoding module, resulting in the output data packet E1. Then, E1 is input to the C decoding module for decoding, resulting in the output result D1. By comparing the data packet D1 with the stimulus data O, it can be determined whether there are any problems with the C encoding and decoding modules. This allows chip designers to test the C encoding and decoding modules in advance, even if they haven't been completed, to ensure that the C model, including the C encoding and decoding modules, is problem-free. In this case, the RTL encoding and decoding modules in the system can be empty, or they can be non-empty but the macros must be disabled.

[0093] To achieve Figure 4 The test scenario shown makes Figure 2 Ports 5, 6, 7, 8, 12, 13, 14, 15, and 16 are valid connections, while the other ports are invalid connections. Specifically, the data packet sent from port 8 is stimulus data O, and the data packet sent from port 16 is data packet D1. Data packets O and D1 are automatically compared within the SCB2 component.

[0094] Please see Figure 5 If the C encoding module is complete but the C decoding module is not, and the RTL encoding module is complete but the RTL decoding module is not, then the C decoding and RTL decoding modules can be turned off, while the C encoding and RTL encoding modules can be turned on. In this case, the macros `C_ENC` and `RTL_ENC` need to be defined. The corresponding data flow in this situation is as follows: stimulus data is input to the C encoding and RTL encoding modules respectively, where the output data packet of the C encoding module is E1, and the output data packet of the RTL encoding module is E2. By comparing E1 and E2, it is determined whether there is a problem with the C encoding and RTL encoding modules. Therefore, even if the C decoding and RTL decoding modules are not fully designed, it is possible to prioritize verifying whether there are any problems with the C encoding and RTL encoding modules. In this case, the C decoding and RTL decoding modules in the system can be empty, or they can be non-empty but the macros must be turned off.

[0095] To achieve Figure 5 The test scenario shown makes Figure 2Ports 1, 2, 5, 6, 7, 9, and 11 are valid connections, while the other ports are invalid connections. Specifically, port 9 sends data packet E2, which is the output of the RTL encoding module, and port 11 sends data packet E1, which is the output of the C encoding module. Data packets E1 and E2 are automatically compared within the SCB0 component.

[0096] Please see Figure 6 If the RTL encoding and decoding modules are complete, but the C encoding and decoding modules are not, you can disable the C encoding and decoding modules and enable the RTL encoding and decoding modules by defining the macros `RTL_ENC` and `RTL_DEC`. In this scenario, a loopback test can be performed on the RTL encoding and decoding modules. The data flow is as follows: stimulus data O is input to the RTL encoding module, resulting in output data packet E2. Then, E2 is input to the RTL decoding module for decoding, resulting in output result D2. By comparing data packet D2 with stimulus data O, it can be determined whether there is a problem with the RTL encoding and decoding modules. This allows for testing the RTL encoding and decoding modules even when the C encoding and decoding modules are not yet complete.

[0097] To achieve Figure 6 The test scenario shown makes Figure 2 Ports 1, 2, 3, 4, 5, 6, 8, 10, 13, 14, and 17 are valid connections, while the other ports are invalid connections. The data packet sent from port 8 is excitation data O, and the data packet sent from port 17 is data packet D2 output by the RTL decoding module. Data packets O and D2 are automatically compared within the SCB2 component.

[0098] Please see Figure 7 If the C encoding module, C decoding module, and RTL encoding module are complete, but the RTL decoding module is incomplete, in this scenario, the RTL decoding module can be turned off, while the C encoding, C decoding, and RTL encoding modules are turned on. This requires defining the macros `C_ENC`, `C_DEC`, and `RTL_ENC`. This scenario is used to perform loopback testing on the C encoding and C decoding modules, while simultaneously testing the RTL encoding module. After testing, comparing data packet D1 with stimulus data O can determine if there are any problems with the C model, including the C encoding and C decoding modules. Comparing data packets E1 and E2 can determine if there are any problems with the RTL encoding module and the C encoding module. If E1 and E2 are inconsistent, and if D1 is also inconsistent with the original data O, it indicates a problem with the C model. This problem can be addressed first, saving time needed for problem localization.

[0099] To achieve Figure 7 The test scenario shown makes Figure 2 Ports 1, 2, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, and 16 are active connections. Port 8 sends the stimulus data O, and port 16 sends the data packet D1 output by the C decoding module. Data packets O and D1 are automatically compared in the SCB2 component. Port 9 sends the actual data packet E2 output by the RTL encoding module, and port 11 sends the data packet E1 output by the C encoding module. Data packets E1 and E2 are automatically compared in the SCB0 component.

[0100] Please see Figure 8 If the C encoding module is complete but the C decoding module is not, and the chip designer has completed the RTL encoding and decoding modules, in this scenario, the C decoding module can be turned off, while the C encoding, RTL encoding, and RTL decoding modules can be turned on. The environment needs to define the macros C_ENC, RTL_ENC, and RTL_DEC. This scenario is used to perform loopback testing on the RTL encoding and decoding modules, while simultaneously testing the C encoding module. After testing, by comparing whether data packet D2 and stimulus data O are consistent, it can be determined whether there are problems with the RTL model including the RTL encoding and decoding modules. By comparing whether data packets E1 and E2 are consistent, it can be determined whether there are problems with the RTL encoding and C encoding modules. When D2 and O are inconsistent, if E1 and E2 are also inconsistent, it indicates that there are problems with the RTL encoding and C encoding modules. These problems can be addressed first, saving time needed for problem localization.

[0101] To achieve Figure 8 The test scenario shown makes Figure 2 Ports 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, and 17 are active connections. Port 8 sends the excitation data O, and port 17 sends the data packet D2, output from the RTL decoding module. Data packets O and D2 are automatically compared in the SCB2 component. Port 9 sends the data packet E2, output from the RTL encoding module, and port 11 sends the data packet E1, output from the C encoding module. Data packets E1 and E2 are automatically compared in the SCB0 component.

[0102] This embodiment selectively tests two encoding modules and two decoding modules. Modules can be freely disabled as needed, thereby accelerating the verification process and problem localization. This allows chip verification personnel to begin verification work earlier, speeding up chip development and problem identification, and reducing the consumption of server resources by verification work. Accordingly, selective testing can be performed on more encoding modules and more decoding modules to simplify the verification complexity brought about by multiple modules.

[0103] The loopback verification method used in this embodiment allows chip verification personnel to begin verification work once algorithm engineers and chip designers have completed some modules, accelerating project development. It also facilitates the identification of design flaws in each module. Furthermore, verifying the encoding and decoding modules in the same environment enables the reuse of the same test data (including the input encoded data and related encoding and decoding results) across different modules, thereby simplifying the chip verification process and saving computer resources used for verification.

[0104] The following describes a codec verification method provided by an embodiment of this application. The codec verification method described below can be referred to in conjunction with other embodiments described herein.

[0105] See Figure 9 As shown in the figure, this application discloses an encoding / decoding verification method, including:

[0106] S901, Obtain encoded data.

[0107] S902. If at least one encoding module is detected, the encoded data is transmitted to at least one encoding module, and the encoding result obtained by encoding the encoded data by at least one encoding module is obtained.

[0108] S903. If at least one decoding module is detected, the arbitrary encoding result is transmitted to at least one decoding module, and the decoding result obtained by at least one decoding module from the corresponding encoding result is obtained.

[0109] S904. Compare the encoded data with any decoded result and record the comparison result.

[0110] In one implementation, when there are at least two encoding modules, the encoding results obtained by encoding data from different encoding modules are compared and the comparison results are recorded.

[0111] In one implementation, when there are at least two decoding modules, the decoding results obtained by different decoding modules decoding arbitrary encoding results are compared and the comparison results are recorded.

[0112] In one implementation, detecting at least one encoding module includes: detecting that a macro of at least one encoding module is enabled; correspondingly, detecting at least one decoding module includes: detecting that a macro of at least one decoding module is enabled.

[0113] In one implementation, if it is detected that the macros of at least one encoding module and / or at least one decoding module are turned off, it is determined that at least one encoding module and / or at least one decoding module does not exist.

[0114] In one implementation, the arbitrary encoding module and arbitrary decoding module are derived from C, Perl, Python, Verilog, and / or VHDL languages.

[0115] In one implementation, problems in the corresponding encoding module and / or the corresponding decoding module are located based on the comparison results.

[0116] For more detailed information on the working process of each step in this embodiment, please refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0117] As can be seen, this embodiment provides a codec verification method that can simplify the chip verification process, reduce the lag in chip verification work, and save computer resources used for verification.

[0118] The following describes an electronic device provided by an embodiment of this application. The electronic device described below can be referred to in conjunction with other embodiments described herein.

[0119] See Figure 10 As shown in the figure, an embodiment of this application discloses an electronic device, including:

[0120] Memory 1001 is used to store computer programs;

[0121] The processor 1002 is configured to execute a computer program to implement the methods disclosed in any of the above embodiments.

[0122] The following describes a readable storage medium provided in an embodiment of this application. The readable storage medium described below can be referred to in conjunction with other embodiments described herein.

[0123] A readable storage medium is provided for storing a computer program, wherein the computer program, when executed by a processor, implements the encoding / decoding verification method disclosed in the foregoing embodiments. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0124] The terms “first,” “second,” “third,” “fourth,” etc., used in this application (if applicable) are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, or apparatus.

[0125] It should be noted that the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0126] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0127] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of readable storage medium known in the art.

[0128] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A codec verification system, characterized in that, include: Encoding end, decoding end, comparison end, positioning end, and data providing end; The encoding end is used to acquire encoded data; If at least one encoding module is detected, the encoded data is transmitted to the at least one encoding module, and the encoding result obtained by the at least one encoding module encoding the encoded data is obtained; if at least one decoding module is detected, the encoded data is transmitted to the comparison end. The decoding end is used to obtain the encoding result; If at least one decoding module is detected, any encoding result is transmitted to the at least one decoding module, and the decoding result obtained by the at least one decoding module from the corresponding encoding result is obtained, and the obtained decoding result is transmitted to the comparison end; The comparison end is used to compare the encoded data with any decoding result and record the comparison result; The positioning end is used to obtain a comparison result of the decoding results obtained by different decoding modules decoding arbitrary encoding results, and / or a comparison result of the encoding results obtained by different encoding modules encoding the encoded data; The data provider is used to enable the reuse of encoded data and arbitrary encoding results in different modules.

2. The system according to claim 1, characterized in that, The data providing end is used to generate the encoded data, store arbitrary encoding results, and transmit arbitrary encoding results to the decoding end.

3. The system according to claim 2, characterized in that, The encoding end includes: a first deployment unit, a first input unit, a first driving unit, a first monitoring unit, and a first comparison unit; The first deployment unit is configured to deploy at least one encoding module according to user operations; The first input unit is used to obtain the encoded data from the data provider. The first driving unit is configured to detect the presence of an encoding module; if at least one encoding module is detected, the encoded data is transmitted to the at least one encoding module; and to detect the presence of a decoding module; if at least one decoding module is detected, the encoded data is transmitted to the comparison end. The first monitoring unit is used to acquire and transmit the encoding result obtained by the at least one encoding module encoding the encoded data to the data providing end; The first comparison unit is used to acquire and compare the encoding results obtained by different encoding modules encoding the encoded data, and record the comparison results.

4. The system according to claim 3, characterized in that, The decoding end includes: a second deployment unit, a second input unit, a second driving unit, a second monitoring unit, and a second comparison unit; The second deployment unit is used to deploy at least one decoding module according to user operations; The second input unit is used to obtain arbitrary encoding results from the data provider. The second driving unit is used to detect the presence of a decoding module; if at least one decoding module is detected, the arbitrary encoding result is transmitted to the at least one decoding module. The second monitoring unit is used to acquire and transmit the decoding result obtained by the at least one decoding module from decoding arbitrary encoding results to the comparison end; The second comparison unit is used to acquire and compare the decoding results obtained by different decoding modules decoding arbitrary encoding results, and record the comparison results.

5. The system according to claim 4, characterized in that, The first driving unit is specifically used to: detect whether the macros of the encoding module and / or the decoding module are enabled; if the macros of the encoding module and / or the decoding module are enabled, then determine that the encoding module and / or the decoding module are detected; otherwise, determine that no usable encoding module and / or decoding module is detected. Accordingly, the second driving unit is specifically used to: detect whether the macro of the decoding module has been enabled; if the macro of the decoding module is enabled, then it is determined that the decoding module has been detected; otherwise, it is determined that no usable decoding module has been detected.

6. The system according to any one of claims 1 to 5, characterized in that, Arbitrary encoding and decoding modules are derived from C, Perl, Python, Verilog, and / or VHDL languages.

7. The system according to any one of claims 1 to 5, characterized in that, The positioning end is used to obtain the comparison results of encoded data and arbitrary decoding results, and to locate the problems in the corresponding encoding module and / or the corresponding decoding module based on the obtained comparison results.

8. A method for verifying encoding and decoding, characterized in that, include: Obtain encoded data; If at least one encoding module is detected, the encoded data is transmitted to the at least one encoding module, and the encoding result obtained by the at least one encoding module encoding the encoded data is obtained. If at least one decoding module is detected, any encoding result is transmitted to the at least one decoding module, and the decoding result obtained by the at least one decoding module from the corresponding encoding result is obtained. Compare the encoded data with any decoding result, and record the comparison results; This also includes: The system obtains a comparison of decoding results obtained by different decoding modules from decoding arbitrary encoding results, and / or a comparison of encoding results obtained by different encoding modules from encoding the encoded data, so that the encoded data and arbitrary encoding results can be reused in different modules.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the method as described in claim 8.

10. A readable storage medium, characterized in that, Used to store a computer program, wherein the computer program, when executed by a processor, implements the method as described in claim 8.

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