Design method, system and related apparatus for semiconductor structure

Abstract

Embodiments of the present application provide a design method, system and related device of a semiconductor structure, the method comprising: obtaining design information of a semiconductor structure and a chip preset on the semiconductor structure; calling a basic design model of the semiconductor structure, determining a stress compensation scheme of the semiconductor structure according to the design information, the stress compensation scheme at least comprising: distribution of a virtual pattern for stress compensation, a film layer type corresponding to the virtual pattern, a groove depth of the corresponding film layer and a thickness of the semiconductor structure; and outputting the stress compensation scheme. Embodiments of the present application can improve the quality of the semiconductor structure, and further improve the quality of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to a semiconductor structure design method, system, and related equipment. Background Technology

[0002] With the development of semiconductor technology, various packaging technologies have emerged, including 2.5D packaging (CoWoS, RDL, etc.) and 3D packaging (TSV). Among these, the semiconductor structure, located in the middle of the packaging structure, can be modularized using COW (Chip-on-Wafer) stacking technology. Different functional chips are stacked together with the wafer via an interposer, enabling multifunctional electronic components. This semiconductor structure can be, for example, an interposer with fine-pitch wiring capabilities. Against this backdrop, improving the quality of semiconductor structures becomes particularly important. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor structure design method, apparatus, and related equipment to improve the quality of semiconductor structures.

[0004] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0005] In a first aspect, embodiments of this application provide a method for designing a semiconductor structure, including:

[0006] To obtain design information of the semiconductor structure and the chip pre-installed on the semiconductor structure;

[0007] The basic design model of the semiconductor structure is invoked, and a stress compensation scheme for the semiconductor structure is determined based on the design information. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film layer type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure.

[0008] Output the stress compensation scheme.

[0009] Optionally, before invoking the basic design model of the semiconductor structure, the method further includes: constructing the basic design model, wherein the basic design model includes at least one design sub-model, and the design sub-model determines the corresponding semiconductor structure warpage distribution for at least one design piece of information.

[0010] Optionally, constructing the basic design model includes:

[0011] A first design sub-model is constructed, which is used to simulate the warpage distribution of semiconductor structures corresponding to different film layer types on semiconductor structures.

[0012] And / or,

[0013] A second design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different pattern densities on the semiconductor structure.

[0014] And / or,

[0015] A third design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different trench depths.

[0016] And / or,

[0017] A fourth design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different thicknesses.

[0018] Optionally, after constructing the basic design model and / or after outputting the stress compensation scheme, the method further includes: optimizing the basic design model so that the basic design model meets the accuracy requirements.

[0019] Optionally, the optimized basic design model includes:

[0020] Obtain at least one set of warpage parameters for a semiconductor structure, and design information for the semiconductor structure corresponding to the warpage parameters;

[0021] Based on the design information, the basic design model is invoked to determine the simulated warping parameters corresponding to the design information;

[0022] Compare whether the warpage parameters are the same as the simulated warpage parameters;

[0023] If so, then the basic design model meets the accuracy requirements;

[0024] If not, adjust the design sub-model corresponding to the design information in the basic design model so that the basic design model meets the accuracy requirements.

[0025] Optionally, optimizing the basic design model includes:

[0026] Obtain warpage parameters of semiconductor structures in at least one set of package structures; the package structure includes the semiconductor structure and a chip located on the semiconductor structure.

[0027] Based on the warping parameters, the compensation error of the stress compensation scheme is determined;

[0028] Based on the compensation error, the design sub-models corresponding to the design information in the basic design model are adjusted so that the basic design model meets the accuracy requirements.

[0029] Optionally, warpage parameters of multiple semiconductor structures can be obtained, and the design sub-models corresponding to the design information in the basic design model can be iteratively adjusted.

[0030] Optionally, at least using finite element analysis software, a design model is constructed based on the constraints corresponding to the design information. The design model includes the basic design model and the design sub-model.

[0031] Optionally, the semiconductor structure includes at least an adapter plate structure.

[0032] Secondly, embodiments of this application provide a semiconductor structure design system, comprising:

[0033] The acquisition module is used to acquire the semiconductor structure and the design information of the chip pre-set on the semiconductor structure.

[0034] The calling module is used to call the basic design model of the semiconductor structure and determine the stress compensation scheme of the semiconductor structure based on the design information. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film type corresponding to the virtual patterns, the trench depth of the corresponding film, and the thickness of the semiconductor structure.

[0035] The output module is used to output the stress compensation scheme.

[0036] Optionally, it may also include: a building module for building the basic design model, wherein the basic design model includes at least one design sub-model, and the design sub-model determines the corresponding semiconductor structure warpage distribution for at least one design information.

[0037] Optionally, the building module, for constructing the basic design model, includes the following steps:

[0038] A first design sub-model is constructed, which is used to simulate the warpage distribution of semiconductor structures corresponding to different film layer types on semiconductor structures.

[0039] And / or,

[0040] A second design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different pattern densities on the semiconductor structure.

[0041] And / or,

[0042] A third design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different trench depths.

[0043] And / or,

[0044] A fourth design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different thicknesses.

[0045] Optionally, it may also include an optimization module for optimizing the basic design model.

[0046] Thirdly, embodiments of this application provide an electronic device, including a memory and a processor, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the design method of the semiconductor structure as described in the first aspect above when executing the computer-executable instructions.

[0047] Fourthly, embodiments of this application provide a storage medium storing one or more computer-executable instructions, which are used to execute the semiconductor structure design method described in the first aspect above.

[0048] The semiconductor structure design method, system, and related equipment provided in this application embodiment include a method that obtains design information of a semiconductor structure and a chip pre-set on the semiconductor structure, calls a basic design model of the semiconductor structure, determines a stress compensation scheme for the semiconductor structure based on the design information, wherein the stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film layer type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure, and then outputs the stress compensation scheme.

[0049] As can be seen, the embodiments of this application, by calling the basic design model of the semiconductor structure, and based on the design information of the semiconductor structure and the chip pre-set on the semiconductor structure, can determine the stress compensation scheme of the semiconductor structure. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film layer type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure. Thus, the stress compensation required by the semiconductor structure during packaging is taken into account during the design process of the semiconductor structure, so that the semiconductor structure itself has stress distribution, improving the quality of the semiconductor structure, thereby compensating for the stress of the chip packaged on the semiconductor structure, so that the overall semiconductor structure after packaging presents stress balance, avoiding warping, and improving the quality of semiconductor devices.

[0050] Furthermore, by calling the basic design model of the semiconductor structure, a stress compensation scheme for the semiconductor structure is obtained, which makes the design of the semiconductor structure more convenient and improves the design efficiency of the semiconductor structure. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0052] Figure 1 This is a top view of a chip packaging structure;

[0053] Figure 2 It corresponds Figure 1 A simulation diagram of the warpage of the packaging structure;

[0054] Figure 3 This is an optional flowchart illustrating the semiconductor structure design method provided in the embodiments of this application;

[0055] Figures 4 to 7 This is a schematic diagram of the groove type corresponding to the virtual pattern in the stress compensation scheme provided in the embodiments of this application;

[0056] Figure 8 This is a schematic diagram showing the chip position and virtual pattern density distribution on the semiconductor structure in the packaging structure provided in this application embodiment;

[0057] Figure 9 This is another optional flowchart illustrating the semiconductor structure design method provided in the embodiments of this application;

[0058] Figure 10 This is an optional structural diagram of the basic design model provided in the embodiments of this application;

[0059] Figure 11 This is an optional flowchart of step S101 provided in an embodiment of this application;

[0060] Figure 12 This is another optional flowchart of step S101 provided in the embodiments of this application;

[0061] Figure 13 This is a schematic diagram of an optional structure of the semiconductor structure design system provided in the embodiments of this application;

[0062] Figure 14 This is a schematic diagram of another optional structure of the semiconductor structure design system provided in the embodiments of this application;

[0063] Figure 15 This is an optional block diagram of the electronic device provided in the embodiments of this application. Detailed Implementation

[0064] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] The semiconductor structure located in the middle of the package structure serves as an interconnect. Using a COW (Chip-on-Wafer) stacking process, a chip can be packaged on top of it, and a substrate, for example, can be packaged below, thus forming a semiconductor device with specific functions. Taking the interposer, located in the middle of the package structure, as an example, the interposer has fine-pitch wiring capabilities. Therefore, during chip packaging, dies with different functions can be stacked together with the wafer via the interposer. Figure 1 An exemplary top view of a chip package structure is shown. Figure 1 As shown, the chip package structure includes an adapter board 10 and a plurality of chips 11 located on the adapter board.

[0066] The adapter board 10 serves as the carrier for packaging and is a core structure in the chip packaging process. It provides electrical connection, protection, support, and heat dissipation for the chip. The adapter board can be, for example, a silicon interposer. In an optional implementation, through silicon vias (TSVs) can be provided on the adapter board to enable interconnection between the chip and the wafer, etc.

[0067] The multiple chips 11 can be logic chips configured according to design requirements.

[0068] It should be noted that during chip packaging, multiple chips are packaged on an adapter board to form a chip structure with upper and lower layers. However, since the adapter board has fixed dimensions, that is, the area and thickness of the adapter board are fixed, and the size of the adapter board is inconsistent with the size of the packaged chip, the stress of the upper and lower chip structures is uneven, which will cause the adapter board to warp, causing the cross-section of the adapter board to change from the original planar state to a curved state, resulting in warping deformation.

[0069] Therefore, to mitigate the warpage problem of semiconductor structures that act as interconnects during packaging, one alternative approach is to insert dummy dies into the chipless regions of the semiconductor structure. These dummy dies are chips without logical functions, used only to balance the stress in the semiconductor structure and alleviate stress imbalance in the packaging structure. For example... Figure 1 As shown, the packaging structure also includes multiple pseudo-chips 12.

[0070] However, the inventors discovered that the size and area of ​​the dummy chip, as well as its insertion position, are limited by the area and position of the chip on the adapter board, thus having certain limitations. Furthermore, there is uncertainty in adjusting the stress of the packaging structure by inserting a dummy chip.

[0071] Among them, corresponding Figure 1 , Figure 2 This is a simulation diagram illustrating the warpage of the packaging structure. (Example:) Figure 2 As shown, although the semiconductor structure contains both a chip and a dummy chip, the semiconductor structure still warps. Furthermore, the chip area indicated by the arrow experiences the greatest stress, which gradually expands outwards, causing the semiconductor structure to bend. It can be seen that inserting a dummy chip into the semiconductor structure results in low precision in stress adjustment, and the insertion of a dummy chip introduces uncertainty into the stress adjustment of the packaged structure.

[0072] In view of this, embodiments of this application propose an improved semiconductor structure design scheme. By calling the basic design model of the semiconductor structure and based on the design information of the semiconductor structure and the chip pre-installed on the semiconductor structure, a stress compensation scheme for the semiconductor structure can be determined. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film layer type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure. Thus, during the semiconductor structure design process, the stress compensation required by the semiconductor structure during packaging is taken into account, so that the semiconductor structure itself has a stress distribution, improving the quality of the semiconductor structure. Furthermore, through this stress distribution, the stress of the chip packaged on the semiconductor structure is compensated, so that the overall packaging structure presents stress balance, avoiding warping and improving device quality.

[0073] It should be noted that in the semiconductor fabrication process, the utilization rate of the semiconductor structure itself is low. The pattern density of through silicon vias (TSVs) used to interconnect chips and wafers is less than 1%, and approximately 98% of the area of ​​a semiconductor structure is unused. Therefore, during the semiconductor structure design process, by designing dummy trenches with different pattern density distributions and corresponding films with different stress characteristics, a corresponding stress state distribution can be generated on the fabricated semiconductor structure based on the dummy pattern density at different locations. This provides positive or negative stress to the semiconductor structure. In other words, the fabricated semiconductor structure itself will have a stress distribution, which can compensate for the stress at the corresponding positions of the chip packaged onto the semiconductor structure in the packaging structure, so that the overall semiconductor structure presents stress balance and avoids warping.

[0074] Figure 3 An exemplary schematic diagram illustrates an optional flow of the semiconductor structure design method provided in an embodiment of this application. For example... Figure 3 As shown, the design method for semiconductor structures may include the following steps.

[0075] Step S100: Obtain the design information of the semiconductor structure and the chip pre-installed on the semiconductor structure.

[0076] The design information can be understood as information such as the material, thickness, area, and film structure of the semiconductor structure, as well as information such as the number of chips, their corresponding thickness, area, placement, bonding method with the semiconductor structure, and bonding materials used in the pre-designed packaging structure.

[0077] By acquiring the design information of the semiconductor structure and the chip pre-installed on the semiconductor structure, it is possible to understand the stress experienced by the semiconductor structure in the packaging structure.

[0078] Step S120: Call the basic design model of the semiconductor structure and determine the stress compensation scheme of the semiconductor structure based on the design information.

[0079] The basic design model of a semiconductor structure can be a warpage simulation model built by taking into account factors such as the thermal expansion coefficient, Young's modulus, geometry, and contact methods of the semiconductor material, guided by semiconductor structure process simulation. Alternatively, the basic design model can be obtained using software such as SolidWorks or ANSYS finite element analysis software.

[0080] By calling a basic design model of a semiconductor structure and inputting the design information into the basic design model, the basic design model can simulate the warpage distribution of the semiconductor structure. Based on the simulated warpage distribution, a stress compensation scheme for the semiconductor structure can be determined. The stress compensation scheme may include at least the distribution of virtual patterns for stress compensation, the film type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure.

[0081] It is understood that the stress compensation scheme determined by the basic design model of the semiconductor structure is for the stress of the chip packaged on the semiconductor structure, and this stress can be directional. Therefore, the film type corresponding to the virtual pattern in the stress compensation scheme can be a thin film that provides stress in different directions, such as a thin film that provides upward tensile stress or downward compressive stress. As an optional example, different methods can be used to generate film layers with different stress characteristics, such as silicon nitride layers or silicon oxide layers formed by deposition processes at different temperatures. Correspondingly, the stress magnitude corresponding to different film layers can also be different. As an optional implementation, the stress magnitude can be reflected by the film layer type or film layer thickness, that is, the film layer filling the trench can be a single-layer structure, such as a silicon oxide layer; or it can be a multi-layer structure, such as a stack of silicon nitride layers and silicon oxide layers. Among them, the trench depth, film layer type, and other information corresponding to the virtual pattern in the stress compensation scheme can be selected according to actual needs, and this application embodiment does not impose any limitations on this.

[0082] As an optional implementation, Figures 4 to 7 An exemplary schematic diagram of the optional groove types corresponding to the virtual pattern in the stress compensation scheme is shown, with reference to... Figures 4 to 7 As shown, the virtual pattern obtained based on the groove type in the stress compensation scheme can be circular, square, or rectangular.

[0083] It should be noted that the above examples are only optional implementations of virtual patterns. The virtual patterns in this application embodiment can also be composed of graphics with complex designs, and can be output according to actual needs. This application embodiment does not set any limitations in this regard.

[0084] In one example Figure 8 An exemplary diagram illustrates the chip placement within a package structure and the density distribution of virtual patterns on the semiconductor structure. Corresponding to... Figure 8 The chip locations and virtual pattern density distribution on the semiconductor structure are shown in Table 1:

[0085]

[0086] Table 1

[0087] It can be seen that the virtual pattern density distribution on the semiconductor structure varies depending on the location of the packaged chip. Furthermore, the virtual pattern density distribution also differs at different locations within the same chip area. This flexibility in virtual pattern density distribution effectively compensates for stress at the chip's location within the package structure, ensuring overall stress balance in the packaged semiconductor structure and preventing warping.

[0088] Understandably, the stress compensation scheme for a semiconductor structure can be determined based on the basic design model of the semiconductor structure, making the design of the semiconductor structure more convenient, improving design efficiency, and providing support for subsequent packaging processes.

[0089] Step S140: Output the stress compensation scheme.

[0090] Based on the stress compensation scheme of the output, a semiconductor structure with its own stress distribution can be prepared, thereby compensating for the stress of packaging the chip onto the semiconductor structure in the packaging structure, so that the semiconductor structure as a whole presents stress balance and avoids warping.

[0091] As can be seen, this application embodiment, by calling the basic design model of the semiconductor structure and based on the semiconductor structure and the design information of the chip pre-installed on the semiconductor structure, can determine the stress compensation scheme of the semiconductor structure. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film layer type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure. This allows the stress compensation required for packaging to be considered during the semiconductor structure design process, resulting in a stress distribution within the semiconductor structure itself, improving the quality of the semiconductor structure. Furthermore, this stress distribution compensates for the stress of the chip packaged on the semiconductor structure, ensuring overall stress balance in the packaging structure, preventing warping, and improving device quality. Moreover, obtaining the stress compensation scheme of the semiconductor structure by calling the basic design model makes the semiconductor structure design more convenient and improves the design efficiency.

[0092] In some embodiments, based on the invocation of a basic design model of the semiconductor structure, Figure 9 An exemplary schematic diagram illustrates another optional flow of the semiconductor structure design method in an embodiment of this application. For example... Figure 9 As shown, before step S120, the following may also be included:

[0093] Step S110: Construct a basic design model of the semiconductor structure.

[0094] The basic design model includes at least one design sub-model, which determines the corresponding semiconductor structure warpage distribution for at least one design piece of information.

[0095] It is understandable that semiconductor structures are designed using different design information, such as different thicknesses of different film layer properties, different pattern density distributions of the same film layer, different film layers with the same pattern density distribution, and different trench depths of the same film layer. When the design information of a semiconductor structure is different, the corresponding warpage may also be different. Therefore, it is necessary to comprehensively consider the different design information of semiconductor structures. Basic design models can be constructed for different design information, and a design sub-model can be built for each design information, thereby determining the corresponding warpage distribution of the semiconductor structure for at least one design information.

[0096] As an optional implementation, Figure 10 An exemplary schematic diagram of an optional structure for the basic design model is shown. For example... Figure 10 As shown, the basic design model can include: a first design sub-model, a second design sub-model, a third design sub-model, and a fourth design sub-model. The first design sub-model can be used to simulate the warpage distribution of the semiconductor structure corresponding to different film layer types; the second design sub-model can be used to simulate the warpage distribution of the semiconductor structure corresponding to different pattern densities; the third design sub-model is used to simulate the warpage distribution of the semiconductor structure corresponding to different trench depths; and the fourth design sub-model is used to simulate the warpage distribution of the semiconductor structure corresponding to different thicknesses.

[0097] Combination Figure 10 As shown, in a specific example, the steps of constructing the basic design model may include: constructing a first design sub-model, and / or, constructing a second design sub-model, and / or, constructing a third design sub-model, and / or, constructing a fourth design sub-model. The first design sub-model, the second design sub-model, the third design sub-model, and the fourth design sub-model may be constructed using finite element analysis software, such as SolidWorks, ANSYS, etc.

[0098] It should be noted that the above example is only an optional implementation. The sub-model can be constructed according to actual needs, and the embodiments of this application do not impose any restrictions on this.

[0099] In some embodiments, to ensure the accuracy of the basic design model being invoked, the basic design model needs to meet accuracy requirements in order to output a more accurate stress compensation scheme. For example... Figure 9 As shown, after step S110, and / or after step S140, the following may also be included:

[0100] Step S101: Optimize the basic design model so that the basic design model meets the accuracy requirements.

[0101] As an optional implementation, the step of optimizing the basic design model can be performed after the basic design model is constructed. This involves using collected existing data to correct the constructed basic design model. The collected existing data can be warpage distribution data of semiconductor structures under different design conditions when the chip is not packaged, i.e., the actual warpage parameters of the semiconductor structure. In a specific example, refer to... Figure 11 The steps for optimizing the basic design model shown may include:

[0102] Step S21: Obtain at least one set of actual warpage parameters of the semiconductor structure, and the design information of the semiconductor structure corresponding to the actual warpage parameters.

[0103] Step S22: Based on the design information, call the basic design model to determine the simulation warping parameters corresponding to the design information.

[0104] Step S23: Compare whether the actual warping parameters are the same as the simulated warping parameters.

[0105] By comparing the actual warping parameters with the simulated warping parameters of the basic design model, the accuracy of the constructed basic design model can be determined. If yes, proceed to step S24; otherwise, proceed to step S25.

[0106] Step S24: The basic design model meets the accuracy requirements.

[0107] Step S25: Adjust the design sub-models in the basic design model corresponding to the design information so that the basic design model meets the accuracy requirements.

[0108] As an alternative implementation, the step of optimizing the basic design model can be performed after calling the basic design model and outputting the stress compensation scheme. The semiconductor structure prepared using the output stress compensation scheme is then used to obtain data on the semiconductor structure within the package structure, and the basic design model is then optimized and adjusted. In a specific example, refer to... Figure 12 The steps for optimizing the basic design model shown may include:

[0109] Step S31: Obtain the warpage parameters of the semiconductor structure in at least one set of packaging structures.

[0110] The packaging structure may include the semiconductor structure and the chip located on the semiconductor structure; the warpage parameter may be the warpage parameter obtained after packaging the chip in the semiconductor structure using the output stress compensation scheme.

[0111] Step S32: Based on the warping parameters, determine the compensation error of the stress compensation scheme.

[0112] It is understandable that when packaging a semiconductor structure prepared using the output stress compensation scheme into a chip, if the semiconductor structure in the packaged structure has a warpage parameter, the stress compensation scheme determined by the basic design model cannot balance the stress of the chip package. Therefore, based on the warpage parameter, the compensation error of the stress compensation scheme can be determined.

[0113] Step S33: Based on the compensation error, adjust the design sub-model in the basic design model corresponding to the design information.

[0114] By compensating for the error, the design sub-models corresponding to the design information in the basic design model can be adjusted accordingly so that the basic design model meets the accuracy requirements.

[0115] In some embodiments, to accurately optimize the basic design model, an iterative approach can be used to optimize the basic design model. Specifically, this can be achieved by obtaining warpage parameters of multiple semiconductor structures and iteratively adjusting the design sub-models in the basic design model that correspond to the design information.

[0116] It should be noted that the above examples are only optional implementations of optimizing the basic design model. Other methods can also be used to optimize the basic design model, and this application does not limit this.

[0117] In some embodiments, the software used to simulate stress or warpage can be finite element analysis software, thereby enabling the construction of a design model based on constraints corresponding to the design information, at least using finite element analysis software. The design model may include the basic design model and design sub-models described in this application. Taking ANSYS software as an example, the steps for constructing a model using ANSYS software include:

[0118] (1) Create geometry and select analysis model. For example, create geometry and analysis model for static stress analysis.

[0119] (2) Define material properties. The material can be, for example, silicon (Si), printed circuit board (PCB), etc. In this step, the yield strength, coefficient of thermal expansion, elastic modulus and strength of the material can be set.

[0120] (3) Divide the grid.

[0121] (4) Boundary condition settings.

[0122] (5) Run analysis. For example, analyze and calculate the displacement, stress, strain, and warpage in the model.

[0123] (6) Results analysis. For example, interpreting and applying the results.

[0124] (7) Compare and analyze the simulation results of the model with the actual experimental parameters, and iteratively update the model.

[0125] In some embodiments, the semiconductor structure may include at least an adapter board structure, so as to design an adapter board structure with stress compensation using the semiconductor structure design method of the present application embodiment, so that the adapter board structure itself has stress distribution, improves the quality of the adapter board structure, and makes the overall packaged adapter board structure present stress balance, avoids warping, and improves the quality of semiconductor devices.

[0126] As can be seen, this application embodiment, by calling the basic design model of the semiconductor structure and based on the semiconductor structure and the design information of the chip pre-installed on the semiconductor structure, can determine the stress compensation scheme of the semiconductor structure. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film layer type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure. This allows the stress compensation required for packaging to be considered during the semiconductor structure design process, resulting in a stress distribution within the semiconductor structure itself, improving the quality of the semiconductor structure, and thus compensating for the stress of the chip packaged on the semiconductor structure. This ensures that the packaged semiconductor structure exhibits overall stress balance, preventing warping and improving the quality of the semiconductor device. Furthermore, by calling the basic design model of the semiconductor structure, a stress compensation scheme for the semiconductor structure is obtained, making the design of the semiconductor structure more convenient and improving its design efficiency.

[0127] This application also provides a semiconductor structure design system. Figure 13 An exemplary schematic diagram of an optional structure of a semiconductor structure design system according to an embodiment of this application is shown, such as... Figure 13 As shown, the semiconductor structure design system includes:

[0128] Acquisition module 41, the acquisition module is used to acquire the semiconductor structure and the design information of the chip preset on the semiconductor structure;

[0129] Calling module 43 is used to call the basic design model of the semiconductor structure and determine the stress compensation scheme of the semiconductor structure according to the design information. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film type corresponding to the virtual patterns, the trench depth of the corresponding film, and the thickness of the semiconductor structure.

[0130] Output module 44, the output module is used to output the stress compensation scheme.

[0131] In some embodiments, based on the invocation of the basic design model of the semiconductor structure by the invocation module 43, Figure 14 An exemplary schematic diagram of another optional structure of the semiconductor structure design system according to an embodiment of this application is shown, such as... Figure 14 As shown, it may also include:

[0132] Construction module 42 is used to construct the basic design model, wherein the basic design model includes at least one design sub-model, and the design sub-model determines the corresponding semiconductor structure warpage distribution for at least one design information.

[0133] As an optional implementation, the building module, for constructing the basic design model, includes the following steps:

[0134] A first design sub-model is constructed, which is used to simulate the warpage distribution of semiconductor structures corresponding to different film layer types on semiconductor structures.

[0135] And / or,

[0136] A second design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different pattern densities on the semiconductor structure.

[0137] And / or,

[0138] A third design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different trench depths.

[0139] And / or,

[0140] A fourth design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different thicknesses.

[0141] In some embodiments, such as Figure 14 As shown, it may further include: an optimization module 401, which is used to optimize the basic design model so that the basic design model meets the accuracy requirements.

[0142] The semiconductor structure design system of this application has a stress distribution in the designed semiconductor structure, which improves the quality of the semiconductor structure and compensates for the stress of the packaged chip. This makes the semiconductor structure present stress balance as a whole after packaging, avoids warping, and effectively improves the quality of the packaged device. Furthermore, by calling the module, the stress compensation scheme of the semiconductor structure is output, which makes the design of the semiconductor structure more convenient and improves the design efficiency of the semiconductor structure.

[0143] This application also provides an electronic device that may include a memory and a processor. The memory stores computer-executable instructions that can be executed by the processor. When the processor executes the computer-executable instructions, it performs the semiconductor structure design method as described above.

[0144] As an optional implementation Figure 15 Optional block diagrams of the electronic device provided in the embodiments of this application, such as Figure 15 As shown, the electronic device may include: at least one processor 1, at least one communication interface 2, at least one memory 3, and at least one communication bus 4.

[0145] In this embodiment, the number of processor 1, communication interface 2, memory 3, and communication bus 4 is at least one, and processor 1, communication interface 2, and memory 3 communicate with each other through communication bus 4.

[0146] Optionally, communication interface 2 can be an interface for a communication module used for network communication.

[0147] Optionally, processor 1 may be a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Embedded Neural Network Processor), FPGA (Field Programmable Gate Array), TPU (Tensor Processing Unit), AI chip, ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of this application.

[0148] Memory 3 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0149] The memory 3 stores one or more computer-executable instructions, and the processor 1 calls the one or more computer-executable instructions to execute the semiconductor structure design method of the present application embodiment.

[0150] This application also provides a storage medium that stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, they implement the semiconductor structure design method of this application embodiment.

[0151] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0152] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for designing a semiconductor structure, characterized in that, include: To obtain design information of the semiconductor structure and the chip pre-installed on the semiconductor structure; The semiconductor structure includes at least a transition plate structure; The basic design model of the semiconductor structure is invoked, and a stress compensation scheme for the semiconductor structure is determined based on the design information. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film layer type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure. The stress compensation scheme is used to ensure that the semiconductor structure itself has a stress distribution to compensate for the stress of the chip packaged on the semiconductor structure. The virtual patterns are not chip devices. Output the stress compensation scheme.

2. The semiconductor structure design method according to claim 1, characterized in that, Before invoking the basic design model of the semiconductor structure, the method further includes: constructing the basic design model, wherein the basic design model includes at least one design sub-model, and the design sub-model determines the corresponding semiconductor structure warpage distribution for at least one design information.

3. The semiconductor structure design method according to claim 2, characterized in that, The construction of the basic design model includes: A first design sub-model is constructed, which is used to simulate the warpage distribution of semiconductor structures corresponding to different film layer types on semiconductor structures. And / or, A second design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different pattern densities on the semiconductor structure. And / or, A third design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different trench depths. And / or, A fourth design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different thicknesses.

4. The semiconductor structure design method according to claim 2, characterized in that, After constructing the basic design model, and / or after outputting the stress compensation scheme, the method further includes: optimizing the basic design model so that the basic design model meets the accuracy requirements.

5. The semiconductor structure design method according to claim 4, characterized in that, Optimizing the basic design model includes: Obtain at least one set of warpage parameters for a semiconductor structure, and design information for the semiconductor structure corresponding to the warpage parameters; Based on the design information, the basic design model is invoked to determine the simulated warping parameters corresponding to the design information; Compare whether the warpage parameters are the same as the simulated warpage parameters; If so, then the basic design model meets the accuracy requirements; If not, adjust the design sub-model corresponding to the design information in the basic design model so that the basic design model meets the accuracy requirements.

6. The semiconductor structure design method according to claim 4, characterized in that, The optimization of the basic design model includes: Obtain warpage parameters of semiconductor structures in at least one set of package structures; the package structure includes the semiconductor structure and a chip located on the semiconductor structure. Based on the warping parameters, the compensation error of the stress compensation scheme is determined; Based on the compensation error, the design sub-models corresponding to the design information in the basic design model are adjusted so that the basic design model meets the accuracy requirements.

7. The method for designing a semiconductor structure according to claim 5 or 6, characterized in that, Obtain warpage parameters for multiple semiconductor structures and iteratively adjust the design sub-models corresponding to the design information in the basic design model.

8. The semiconductor structure design method according to claim 1, characterized in that, At least using finite element analysis software, a design model is constructed based on the constraints corresponding to the design information. The design model includes the basic design model and the design sub-model.

9. A semiconductor structure design system, characterized in that, include: The acquisition module is used to acquire the semiconductor structure and the design information of the chip pre-set on the semiconductor structure. The semiconductor structure includes at least a transition plate structure; The calling module is used to call the basic design model of the semiconductor structure and determine the stress compensation scheme of the semiconductor structure based on the design information. The stress compensation scheme includes at least: the distribution of virtual patterns for stress compensation, the film layer type corresponding to the virtual patterns, the trench depth of the corresponding film layer, and the thickness of the semiconductor structure. The stress compensation scheme is used to make the semiconductor structure itself have stress distribution to compensate for the stress of the chip packaged on the semiconductor structure. The virtual patterns are not chip devices. The output module is used to output the stress compensation scheme.

10. The semiconductor structure design system according to claim 9, characterized in that, Also includes: A construction module is used to construct the basic design model, wherein the basic design model includes at least one design sub-model, and the design sub-model determines the corresponding semiconductor structure warpage distribution for at least one design information.

11. The semiconductor structure design system according to claim 10, characterized in that, The construction module, used for constructing the basic design model, includes the following steps: A first design sub-model is constructed, which is used to simulate the warpage distribution of semiconductor structures corresponding to different film layer types on semiconductor structures. And / or, A second design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different pattern densities on the semiconductor structure. And / or, A third design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different trench depths. And / or, A fourth design sub-model is constructed to simulate the warpage distribution of the semiconductor structure corresponding to different thicknesses.

12. The semiconductor structure design system according to claim 9, characterized in that, Also includes: An optimization module is used to optimize the basic design model.

13. An electronic device, characterized in that, It includes a memory and a processor, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to perform a method for designing a semiconductor structure as described in any one of claims 1 to 8.

14. A storage medium, characterized in that, The storage medium stores one or more computer-executable instructions for performing the design method of the semiconductor structure as described in any one of claims 1 to 8.

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