Display panel, driving method thereof, and display device

Abstract

A display panel, a driving method thereof and a display device, the display panel comprising: a plurality of gate driving circuits, and a plurality of sub-pixels arranged in an array, each of the sub-pixels comprising a pixel driving circuit and a light emitting element, the pixel driving circuit comprising a plurality of transistors, wherein: the plurality of gate driving circuits are configured to output a plurality of gate driving signals to the plurality of transistors in the pixel driving circuit, each of the gate driving circuits outputs one of the gate driving signals, the plurality of gate driving signals are divided into at least two groups, the high voltage of the gate driving signals in the same group is the same, and the low voltage of the gate driving signals in the same group is the same; the high voltage of the gate driving signals in different groups is different, and / or the low voltage of the gate driving signals in different groups is different; and the pixel driving circuit is configured to receive the plurality of gate driving signals, and drive the light emitting element to emit light according to the received plurality of gate driving signals.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display panel, including: multiple gate driving circuits, and multiple sub-pixels arranged in an array. Each sub-pixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes multiple transistors, wherein:

[0005] The plurality of gate driving circuits are configured to output a plurality of gate driving signals to a plurality of transistors in the pixel driving circuit, wherein each of the gate driving circuits outputs a gate driving signal, the plurality of gate driving signals are divided into at least two groups, the high-level voltage of the gate driving signals in the same group is the same, and the low-level voltage of the gate driving signals in the same group is the same; the high-level voltage of the gate driving signals in different groups is different, and / or the low-level voltage of the gate driving signals in different groups is different.

[0006] The pixel driving circuit is configured to receive the various gate driving signals and drive the light-emitting element to emit light according to the received various gate driving signals.

[0007] This disclosure also provides a display device, including a display panel as described in any embodiment of this disclosure.

[0008] This disclosure also provides a method for driving a display panel, including:

[0009] Multiple gate driving circuits are controlled to output multiple gate driving signals to multiple transistors in a pixel driving circuit. The multiple gate driving signals are divided into at least two groups. The high-level voltages of the gate driving signals in the same group are the same, and the low-level voltages of the gate driving signals in the same group are the same. The high-level voltages of the gate driving signals in different groups are different, and / or the low-level voltages of the gate driving signals in different groups are different.

[0010] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0012] Figure 1 This is a schematic diagram of the structure of a display device;

[0013] Figure 2 This is a planar schematic diagram of a display panel;

[0014] Figure 3A This is a schematic diagram of a pixel driving circuit.

[0015] Figure 3B for Figure 3A A schematic diagram illustrating the working process of the provided pixel driving circuit;

[0016] Figure 4A This is a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure;

[0017] Figure 4B This is a schematic diagram of the structure of a display panel in some technologies;

[0018] Figure 5A This is a schematic diagram of another pixel driving circuit.

[0019] Figure 5B for Figure 5A A schematic diagram of the operation process of the provided pixel driving circuit. Detailed Implementation

[0020] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0021] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0022] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0023] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0024] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0025] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0026] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0027] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0028] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0029] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0030] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0031] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0032] Figure 1 This is a schematic diagram of the structure of a display device. In some examples, such as... Figure 1 As shown, the display device may include: a timing controller 21, a data driver 22, a scan driving circuit 23, a light-emitting driving circuit 24, and a sub-pixel array 25. In some examples, the sub-pixel array 25 may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driving circuit 23 may be configured to provide a scan signal to the sub-pixels PX along a scan signal line; the data driver 22 may be configured to provide a data voltage to the sub-pixels PX along a data line; the light-emitting driving circuit 24 may be configured to provide a light-emitting control signal to the sub-pixels PX along a light-emitting control line; and the timing controller 21 may be configured to control the scan driving circuit 23, the light-emitting driving circuit 24, and the data driver 22.

[0033] In some examples, such as Figure 1 As shown, timing controller 21 can provide grayscale values ​​and control signals of specifications suitable for data driver 22 to data driver 22; timing controller 21 can provide scan clock signals, scan start signals, etc. of specifications suitable for scan driver circuit 23 to scan driver circuit 23; timing controller 21 can provide light emission clock signals, light emission start signals, etc. of specifications suitable for light emission driver circuit 24 to light emission driver circuit 24. Data driver 22 can use the grayscale values ​​and control signals received from timing controller 21 to generate data voltages to be provided to data lines D1 to Di. For example, data driver 22 can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data lines D1 to Di on a sub-pixel line basis. Scan driver circuit 23 can use the scan clock signals, scan start signals, etc. received from timing controller 21 to generate scan signals to be provided to scan lines S1 to Sj. For example, scan driver circuit 23 can sequentially provide scan signals with conduction level pulses to scan lines. In some examples, the scan driver circuit 23 may include a shift register to generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of the scan clock signal. The light-emitting driver circuit 24 can generate light-emitting control signals to be provided to the light-emitting control lines EM1 to Eo using the light-emitting clock signal, light-emitting start signal, etc., received from the timing controller 21. For example, the light-emitting driver circuit 24 can sequentially provide light-emitting control signals with off-level pulses to the light-emitting control lines. The light-emitting driver circuit 24 may include a shift register to generate light-emitting control signals by sequentially transmitting light-emitting start signals, provided in the form of off-level pulses, to the next stage circuit under the control of the clock signal. Here, i, j, and o are all natural numbers.

[0034] In some examples, the display device may include a display panel. The subpixel array, scan driving circuitry, and light-emitting driving circuitry may be directly disposed on the display panel. For example, the scan driving circuitry may be disposed on the left bezel of the display panel, and the light-emitting driving circuitry may be disposed on the right bezel of the display panel; alternatively, both the left and right bezels of the display panel may contain the scan driving circuitry and the light-emitting driving circuitry. In some examples, the scan driving circuitry and the light-emitting driving circuitry may be formed together with the subpixels during the subpixel formation process.

[0035] In some examples, the data driver can be located on a separate chip or printed circuit board. For example, the data driver can be formed using chip-on-glass, chip-on-plastic, or chip-on-film technology and located on the lower bezel of the display panel to connect to the driver chip pins. The timing controller can be located separately from the data driver or integrated with it. However, this embodiment is not limited to this.

[0036] Figure 2 This is a plan view of a display panel. In some examples, such as... Figure 2 As shown, the display panel may include: a display area AA, a bonding area B1 located on one side of the display area AA, and border areas B2 located on the other sides of the display area AA. The bonding area B1 may be, for example, the bottom border of the display panel, and the border area B2 may include the top border, left border, and right border of the display panel. In some examples, the display area AA may be a flat area comprising multiple sub-pixels PX that make up a pixel array, and these sub-pixels PX are configured to display moving or still images. The display area may be referred to as the effective area. In some examples, the display panel may be a flexible substrate, and therefore the display panel may be deformable, such as rollable, bent, folded, or rolled up.

[0037] In some examples, the border area B2 may include a circuit area, a power line area, a crack dam area, and a cutting area arranged sequentially along the direction of the display area AA. The circuit area may be connected to the display area AA and may include at least multiple cascaded gate drive circuits electrically connected to multiple gate lines in the display area AA. The power line area is connected to the circuit area and may include at least low-level power lines extending parallel to the edge of the display area and connected to the cathode of the display area. The crack dam area may be connected to the power line area and may include at least multiple cracks formed on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least cutting grooves formed on the composite insulating layer. These cutting grooves can be configured to allow cutting along the cutting grooves after all film layers of the display panel have been prepared.

[0038] In some examples, the binding area B1 and the border area B2 can be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam can extend along a direction parallel to the edge of the display area to form a ring structure around the display area AA. The edge of the display area is the edge of the display area closer to the binding area B1 or the border area B2.

[0039] In some examples, such as Figure 2 As shown, the display area AA may include at least multiple sub-pixels PX, multiple gate lines, and multiple data lines Data. The multiple gate lines may extend along a first direction X, and the multiple data lines Data may extend along a second direction Y. The orthogonal projections of the multiple gate lines and the multiple data lines Data on the substrate intersect to form multiple sub-pixel regions, each sub-pixel region containing one sub-pixel PX. The multiple data lines Data are electrically connected to the multiple sub-pixels PX and can be configured to provide data signals to the multiple sub-pixels PX. The multiple data lines Data may extend to the bonding area B1. The multiple gate lines are electrically connected to the multiple sub-pixels PX and can be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals.

[0040] In some examples, such as Figure 2 As shown, the first direction X can be the extension direction of the gate line in the display area AA (row direction), and the second direction Y can be the extension direction of the data line in the display area AA (column direction). The first direction X and the second direction Y can intersect, and for example, the first direction X and the second direction Y can be perpendicular to each other.

[0041] In some examples, a pixel unit of the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0042] In some examples, the shape of the subpixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three subpixels, the three subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four subpixels, the four subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0043] In some examples, a sub-pixel may include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit may include multiple transistors and at least one capacitor. For example, the pixel driving circuit may be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc.

[0044] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel driving circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include a first electrode, a second electrode, and an organic light-emitting layer located between the first and second electrodes. The first electrode of the light-emitting element can be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited in this respect.

[0045] Figure 3A This is a schematic diagram of a pixel driving circuit. Figure 3A This explanation uses 8T1C as an example. Figure 3A As shown, the pixel driving circuit can be connected to 11 signal lines (Data line, first scan line Gate-P, second scan line Gate-N, first reset line Reset-P, second reset line Reset-H, light emission control line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD, and second power line VSS). The gate lines include: first scan line Gate-P, second scan line Gate-N, first reset line Reset-P, second reset line Reset-H, and light emission control line EM.

[0046] In an exemplary implementation, such as Figure 3AAs shown, the control electrode of the first transistor M1 is connected to the first reset line Reset-P, the first terminal of the first transistor M1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor is connected to the third node N3. The control electrode of the second transistor M2 is connected to the second scan line Gate-N, the first terminal of the second transistor M2 is connected to the first node N1, and the second terminal of the second transistor M2 is connected to the third node N3. The control electrode of the third transistor M3 is connected to the first node N1, the first terminal of the third transistor M3 is connected to the second node N2, and the second terminal of the third transistor M3 is connected to the third node N3. The control electrode of the fourth transistor M4 is connected to the first scan line Gate-P, the first terminal of the fourth transistor M4 is connected to the data line Data, and the second terminal of the fourth transistor M4 is connected to the second node N2. The control electrode of the fifth transistor M5 is connected to the light emission control line EM, the first terminal of the fifth transistor M5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor M5 is connected to the second node N2. The control electrode of the sixth transistor M6 is connected to the light-emitting control line EM. The first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the fourth node N4. The control electrode of the seventh transistor M7 is connected to the second reset line Reset-H. The first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is connected to the fourth node N4. The control electrode of the eighth transistor M8 is connected to the second reset line Reset-H. The first electrode of the eighth transistor M8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor M8 is connected to the second node N2. The first terminal of capacitor C is connected to the first power supply line VDD, and the second terminal of capacitor C is connected to the first node N1.

[0047] In an exemplary embodiment, the first electrode of the light-emitting device is electrically connected to the fourth node N4, and the second electrode of the light-emitting device is connected to the second power line VSS.

[0048] In an exemplary embodiment, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

[0049] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0050] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor M1 to the eighth transistor M8 may include both P-type and N-type transistors.

[0051] In an exemplary embodiment, the first transistor M1 to the eighth transistor M8 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display panel to form a low-temperature polycrystalline oxide (LTPO) display panel leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0052] In an exemplary implementation, such as Figure 3A As shown, the second transistor M2 can be an N-type transistor, and the first transistor M1, the third transistor M3 to the eighth transistor M8 can be P-type transistors.

[0053] In this exemplary embodiment, the first transistor M1, the seventh transistor M7, and the eighth transistor M8 can all be called reset transistors, the second transistor M2 can be called compensation transistors, the second transistor M3 can be called driving transistors, the fourth transistor M4 can be called data writing transistors, and the fifth transistor M5 and the sixth transistor M6 can be called light-emitting control transistors.

[0054] Figure 3B As a kind Figure 3A The operation process of the provided pixel driving circuit. In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0055] In the first stage, P1, also known as the first reset stage, the signal of the second reset line Reset-H is low, while the signals of the first reset line Reset-P, the first scan line Gate-P, the second scan line Gate-N, and the light-emitting control line EM are high. The low signal of the second reset line Reset-H turns on the seventh transistor M7 and the eighth transistor M8. The signal of the second initial signal line INIT2 is provided to the fourth node N4 to initialize (reset) the first electrode of the light-emitting device L, clearing the original charge from the first electrode. The signal of the third initial signal line INIT3 is provided to the second node N2 to initialize (reset) the second node N2, clearing the original charge from the second node N2. During this stage, the third transistor M3 is turned on. The signal of the second scan line Gate-N is high, and the second transistor M2 is turned on. The signal from the second node N2 is supplied to the first node N1 and the third node N3. The first node N1 and the third node N3 are initialized. The signals of the first reset line Reset-P, the first scan line Gate-P, and the light emission control line EM are high-level signals. The first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are disconnected. During this stage, the light-emitting device L does not emit light.

[0056] The second stage, P2, is called the second reset stage. The signal on the first reset line, Reset-P, is low, while the signals on the second reset line, Reset-H, the first scan line, Gate-P, the second scan line, Gate-N, and the light-emitting control line, EM, are high. The low signal on the first reset line, Reset-P, causes the first transistor M1 and the first initial signal line, INIT1, to provide signals to the third node, N3, re-initializing (resetting) N3 and clearing its existing charge. During this stage, the third transistor M3 remains on. The high signal on the second scan line, Gate-N, turns on the second transistor M2. The signal from the third node, N3, is supplied to the first node, N1, continuously initializing it. The high signals on the second reset line, Reset-H, the first scan line, Gate-P, and the light-emitting control line, EM, turn off the fourth transistor, M4, the fifth transistor, M5, the sixth transistor, M6, the seventh transistor, M7, and the eighth transistor, M8. During this stage, the light-emitting device L does not emit light.

[0057] The third stage, P3, is called the data writing stage or threshold compensation stage. The signal on the first scan line, Gate-P, is low, while the signals on the first reset line, Reset-P, the second reset line, Reset-H, the second scan line, Gate-N, and the light control line, EM, are high. The data line, Data, outputs a data voltage. During this stage, the third transistor, M3, remains continuously on. The low signal on the first scan line, Gate-P, turns on the fourth transistor, M4. The high signal on the second scan line, Gate-N, turns on the second transistor, M2. The data voltage output from Data line Data is supplied to the first node, N1, via the on-state fourth transistor M4, the second node, N2, the on-state third transistor M3, and the on-state second transistor M2. The difference between the data voltage output from Data line Data and the threshold voltage of the third transistor M3 is charged into capacitor C. The voltage at the second terminal of capacitor C (first node N1) is Vd - |Vth|, where Vd is the data voltage output from Data line Data and Vth is the threshold voltage of the third transistor M3. The signals of the first reset line Reset-P, the second reset line Reset-H, and the light-emitting control line EM are all high-level signals, and the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are disconnected. During this stage, the light-emitting device L does not emit light.

[0058] In the fourth stage, P4, known as the continuous compensation stage, the signals of the first reset line (Reset-P), the second reset line (Reset-H), the first scan line (Gate-P), the second scan line (Gate-N), and the light-emitting control line (EM) are all high-level signals. The signal of the second scan line (Gate-N) is also high-level, and the second transistor M2 remains continuously on. Meanwhile, the signals of the first scan line (Gate-P), the first reset line (Reset-P), the second reset line (Reset-H), and the light-emitting control line (EM) are all high-level signals, while the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are off. Although the data line (Data) stops writing, the second node N2 still supplies power to the first node N1 through the on-state third transistor M3, the third node N3, and the on-state second transistor M2, continuously compensating for the threshold voltage of the third transistor M3.

[0059] In the fifth stage, P5, also known as the bias stage, the signals of the second scan line Gate-N and the second reset line Reset-H are low-level signals, while the signals of the first reset line Reset-P, the first scan line Gate-P, and the light-emitting control line EM are high-level signals. When the signal of the second scan line Gate-N is low, and the signals of the first scan line Gate-P, the first reset line Reset-P, and the light-emitting control line EM are high, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all off. When the signal of the second reset line Reset-H is low, the seventh transistor M7 and the eighth transistor M8 are turned on. The signal of the third initial signal line INIT3 is written to the second node N2 and the third node N3, and the signal of the second initial signal line INIT2 is written to the fourth node N3. During this stage, the third transistor M3 is in a biased state, and the light-emitting device L does not emit light.

[0060] The sixth stage, P6, is called the light-emitting stage. The signals on the light-emitting control line EM and the second scan line Gate-N are low-level signals, while the signals on the first reset line Reset-P, the second reset line Reset-H, and the first scan line Gate-P are high-level signals. When the light-emitting control line EM is low, the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, driving the light-emitting device L to emit light.

[0061] During the pixel driving circuit operation, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its control electrode and its first electrode. Since the voltage at the first node N1 is Vdata - |Vth|, the driving current of the third transistor M3 is:

[0062] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2 ;

[0063] Where I is the driving current flowing through the third transistor M3, which is also the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power line VDD.

[0064] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product, and improving the overall display effect of the display product.

[0065] Currently, the mainstream image resolution (Pixels Per Inch, PPI) of OLED display panels is between 400 and 450. However, with the maturity of display technology, the market demand for products with higher PPI is becoming increasingly urgent, and the PPI of some display panels has now increased to between 500 and 550. Higher PPI results in less charging time per row of subpixels (for example, the subpixel charging time of some high PPI products is about 1.6us, and the subpixel charging time of some mainstream PPI products is about 2.5us). This can cause problems related to insufficient charging, such as poor low grayscale image quality, poor image uniformity, and color shift.

[0066] Improving the charging time and charging rate of high-PPI products is a pressing issue. Some high-PPI products increase the charging rate by reducing the resistive-capacitive load (RC loading) of signal lines such as data lines and scan lines. However, reducing the RC loading of signal lines is mainly achieved by increasing the thickness of the insulation and planarization layers in the manufacturing process to minimize the overlapping capacitance between signal lines in different layers. This method increases the size of the display panel, which is detrimental to the thinness and lightness of the display panel.

[0067] like Figure 4A As shown, this disclosure provides a display panel including various gate driving circuits and multiple sub-pixels arranged in an array. Each sub-pixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes multiple transistors, wherein:

[0068] Multiple gate driving circuits are configured to output multiple gate driving signals to multiple transistors in a pixel driving circuit. Each gate driving circuit outputs a gate driving signal. The multiple gate driving signals are divided into at least two groups. The high-level voltages of the different groups of gate driving signals are different, and / or the low-level voltages of the different groups of gate driving signals are different.

[0069] The pixel driving circuit is configured to receive multiple gate driving signals and drive the light-emitting element to emit light according to the received multiple gate driving signals.

[0070] The display panel of this disclosure divides multiple gate drive signals into at least two groups, with different high-level voltages and / or different low-level voltages for different groups of gate drive signals. This allows for the adjustment of the high and low levels of the gate drive signals to address the impact of each group of gate drive signals on the charging rate, thereby achieving an optimal combination of charging rate and power consumption.

[0071] In some exemplary embodiments, the gate driving circuit can be an array substrate row driving (Gate Driver On Array, GOA) circuit, and correspondingly, the gate driving signal can be a GOA driving signal.

[0072] For example, Table 1 shows the data voltage Vdata, the voltage value of the first node N1 corresponding to the voltage jump point of the first reset line Reset-P, the voltage value of the first node N1 corresponding to the low level stage of the light emission control line EM, the ratio of the voltage value of the first node N1 corresponding to the low level stage of the light emission control line EM to the data voltage VN1@EM / Data, and the current change rate I for a type of display panel when the grayscale value is 10 and when the grayscale value is 128. In the table, I = (max-min) / (max+min), where max represents the maximum current and min represents the minimum current.

[0073] Table 1

[0074]

[0075]

[0076]

[0077] Based on the data in Table 1, the effect of the VGH voltage of each GOA driving signal on the charging rate of the first node N1 is shown in Table 2.

[0078] Table 2

[0079]

[0080]

[0081] As can be seen from Table 2, the higher the signal voltage of the first scan line Gate-P, the higher the charging rate of the first node N1. Therefore, the high-level voltage VGH_Gate-P of the first scan line Gate-P should be set relatively high, such as 9V to 10V. The lower the high-level voltage VGH_Gate-N of the second scan line Gate-N, the higher the charging rate of the first node N1. Therefore, the high-level voltage VGH_Gate-N of the second scan line Gate-N should be set relatively low, such as 6V to 7V. The high-level voltages of the first reset line Reset-P, the first reset line Reset-H, and the light emission control line EM have little impact on the charging rate of the first node N1 and can be designed according to conventional values, such as 7.5 to 8.5V.

[0082] like Figure 4B As shown, in some technologies, the high and low level signals of multiple GOA driving signals are set to the same signal and can only be changed uniformly. For example, the high level voltage VGH_Gate-P of the first scan line Gate-P, the high level voltage VGH_Gate-N of the second scan line Gate-N, and the high level voltage VGH_EM of the light emission control line EM are the same high level signal. That is, the high level voltage of multiple GOA driving signals can only be set to the same high level voltage value, and the low level voltage of multiple GOA driving signals can also only be set to the same low level voltage value. In this embodiment, multiple GOA driving signals are divided into multiple groups according to their different effects on the charging rate of the first node N1. These multiple groups of GOA driving signals can be set differently and combined as needed to achieve the optimal high and low level voltage configuration. Compared with a unified high and low level signal, individually set high and low level signals can avoid the negative impact of a single GOA driving signal. For example, increasing the high level voltage increases the charging rate of the first node N1 from the perspective of the first scan line Gate-P, but decreases the charging rate of the first node N1 from the perspective of the second scan line Gate-N. By controlling multiple GOA driving signals separately, the optimal combination of charging rate and power consumption can be achieved.

[0083] In some exemplary embodiments, the various GOA driving signals can be divided into three groups. The first group of GOA driving signals includes a first gate control signal provided by the first scan line Gate-P, the second group of GOA driving signals includes a second gate control signal provided by the second scan line Gate-N, and the third group of GOA driving signals includes a first reset control signal provided by the first reset line Reset-P, a second reset control signal provided by the second reset line Reset-N, and a light emission control signal provided by the light emission control line EM.

[0084] In some exemplary embodiments, the high-level voltage of the first group of GOA driving signals is greater than the high-level voltage of the third group of GOA driving signals, and / or, the low-level voltage of the first group of GOA driving signals is greater than the low-level voltage of the third group of GOA driving signals.

[0085] The high-level voltage of the second group of GOA drive signals is less than the high-level voltage of the third group of GOA drive signals, and / or the low-level voltage of the second group of GOA drive signals is less than the low-level voltage of the third group of GOA drive signals.

[0086] In some exemplary embodiments, the high-level voltage of the first set of GOA drive signals is between 9V and 10V; the high-level voltage of the second set of GOA drive signals is between 6V and 7V; and the high-level voltage of the third set of GOA drive signals is between 7.5V and 8.5V.

[0087] For example, the high-level voltage of the first group of GOA drive signals can be 9.5V; the high-level voltage of the second group of GOA drive signals can be 6.5V; and the high-level voltage of the third group of GOA drive signals can be 8V.

[0088] In some exemplary embodiments, the low-level voltage of the first set of GOA drive signals is between -6V and -7V; the low-level voltage of the second set of GOA drive signals is between -8V and -9V; and the low-level voltage of the third set of GOA drive signals is between -7V and -8V.

[0089] For example, the low-level voltage of the first group of GOA drive signals can be -6.5V; the low-level voltage of the second group of GOA drive signals can be -8.5V; and the low-level voltage of the third group of GOA drive signals can be -7.5V.

[0090] In some other exemplary embodiments, the various GOA driving signals can be divided into five groups, wherein the first group of GOA driving signals includes a first gate control signal provided by the first scan line Gate-P, the second group of GOA driving signals includes a second gate control signal provided by the second scan line Gate-N, the third group of GOA driving signals includes a first reset control signal provided by the first reset line Reset-P, the fourth group of GOA driving signals includes a second reset control signal provided by the second reset line Reset-N, and the fifth group of GOA driving signals includes a light emission control signal provided by the light emission control line EM.

[0091] In some other exemplary embodiments, the high-level voltage of the first group of GOA drive signals is greater than the high-level voltage of the third group of GOA drive signals, and / or, the low-level voltage of the first group of GOA drive signals is greater than the low-level voltage of the third group of GOA drive signals.

[0092] The high-level voltage of the second group of GOA drive signals is less than the high-level voltage of the third group of GOA drive signals, and / or the low-level voltage of the second group of GOA drive signals is less than the low-level voltage of the third group of GOA drive signals.

[0093] In some other exemplary embodiments, the high-level voltage of the fourth group of GOA drive signals is equal to or approximately equal to the high-level voltage of the third group of GOA drive signals, and / or, the low-level voltage of the fourth group of GOA drive signals is equal to or approximately equal to the low-level voltage of the third group of GOA drive signals.

[0094] In some other exemplary embodiments, the high-level voltage of the fifth group of GOA drive signals is equal to or approximately equal to the high-level voltage of the third group of GOA drive signals, and / or, the low-level voltage of the fifth group of GOA drive signals is equal to or approximately equal to the low-level voltage of the third group of GOA drive signals.

[0095] In this embodiment of the disclosure, A and B being approximately equal means that the difference between A and B is within a preset difference threshold range. For example, the preset difference threshold can be 1.

[0096] In some other exemplary embodiments, the high-level voltage of the first group of GOA drive signals is between 9V and 10V; the high-level voltage of the second group of GOA drive signals is between 6V and 7V; the high-level voltage of the third group of GOA drive signals is between 7.5V and 8.5V; the high-level voltage of the fourth group of GOA drive signals is between 7.5V and 8.5V; and the high-level voltage of the fifth group of GOA drive signals is between 7.5V and 8.5V.

[0097] For example, the high-level voltage of the first group of GOA drive signals can be 9.5V; the high-level voltage of the second group of GOA drive signals can be 6.5V; the high-level voltage of the third group of GOA drive signals can be 8V; the high-level voltage of the fourth group of GOA drive signals can be 8V; and the high-level voltage of the fifth group of GOA drive signals can be 8V.

[0098] In some other exemplary embodiments, the low-level voltage of the first group of GOA drive signals is between -6V and -7V; the low-level voltage of the second group of GOA drive signals is between -8V and -9V; the low-level voltage of the third group of GOA drive signals is between -7V and -8V; the low-level voltage of the fourth group of GOA drive signals is between -7V and -8V; and the low-level voltage of the fifth group of GOA drive signals is between -7V and -8V.

[0099] For example, the low-level voltage of the first group of GOA drive signals can be -6.5V; the low-level voltage of the second group of GOA drive signals can be -8.5V; the low-level voltage of the third group of GOA drive signals can be -7.5V; the low-level voltage of the fourth group of GOA drive signals can be -7.5V; and the low-level voltage of the fifth group of GOA drive signals can be -7.5V.

[0100] Figure 5A This is a schematic diagram of an equivalent circuit for another pixel driving circuit according to an exemplary embodiment of this disclosure. In other exemplary embodiments, such as... Figure 5A As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and multiple signal lines (data line Data, scan line Gate, reset line Reset, initial signal line INIT, first power supply line VDD, second power supply line VSS, and light emission control line EM).

[0101] In some exemplary embodiments, the control electrode of the first transistor T1 is connected to the reset line Reset, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the first node N1. The control electrode of the second transistor T2 is connected to the scan line Gate, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The control electrode of the fourth transistor T4 is connected to the scan line Gate, the first electrode of the fourth transistor T4 is connected to the data line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2. The control electrode of the fifth transistor T5 is connected to the light emission control line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the light-emitting control line EM. The first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first electrode of the light-emitting element). The control electrode of the seventh transistor T7 is connected to the scan line Gate or the reset line Reset. The first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. The first terminal of the storage capacitor C is connected to the first power supply line VDD, and the second terminal of the storage capacitor C is connected to the first node N1.

[0102] In some exemplary embodiments, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0103] In some exemplary embodiments, the second electrode of the light-emitting element is connected to the second power line VSS, the signal of the second power line VSS is a continuously low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The scan line Gate is the scan signal line in the pixel driving circuit of this display row, and the reset line Reset is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the scan line Gate is Gate(n), and the reset line Reset is Gate(n-1). The reset line Reset of this display row and the scan line Gate in the pixel driving circuit of the previous display row can be the same signal line to reduce the signal lines of the display panel and achieve a narrow bezel of the display panel.

[0104] In some exemplary embodiments, the scan line Gate, the reset line Reset, the light emission control line EM, and the initial signal line INIT all extend horizontally, while the second power line VSS, the first power line VDD, and the data line Data extend vertically.

[0105] In some exemplary embodiments, the light-emitting element may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0106] In this exemplary embodiment, the first transistor T1 and the seventh transistor T7 can both be called reset transistors, the second transistor T2 can be called compensation transistors, the third transistor T3 can be called driving transistors, the fourth transistor T4 can be called data writing transistors, and the fifth transistor T5 and the sixth transistor T6 can be called light-emitting control transistors.

[0107] Figure 5B for Figure 5A The diagram shows a timing diagram of a pixel driving circuit. The following is an example of such a circuit. Figure 5A All seven transistors in the structure are P-type transistors, which are used to... Figure 5B The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. For example, the operation of the pixel driving circuit may include:

[0108] The first stage, A1, is called the reset stage. The Reset signal is low, while the Gate and EM signals are high. When the Reset signal is low, the first transistor T1 is turned on, and the INIT signal is supplied to the first node N1 to initialize the storage capacitor C, clearing the existing data voltage. When the Gate and EM signals are high, the second, fourth, fifth, sixth, and seventh transistors T2, T4, T5, T6, and T7 are turned off; the OLED does not emit light during this stage.

[0109] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signal on the scan line Gate is low, while the signals on the reset line Reset and the light control line EM are high. The data line Data outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal on the scan line Gate turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data line Data to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The sum of the data voltage output from the data line Data and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vdata + Vth, where Vdata is the data voltage output from the data line Data, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The reset signal is high, causing the first transistor T1 to turn off. The light emission control line EM is high, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0110] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting control line EM has a low-level signal, while the scan line Gate and the reset line Reset have high-level signals. When the light-emitting control line EM is low, it turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0111] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode and its first electrode. Since the voltage at the second node N2 is Vdata + Vth, the driving current of the third transistor T3 is:

[0112] I = K * (Vgs - Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdata-Vdd)] 2

[0113] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line Data, and Vdd is the power supply voltage output by the first power line VDD.

[0114] As can be seen from the above formula, the current I flowing through the light-emitting element is independent of the threshold voltage Vth of the third transistor T3, thus eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.

[0115] Based on the above working timing, the pixel circuit eliminates the residual positive charge of the light-emitting element after the last emission, realizes the compensation of the gate voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light-emitting element, and improves the uniformity of the displayed image and the display quality of the display panel.

[0116] In some exemplary embodiments, the various GOA driving signals include a gate control signal for controlling the opening and closing of the data writing transistor, a reset control signal for controlling the opening and closing of the reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor.

[0117] The various GOA driving signals are divided into two groups. The first group includes gate control signals, and the second group includes light emission control signals.

[0118] In some exemplary embodiments, when the reset control signal and the gate control signal are related signals, the first group of GOA drive signals includes the reset control signal;

[0119] When the reset control signal and the gate control signal are unrelated signals, the second group of GOA drive signals includes the reset control signal.

[0120] In some exemplary embodiments, the high-level voltage of the first group of GOA drive signals is greater than the high-level voltage of the second group of GOA drive signals, and / or, the low-level voltage of the first group of GOA drive signals is greater than the low-level voltage of the second group of GOA drive signals.

[0121] In some other exemplary embodiments, the pixel driving circuit includes a driving transistor, a data writing transistor, a reset transistor, a light-emitting control transistor, and a compensation transistor.

[0122] The various GOA driving signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a reset control signal for controlling the opening and closing of the reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor.

[0123] The various GOA driving signals are divided into three groups. The first group includes the first gate control signal, the second group includes the second gate control signal, and the third group includes the reset control signal and the light emission control signal.

[0124] In some exemplary embodiments, the high-level voltage of the first group of GOA driving signals is greater than the high-level voltage of the third group of GOA driving signals, and / or, the low-level voltage of the first group of GOA driving signals is greater than the low-level voltage of the third group of GOA driving signals.

[0125] The high-level voltage of the second group of GOA drive signals is less than the high-level voltage of the third group of GOA drive signals, and / or the low-level voltage of the second group of GOA drive signals is less than the low-level voltage of the third group of GOA drive signals.

[0126] In some exemplary embodiments, the high-level voltage of the first set of GOA drive signals is between 9V and 10V; the high-level voltage of the second set of GOA drive signals is between 6V and 7V; and the high-level voltage of the third set of GOA drive signals is between 7.5V and 8.5V.

[0127] For example, the high-level voltage of the first group of GOA drive signals can be 9.5V; the high-level voltage of the second group of GOA drive signals can be 6.5V; and the high-level voltage of the third group of GOA drive signals can be 8V.

[0128] In some exemplary embodiments, the low-level voltage of the first set of GOA drive signals is between -6V and -7V; the low-level voltage of the second set of GOA drive signals is between -8V and -9V; and the low-level voltage of the third set of GOA drive signals is between -7V and -8V.

[0129] For example, the low-level voltage of the first group of GOA drive signals can be -6.5V; the low-level voltage of the second group of GOA drive signals can be -8.5V; and the low-level voltage of the third group of GOA drive signals can be -7.5V.

[0130] This disclosure also provides a display device, including a display panel.

[0131] The display panel is the same as the display panel provided in any of the foregoing embodiments, and the implementation principle and effect are similar, so it will not be described again here.

[0132] In exemplary embodiments, the display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this application.

[0133] This disclosure also provides a method for driving a display panel, including:

[0134] Multiple gate driving circuits are controlled to output multiple gate driving signals to multiple transistors in a pixel driving circuit. The multiple gate driving signals are divided into at least two groups. The high-level voltages of the gate driving signals in the same group are the same, and the low-level voltages of the gate driving signals in the same group are the same. The high-level voltages of the gate driving signals in different groups are different, and / or the low-level voltages of the gate driving signals in different groups are different.

[0135] In some exemplary embodiments, the pixel driving circuit includes a data writing transistor, a driving transistor, and a light-emitting control transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line to the driving transistor when a gate control signal provided by a scan line is valid; the driving transistor is configured to generate a driving current according to the data voltage; and the light-emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light-emitting element when a light-emitting control signal provided by a light-emitting line is valid, so as to drive the light-emitting element to emit light.

[0136] The various gate drive signals include a gate control signal for controlling the opening and closing of the data writing transistor and a light emission control signal for controlling the opening and closing of the light emission control transistor.

[0137] The various gate drive signals are divided into two groups, wherein the first group of gate drive signals includes the gate control signal, and the second group of gate drive signals includes the light emission control signal.

[0138] In some exemplary embodiments, the high-level voltage of the first group of gate drive signals is greater than the high-level voltage of the second group of gate drive signals, and / or, the low-level voltage of the first group of gate drive signals is greater than the low-level voltage of the second group of gate drive signals.

[0139] In some exemplary embodiments, the pixel driving circuit further includes a reset transistor configured to reset at least one of the following when a reset control signal is active: the anode of the light-emitting element, the first terminal of the driving transistor, and the second terminal of the driving transistor; the plurality of gate driving signals include a reset control signal for controlling the opening and closing of the reset transistor;

[0140] When the reset control signal and the gate control signal are related signals, the first group of gate drive signals includes the reset control signal;

[0141] When the reset control signal and the gate control signal are unrelated signals, the second group of gate drive signals includes the reset control signal.

[0142] In some exemplary embodiments, the pixel driving circuit includes a driving transistor, a data writing transistor, a reset transistor, a light-emitting control transistor, and a compensation transistor. The data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a first gate control signal provided by a first scan line is valid. The driving transistor is configured to generate a driving current based on the data voltage. The light-emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light-emitting element when a light-emitting control signal provided by a light-emitting line is valid, thereby driving the light-emitting element to emit light. The reset transistor is configured to reset at least one of the following when a reset control signal is valid: the anode of the light-emitting element, the first terminal of the driving transistor, and the second terminal of the driving transistor. The compensation transistor is configured to perform threshold compensation on the driving transistor when a second gate control signal provided by a second scan line is valid.

[0143] The various gate drive signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a reset control signal for controlling the opening and closing of the reset transistor, and a light-emitting control signal for controlling the opening and closing of the light-emitting control transistor.

[0144] The various gate drive signals are divided into three groups. The first group of gate drive signals includes the first gate control signal, the second group of gate drive signals includes the second gate control signal, and the third group of gate drive signals includes the reset control signal and the light emission control signal.

[0145] In some exemplary embodiments, the high-level voltage of the first group of gate drive signals is greater than the high-level voltage of the third group of gate drive signals, and / or, the low-level voltage of the first group of gate drive signals is greater than the low-level voltage of the third group of gate drive signals.

[0146] The high-level voltage of the second group of gate drive signals is less than the high-level voltage of the third group of gate drive signals, and / or the low-level voltage of the second group of gate drive signals is less than the low-level voltage of the third group of gate drive signals.

[0147] In some exemplary embodiments, the high-level voltage of the first set of gate drive signals is between 9V and 10V; the high-level voltage of the second set of gate drive signals is between 6V and 7V; and the high-level voltage of the third set of gate drive signals is between 7.5V and 8.5V.

[0148] In some exemplary embodiments, the low-level voltage of the first set of gate drive signals is between -6V and -7V; the low-level voltage of the second set of gate drive signals is between -8V and -9V; and the low-level voltage of the third set of gate drive signals is between -7V and -8V.

[0149] In some exemplary embodiments, the pixel driving circuit includes a driving transistor, a data writing transistor, a first reset transistor, a second reset transistor, a light-emitting control transistor, and a compensation transistor. The data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a first gate control signal provided by a first scan line is valid. The driving transistor is configured to generate a driving current based on the data voltage. The light-emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light-emitting element when a light-emitting control signal provided by a light-emitting line is valid, thereby driving the light-emitting element to emit light. The first reset transistor is configured to reset the second terminal of the driving transistor when the first reset control signal is valid. The second reset transistor is configured to reset the anode of the light-emitting element and the first terminal of the driving transistor when the second reset control signal is valid. The compensation transistor is configured to perform threshold compensation on the driving transistor when a second gate control signal provided by a second scan line is valid.

[0150] The various gate drive signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a first reset control signal for controlling the opening and closing of the first reset transistor, a second reset control signal for controlling the opening and closing of the second reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor.

[0151] The various gate drive signals are divided into five groups, wherein the first group includes the first gate control signal, the second group includes the second gate control signal, the third group includes the first reset control signal, the fourth group includes the second reset control signal, and the fifth group includes the light emission control signal.

[0152] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0153] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0154] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display panel, characterized in that, include: The system includes multiple gate driving circuits and also includes multiple sub-pixels arranged in an array. Each sub-pixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes multiple transistors, wherein: The plurality of gate driving circuits are configured to output a plurality of gate driving signals to a plurality of transistors in the pixel driving circuit. Each gate driving circuit outputs a gate driving signal. The plurality of gate driving signals are divided into at least two groups. The plurality of transistors in the pixel driving circuit includes P-type transistors and N-type transistors. The gate driving signals output to the P-type transistors and the gate driving signals output to the N-type transistors are located in different groups. The high-level voltages and low-level voltages of the gate driving signals in the same group are the same. The high-level voltages of the gate driving signals in different groups are different, and / or the low-level voltages of the gate driving signals in different groups are different. The pixel driving circuit is configured to receive the various gate driving signals and drive the light-emitting element to emit light according to the received various gate driving signals.

2. The display panel according to claim 1, characterized in that, The pixel driving circuit includes a driving transistor, a data writing transistor, a reset transistor, a light-emitting control transistor, and a compensation transistor. The data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a first gate control signal provided by a first scan line is valid. The driving transistor is configured to generate a driving current based on the data voltage. The light-emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light-emitting element when a light-emitting control signal provided by a light-emitting line is valid, thereby driving the light-emitting element to emit light. The reset transistor is configured to reset at least one of the following when a reset control signal is valid: the anode of the light-emitting element, the first terminal of the driving transistor, and the second terminal of the driving transistor. The compensation transistor is configured to perform threshold compensation on the driving transistor when a second gate control signal provided by a second scan line is valid. The compensation transistor is of a different type than the data writing transistor. The various gate drive signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a reset control signal for controlling the opening and closing of the reset transistor, and a light-emitting control signal for controlling the opening and closing of the light-emitting control transistor. The various gate drive signals are divided into three groups. The first group of gate drive signals includes the first gate control signal, the second group of gate drive signals includes the second gate control signal, and the third group of gate drive signals includes the reset control signal and the light emission control signal.

3. The display panel according to claim 2, characterized in that, The high-level voltage of the first group of gate drive signals is greater than the high-level voltage of the third group of gate drive signals, and / or the low-level voltage of the first group of gate drive signals is greater than the low-level voltage of the third group of gate drive signals. The high-level voltage of the second group of gate drive signals is less than the high-level voltage of the third group of gate drive signals, and / or the low-level voltage of the second group of gate drive signals is less than the low-level voltage of the third group of gate drive signals.

4. The display panel according to claim 3, characterized in that, The high-level voltage of the first group of gate drive signals is between 9V and 10V; the high-level voltage of the second group of gate drive signals is between 6V and 7V; and the high-level voltage of the third group of gate drive signals is between 7.5V and 8.5V.

5. The display panel according to claim 3, characterized in that, The low-level voltage of the first group of gate drive signals is between -6V and -7V; the low-level voltage of the second group of gate drive signals is between -8V and -9V; and the low-level voltage of the third group of gate drive signals is between -7V and -8V.

6. The display panel according to claim 1, characterized in that, The pixel driving circuit includes a driving transistor, a data writing transistor, a first reset transistor, a second reset transistor, a light-emitting control transistor, and a compensation transistor. The data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a first gate control signal provided by a first scan line is valid. The driving transistor is configured to generate a driving current based on the data voltage. The light-emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light-emitting element when a light-emitting control signal provided by a light-emitting line is valid, thereby driving the light-emitting element to emit light. The first reset transistor is configured to reset the second terminal of the driving transistor when a first reset control signal is valid. The second reset transistor is configured to reset the anode of the light-emitting element and the first terminal of the driving transistor when a second reset control signal is valid. The compensation transistor is configured to perform threshold compensation on the driving transistor when a second gate control signal provided by a second scan line is valid. The compensation transistor is of a different type than the data writing transistor. The various gate drive signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a first reset control signal for controlling the opening and closing of the first reset transistor, a second reset control signal for controlling the opening and closing of the second reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor. The various gate drive signals are divided into five groups, wherein the first group includes the first gate control signal, the second group includes the second gate control signal, the third group includes the first reset control signal, the fourth group includes the second reset control signal, and the fifth group includes the light emission control signal.

7. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 6.

8. A driving method for a display panel, characterized in that, include: Multiple gate driving circuits are controlled to output various gate driving signals to multiple transistors in a pixel driving circuit. These gate driving signals are divided into at least two groups. The multiple transistors in the pixel driving circuit include P-type transistors and N-type transistors. The gate driving signals output to the P-type transistors and the gate driving signals output to the N-type transistors are located in different groups. Gate driving signals in the same group have the same high-level voltage and the same low-level voltage. Gate driving signals in different groups have different high-level voltages and / or different low-level voltages.

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