Magnetic disk device
By setting parity sectors on the tracks and starting read and write operations before the read/write head reaches the reference position, the problem of data reading difficulties caused by interference between adjacent tracks is solved, and efficient disk rewriting is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2022-06-08
- Publication Date
- 2026-07-31
AI Technical Summary
Adjacent track interference (ATI) makes it difficult to read data on adjacent tracks, and current technology requires multiple disk rotations during rewriting, which is inefficient.
By setting parity sectors on the tracks, the controller can start reading and writing operations before the read/write head reaches the reference position, and rewrite on a track-by-track basis using ATI management information, reducing the number of disk rotations.
It effectively suppressed rewrite time, improved the reliability and efficiency of data reading, and reduced the impact of inter-track interference.
Smart Images
Figure CN116844581B_ABST
Abstract
Description
[0001] This application enjoys priority based on Japanese Patent Application No. 2022-046431 (filed on March 23, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field
[0002] This embodiment relates to a disk drive. Background Technology
[0003] As one of the effects of disk writes on adjacent tracks, Adjacent Track Interference (ATI) is known. Corresponding to the number of writes to a track, the ATI effect on adjacent tracks accumulates, and the data on those tracks soon becomes difficult to read. Therefore, to prevent this, all data on adjacent tracks is rewritten before it becomes difficult to read. Summary of the Invention
[0004] One implementation involves providing a disk device capable of suppressing the time required for rewriting on a track-by-track basis.
[0005] According to one embodiment, a disk drive includes a disk, a read / write head, a buffer memory, and a controller. The disk has a first track. On the first track, starting from a first position, a plurality of first sectors and second sectors are arranged in a write / read direction in a plurality of first sectors and second sectors respectively. Each of the plurality of first sectors stores a data segment, and each second sector stores a parity check for a first error correction. The read / write head performs write / read operations on the first track in the write / read direction. The controller performs a first operation, which is to sequentially read a first data segment, which is a data segment stored therein, from each of the plurality of first sectors, and store a group of the read first data segments in the buffer memory. The controller obtains a first parity check from the group of read first data segments. The controller performs a second operation, which is to write each first data segment from the group of first data segments stored in the buffer memory to a first sector of the read source among the plurality of first sectors, and write the first parity check to a second sector. The timing for the start of the second action is before the timing for the read / write head to reach the first position. Attached Figure Description
[0006] Figure 1 This is a schematic diagram illustrating an example of the configuration of a disk device in an embodiment.
[0007] Figure 2 This is a diagram illustrating an example of the configuration of a disk in an implementation method.
[0008] Figure 3This is a schematic diagram illustrating an example of the configuration of a magnetic track in an implementation method.
[0009] Figure 4 This is a schematic diagram illustrating an example of a data structure for ATI management information in an implementation method.
[0010] Figure 5 This is a diagram used to illustrate an example of the rewriting action of an implementation method.
[0011] Figure 6 This is a flowchart illustrating an example of an ATI counting operation performed by a controller in an implementation method.
[0012] Figure 7 This is a flowchart illustrating an example of an action performed by a controller to detect the track of the object to be rewritten in an implementation.
[0013] Figure 8 This is a flowchart illustrating an example of a rewriting action in an implementation method.
[0014] Figure 9 This is a flowchart illustrating an example of a track reading operation in an implementation method.
[0015] Figure 10 This is a flowchart illustrating an example of a track write operation in an implementation method.
[0016] Label Explanation
[0017] 1 Disk drive, 2 Host, 11 Disk, 12 Spindle motor, 13 Ramp, 15 Actuator arm, 21 Motor driver IC, 22 Head, 22r Read chip, 22w Write chip, 23 HDC, 24 Head IC, 25 RWC, 26 Processor, 27 RAM, 28 FROM, 29 Buffer memory, 30 Controller, 41 Servo area, 42 Data area, 50 Track, 271 ATI management information. Detailed Implementation
[0018] The disk device according to the embodiments will be described in detail below with reference to the accompanying drawings. However, this invention is not limited to these embodiments.
[0019] (Implementation Method)
[0020] Figure 1 This is a schematic diagram illustrating an example of the configuration of the disk device 1 in an embodiment.
[0021] Disk device 1 is connected to host 2. Disk device 1 can receive access commands such as write commands and read commands from host 2.
[0022] The disk drive 1 includes a disk 11 on which a magnetic layer is formed on its surface. The disk drive 1 writes data to the disk 11 and reads data from the disk 11 according to access commands.
[0023] Data writing and reading are performed via the read / write head 22. In addition to the disk 11, the disk device 1 also includes a spindle motor 12, a ramp 13, an actuator arm 15, a voice coil motor (VCM) 16, a motor driver IC (Integrated Circuit) 21, a read / write head 22, a hard disk controller (HDC) 23, a head IC 24, a read / write channel (RWC) 25, a processor 26, RAM 27, FROM (Flash Read Only Memory) 28, and a buffer memory 29.
[0024] The disk 11 is rotated at a predetermined speed by a spindle motor 12 mounted coaxially. The spindle motor 12 is driven by a motor driver IC 21.
[0025] The processor 26 controls the rotation of the spindle motor 12 and the VCM 16 via the motor driver IC 21.
[0026] The read / write head 22 writes and reads information from the disk 11 using its write core 22w and read core 22r. The read / write head 22 is mounted at the front end of the actuator arm 15. The read / write head 22 moves radially across the disk 11 via the VCM 16. Furthermore, multiple copies of either the write core 22w or the read core 22r can be provided for a single read / write head 22.
[0027] When the disk 11 stops rotating, the read / write head 22 moves onto the ramp 13. The ramp 13 is configured to hold the read / write head 22 in a position where it has left the disk 11.
[0028] During a read operation, head IC24 amplifies the signal read by head 22 from disk 11 and outputs it to RWC25. Conversely, during a write operation, head IC24 amplifies the signal corresponding to the data to be written from RWC25 and provides it to head 22.
[0029] HDC23 controls data transmission and reception between the HDC23 and the host 2 via the I / F bus, and controls the buffer memory 29, etc.
[0030] The buffer memory 29 is used as a buffer for data exchanged between the host 2 and the host 2. For example, the buffer memory 29 is used to temporarily store data for write operations or data read from the disk 11.
[0031] The buffer memory 29 is composed of volatile memory capable of high-speed operation. The type of memory constituting the buffer memory 29 is not limited to a specific type. For example, the buffer memory 29 can be composed of DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or a combination thereof. Furthermore, the buffer memory 29 can also be composed of any non-volatile memory.
[0032] RWC25 modulates the write object data provided by HDC23 using error correction coding and other methods, and provides the modulated data to head IC24. Additionally, RWC25 demodulates the signal read from disk 11 and provided by head IC24, including error correction processing, and outputs the demodulated signal as digital data to HDC23.
[0033] The processor 26 is, for example, a CPU (Central Processing Unit). RAM 27, FROM (Flash Read Only Memory) 28, and buffer memory 29 are connected to the processor 26.
[0034] FROM 28 is a non-volatile memory. Firmware (program data) and various operational parameters are stored in FROM 28. Additionally, the firmware can also be stored on disk 11.
[0035] RAM 27 is composed of, for example, DRAM, SRAM, or a combination thereof. RAM 27 is used by the processor 26 as its working memory. RAM 27 is used as an area for loading firmware and as an area for temporarily storing various management data.
[0036] The processor 26 performs overall control of the disk device 1 according to the firmware stored in the FROM 28 or the disk 11. For example, the processor 26 loads the firmware from the FROM 28 or the disk 11 into the RAM 27, and executes the control of the motor driver IC 21, head IC 24, RWC 25, HDC 23, etc. according to the loaded firmware.
[0037] The configuration including HDC23, RWC25, and processor 26 can also be regarded as a controller 30 that controls the operation of disk device 1. Controller 30 may also include other elements (such as RAM27, FROM28, or buffer memory 29, etc.).
[0038] Alternatively, the firmware program can also be stored on disk 11. Furthermore, some or all of the functions of processor 26 can be implemented using hardware circuitry such as FPGA (Field-Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).
[0039] Furthermore, the number of disks 11 included in the disk device 1 is not limited to one. Additionally, the disk device 1 may have a number of actuator arms 15 and read / write heads 22 corresponding to the number of disks 11. Furthermore, when the disk device 1 has multiple read / write heads 22, these multiple heads 22 can be moved as a single unit, or they can be configured into multiple groups capable of moving independently.
[0040] Figure 2 This is a diagram illustrating an example of the configuration of the disk 11 in an embodiment. Servo data used for positioning the read / write head 22 is written into the magnetic layer formed on the surface of the disk 11, for example, by servo writing or by self-servo writing (SSW).
[0041] exist Figure 2 The diagram shows a radially arranged servo region 41 as an example of a servo region configuration for writing servo data. A data region 42, where data can be written, is defined between two servo regions 41 in the circumferential direction. Multiple concentric tracks 50 are arranged in the radial direction of the disk 11. On each track 50, multiple sectors, each containing data of a predetermined size (sector size), are arranged within the data region 42.
[0042] The servo data includes a servo marker, Gray code, a burst pattern, and a postcode. The servo marker indicates the start of the servo data. The Gray code includes an ID (track number) for identifying each track 50 on disk 11 and an ID (servo sector number) for identifying each servo sector (servo area 41) on track 50. The burst pattern is used to detect the deviation of the track's position from the center position indicated by the track number contained in the Gray code. The track number contained in the Gray code is provided, for example, as an integer value. By demodulating the burst pattern, the offset below the decimal point based on the position indicated by the track number can be obtained. That is, by demodulating the burst pattern, the current position of the head 22 in the radial direction can be obtained. The postcode is data used to correct for deviations in position of the track 50 shape defined by the Gray code and burst pattern from the ideal track 50 shape.
[0043] When writing data to or reading data from the disk 11, the controller 30 performs the positioning of the head 22, that is, seek control and tracking control, based on the servo data read by the head 22 from the servo area 41.
[0044] Figure 3 This is a schematic diagram illustrating an example of the configuration of a track 50 in an embodiment. The servo region 41 is omitted from this diagram. Additionally, the write / read direction is illustrated in this diagram. The write / read direction is the direction in which the read / write head 22 moves relative to the track 50 as the disk 11 rotates. The read / write head 22 writes or reads data from each track 50 in the write / read direction.
[0045] Each sector on track 50 is identified by its sector number. The sector with sector number x is recorded as sector #x. Figure 3 In the example shown, track 50 has 11 sectors, from sector #0 to sector #10.
[0046] The data written to each sector contains error correction codes. The RWC25 is capable of performing sector-by-sector error correction using error correction codes on data read from a sector. This sector-by-sector error correction is an example of the second type of error correction.
[0047] The error correction coding method used for sector-level error correction is not limited to a specific method. In one example, a low-density parity-check code is applied as the error correction coding method for sector-level error correction.
[0048] The 11 sectors are arranged sequentially by sector number in the write / read direction, starting from the reference position. In other words, the reference position is the location within track 50 where the sector with the smallest sector number is located. Furthermore, the reference position is an example of position 1. In this specification, the start and end are defined based on the reference position and the write / read direction.
[0049] For example, regarding the interval from when the read / write head 22 passes the reference position to when it passes the reference position again, i.e., sector #0 to sector #10, the sector that the read / write head 22 passes through first, i.e., sector #0, is recorded as the beginning sector. Regarding sectors #0 to sector #10, the sector that the read / write head 22 passes through last, i.e., sector #10, is recorded as the end sector.
[0050] Additionally, the position where the read / write head 22 begins to pass through the sector is recorded as the beginning of the sector. The position where the read / write head 22 ends to pass through the sector is recorded as the end of the sector.
[0051] The last sector, #10, is designated as the sector for storing parity checks. That is, the writing of a unit on track 50 is performed as follows: First, data is written in sector #0 to sector #9 in the order of sector numbers. Then, parity checks generated based on the data groups written in sectors #0 to #9 are written to the last sector, #10, of track 50.
[0052] The parity check written in sector #10 protects the data groups written in sectors #0 to #9 from incorrect parity checks. That is, the parity check written in sector #10 protects data on a track-by-track basis. Error correction using the parity check written in sector #10 is recorded as track-by-track error correction. Track-by-track error correction is an example of first-order error correction.
[0053] Sectors that store data, such as sectors #0 to #9, are recorded as data sectors. Data written in data sector #x is sometimes recorded as data #x. Data #x is an example of a data segment. Sectors that store parity checks, such as sector #10, are recorded as parity sectors.
[0054] The error correction coding used for track-level error correction is not limited to a specific method. In one example, parity is generated by performing an XOR operation on each bit of data #0 through #9.
[0055] As mentioned above, when data is written to a track 50 (referred to as track 1 50), the adjacent track 50 (track 2 50) is affected by ATI (Automatic Time Injection). The ATI effect on track 2 50 accumulates accordingly with the number of writes to track 1 50. When the ATI effect on track 2 50 becomes too large, it becomes difficult to read the data stored on track 2 50.
[0056] The controller 30 rewrites the data before each track 50 becomes difficult to read due to the influence of ATI.
[0057] The controller 30 uses, for example, ATI management information 271 to infer the extent of ATI influence on each track 50.
[0058] Figure 4 This is a schematic diagram illustrating an example of the data structure of ATI management information 271 in an implementation method.
[0059] ATI management information 271 has a data structure that records ATI counts for each track 50. When data is written to a track 50, the controller 30 increments the ATI counts of tracks 50 near the destination track 50. The increment value is determined by the designer using any method. In one example, the closer the track 50 is to the destination, the larger the increment value. That is, the ATI count represents the degree of ATI influence accumulated on the corresponding track 50.
[0060] The controller 30 compares the ATI count of each track 50 with a threshold. If an ATI count exceeds the threshold, the controller 30 rewrites the track 50 corresponding to that ATI count. After rewriting, the controller 30 resets the ATI count of the rewritten track 50.
[0061] Furthermore, the threshold for comparison with the ATI count can either be a common value applied across all tracks 50, or it can be set individually for each track. Additionally, the controller 30 can change the threshold during operation.
[0062] For example, if a track 50 (referred to as track 3 50) is written on a track-by-track basis, track 3 50 becomes a state where all data is protected by parity check. That is, parity-based protection is effective.
[0063] Then, when the controller 30 performs an overlay write to a portion of the data sectors of track 50, track 50 becomes a state where all data is not protected by parity. That is, parity-based protection becomes invalid.
[0064] Regarding the impact on ATI, track 50 with parity-based protection invalid is more vulnerable than track 50 with parity-based protection valid. Therefore, controller 30 can also use a smaller threshold value when parity-based protection is invalid compared to when parity-based protection is valid.
[0065] Specifically, after writing to track 50 on a track-by-track basis, controller 30 uses a first threshold to compare the ATI count corresponding to track 50. Furthermore, when overlapping writes are performed on a portion of the data sectors of track 50, the parity-based protection of track 50 becomes invalid. Therefore, controller 30 uses a second threshold, smaller than the first threshold, to compare the ATI count corresponding to track 50. Thus, even if the parity-based protection becomes invalid, it prevents data stored on track 50 from becoming difficult to read due to ATI issues.
[0066] Furthermore, the threshold modification method described above is just one example. The threshold can be modified using any method, or it can remain unchanged.
[0067] The controller 30 performs a track-by-track rewrite on tracks 50 that have exceeded the ATI count threshold. The track-by-track rewrite is recorded as a rewrite action.
[0068] Here, a technique compared to the implementation method is described. According to the technique compared to the implementation method, during the rewrite operation, the controller positions the read head on the track to be rewritten and sequentially reads data and parity checks starting from the reference position of the track to be rewritten. When the reading of data and parity checks from the track to be rewritten is completed, the controller positions the write head on the track to be rewritten and sequentially writes data and parity checks starting from the reference position of the track to be rewritten.
[0069] According to the comparative example, both track-based reads and track-based writes begin accessing from the reference position of the track being rewritten. Therefore, in addition to each track-based read and write requiring one revolution, there is also one disk revolution between each track-based read and write operation. Thus, a rewrite operation requires at least three disk revolutions.
[0070] In this implementation, the controller 30 begins writing track by track without waiting for the read / write head 22 (more precisely, the write core 22w) to reach the reference position. That is, the timing for starting track-by-track writing is before the timing for the read / write head 22 to reach the reference position. Therefore, compared to the comparative example, the rewrite operation is completed in a shorter time.
[0071] From now on, read operations on a track-by-track basis included in a rewrite operation will be recorded as track read operations. Write operations on a track-by-track basis included in a rewrite operation will be recorded as track write operations.
[0072] Figure 5 This is a diagram illustrating an example of a rewrite operation in an implementation. The diagram shows the position of the read / write head 22 during the rewrite operation and the temporal progression of the control category of the controller 30 during the rewrite operation. Furthermore, "#x" (where x is an integer from 0 to 9) representing the position of the read / write head 22 signifies sector #x of the data sector. Additionally, "P" representing the position of the read / write head 22 signifies the parity sector, i.e., sector #10. In the following description, the track 50 to which the rewrite operation is intended will be referred to as the target track 50.
[0073] When the read chip 22r is positioned towards the target track 50 and readiness is achieved, the controller 30 begins the track reading operation from the sector initially reached by the read head 22 without waiting for it to reach the reference position. That is, the timing of the start of the track reading operation is the timing before the read head 22 reaches the reference position. Figure 5 In the example shown, the track reading operation begins at moment t1 when the read head 22 reaches the beginning of sector #2.
[0074] In addition, the preparation for reading includes various processes required at the start of reading, such as setting parameters related to the current of the magnetic head 22.
[0075] The controller 30 reads sectors #2, #3, #4, #5, #6, #7, #8, #9, and the parity sector in this order. The read / write head 22 reaches the reference position, which is the beginning of sector #0 (in other words, the end of the parity sector). The controller 30 then continues the track reading operation, reading sectors #0 and #1 in this order.
[0076] At time t2, based on time t1 when the track read operation began, disk 11 has completed one revolution, and all data and parity checks stored in the target track 50 have been read. That is, the track read operation has ended.
[0077] When the track read operation is completed, the controller 30 positions the write core 22w of the read / write head 22 on the target track 50 and prepares for writing. The writing preparation includes various processes required to begin writing, such as setting parameters related to the current of the read / write head 22.
[0078] During the positioning and writing preparation of the write drive 22w, the disk 11 continues to rotate. When the positioning and writing preparation of the write drive 22w is complete, the controller 30 does not wait for the head 22 to reach the reference position and begins the track writing operation from the sector initially reached by the head 22. Figure 5 In the example shown, starting from time t2, disk 11 rotates 2 sectors, and the track write operation begins at time t3 when the read / write head 22 reaches the beginning of sector #4.
[0079] The controller 30 writes to sectors #4, #5, #6, #7, #8, #9, and the parity sector in this order, until the read / write head 22 reaches the reference position, which is the beginning of sector #0 (in other words, the end of the parity sector). Then, the controller 30 continues the track writing operation, writing to sectors #0, #1, #2, and #3 in this order.
[0080] At time 52, based on time t3 when the track write operation began, disk 11 completes one revolution, finishing the writing of all data and parity checks on the target track 50. In other words, the track write operation ends, and the rewrite operation ends.
[0081] exist Figure 5 In the example shown, the rewrite operation begins at time t1 and ends at time t4. The rewrite operation concludes during the two revolutions and two sector rotations of disk 11. Compared to a comparative example where the rewrite operation requires three disk revolutions, the time required for the rewrite operation is reduced.
[0082] In this way, once the read operation is complete, the write operation begins. As a result, the time required for the rewrite operation is significantly reduced.
[0083] Next, for the implementation Figure 5 The control of the controller 30 for the actions shown will be explained.
[0084] Figure 6 This is a flowchart illustrating an example of an ATI counting operation performed by the controller 30 in an implementation embodiment.
[0085] When the controller 30 writes data to a track 50 (S101), it increments the ATI count of tracks 50 near the destination track 50 (S102). In S102, the controller 30 can increment the ATI count of tracks 50 adjacent to the destination track 50 on both sides in the radial direction, or it can increment the ATI count of all tracks 50 within a predetermined range in the radial direction centered on the destination track 50. The amount added in each increment can be fixed or vary depending on the distance from the destination track 50.
[0086] The ATI counting operation ends via S102. Furthermore, the controller 30 executes [the following step] each time data is written. Figure 6 The series of actions shown.
[0087] Figure 7 This is a flowchart illustrating an example of an action performed by the controller 30 to detect the track 50 of the object to be rewritten in an implementation.
[0088] The controller 30 refers to the ATI management information 271 to determine whether there is a track 50 with an ATI count exceeding the threshold (S201). If there is a track 50 with an ATI count exceeding the threshold (S201: Yes), a rewrite operation is performed on that track 50 (S202). After the rewrite operation, the controller 30 resets the ATI count of the track 50 to "0" (S203). Then, the operation of detecting the track 50 to be rewritten ends.
[0089] If no track 50 has an ATI count exceeding the threshold (S201: No), the action of detecting track 50 of the rewrite target ends.
[0090] In addition, controller 30 executes repeatedly Figure 7 The series of actions shown. For example, the controller 30 performs the above actions when the disk device 1 is not processing commands from the host 2. Alternatively, the controller 30 performs the above actions at predetermined intervals. Alternatively, the controller 30 performs the above actions whenever a predetermined amount of data is written to the disk 11.
[0091] Figure 8 This is a flowchart illustrating an example of a rewriting action in an implementation method.
[0092] The controller 30 positions the read core 22r of the magnetic head 22 on the target track 50 (i.e., the track 50 to be rewritten) (S301). Furthermore, the target track 50 is an example of the first track.
[0093] When the read core 22r is positioned and ready for reading, the controller 30 begins the track reading operation without waiting for the read core 22r to reach the reference position (S302). Furthermore, the track reading operation is an example of the first operation.
[0094] When the track reading operation is completed (S303), the controller 30 positions the write core 22w of the magnetic head 22 on the target track 50 (S304).
[0095] When the writing die 22w is positioned and writing is ready, the controller 30 begins the track writing operation without waiting for the writing die 22w to reach the reference position (S305). Furthermore, the track writing operation is an example of the second operation.
[0096] When the track write operation is completed, the rewrite operation ends.
[0097] Figure 9 This is a flowchart illustrating an example of a track reading operation in an implementation method.
[0098] During the track read operation, the loop process of S401 to S409 is repeatedly executed until the disk 11 completes one revolution.
[0099] In this loop process, the controller 30 determines whether the read chip 22r is located in a data sector (S401). If the read chip 22r is located in a data sector (S401), the controller 30 reads data from the data sector through the read chip 22r (S402) and performs sector-based error correction on the read data through the RWC25 (S403).
[0100] If the sector-based error correction has been successful (S404: Yes), the controller 30 uses the read data to perform a new parity check operation (S405). The new parity check is an example of the first parity check.
[0101] During track reading, controller 30 uses data read from all data sectors to obtain parity. In one example, parity is obtained by XORing the data read from all data sectors. Controller 30 performs the XOR operation whenever data is read successfully from a data sector (i.e., whenever error correction on a sector-by-sector basis for the read data is successful).
[0102] Next, in S405, the controller 30 saves the read data to the buffer memory 29 (S406). Then, control is transferred to S409, which will be described later.
[0103] If sector-level error correction fails (S404: No), that is, if data cannot be read normally from the data sector, controller 30 skips the processing of S405 and S406 and transfers control to S409. Data that was not read normally from the data sector (i.e., data whose sector-level error correction failed) is not used in the XOR operation until it is corrected by track-level error correction as described later.
[0104] If the read chip 22r is not located in a data sector (S401: No), the controller 30 determines whether the read chip 22r is located in a parity sector (S407). If the read chip 22r is not located in a parity sector (S407: No), control is transferred to S409.
[0105] If the read chip 22r is located in the parity sector (S407: Yes), the controller 30 reads the parity from the parity sector (S408). Then, control is transferred to S409.
[0106] Furthermore, error correction can be performed on a track-by-track basis only if the parity value read in S408 is the same as the parity value obtained through the new operation in S405 and S415 (described later). Therefore, there are cases where the parity value read in S408 differs from the parity value obtained through the new operation in S405 and S415 (described later). The parity value read in S408 is recorded as the old parity value. The old parity value is an example of the second parity check.
[0107] In S409, the controller 30 determines whether the disk 11 has completed one revolution since the start of the track read operation. If the disk 11 has not completed one revolution (S409: No), control is transferred to S401.
[0108] After disk 11 has completed one rotation (S409: Yes), controller 30 determines whether there is data for which error correction has failed on a sector-by-sector basis (S410). That is, controller 30 determines whether error correction has failed on a sector-by-sector basis when reading from any data sector.
[0109] If there is data where error correction has failed on a sector-by-sector basis (S410: Yes), the controller 30 determines whether the old parity check is valid (S411). If the old parity check is valid (S411: Yes), the controller 30 performs track-by-track error correction in order to correct the data where error correction has failed on a sector-by-sector basis (S412).
[0110] Next, the controller 30 uses the data corrected by error correction on a track-by-track basis to perform a calculation to obtain a new parity check (S413). Thus, a new parity check can be obtained based on the data read from all data sectors.
[0111] The controller 30 stores the new parity check in the buffer memory 29 (S414).
[0112] Then, the controller 30 saves the data corrected by error correction on a track-by-track basis in the buffer memory 29 (S415), and the track write operation ends.
[0113] If the old parity check is invalid (S411: No), the controller 30 cannot obtain the correct data even if it performs error correction on a track-by-track basis. Therefore, the controller 30 performs the predetermined process (S417), and the track write operation ends.
[0114] The pre-defined processing can be arbitrarily designed by the designer. For example, the controller 30 can also re-perform a read operation for data sectors that failed to be read normally. Alternatively, the controller 30 can also re-perform a track read operation.
[0115] If there is no data where error correction has failed on a sector-by-sector basis (S410: No), a new parity check is obtained through the processing of the last executed S405. The controller 30 saves the new parity check in the buffer memory 29 (S416), and the track write operation ends.
[0116] pass Figure 9 The process shown involves sequentially reading data from each data sector, and the read data sets are stored in buffer memory 29. This process is completed within one revolution of disk 11.
[0117] Figure 10 This is a flowchart illustrating an example of a track write operation in an implementation method.
[0118] During the track write operation, the loop process of S501 to S505 is repeatedly executed until the disk 11 completes one revolution.
[0119] In this loop process, the controller 30 determines whether the write chip 22w is located in the data sector (S501). If the write chip 22w is located in the data sector (S501: Yes), the controller 30 writes the data read from the data sector and stored in the buffer memory 29 into the data sector (S502). Then, control is transferred to S505.
[0120] If the write chip 22w is not located in a data sector (S501: No), the controller 30 determines whether the write chip 22w is located in a parity sector (S503). If the write chip 22w is not located in a parity sector (S503: No), control is transferred to S505.
[0121] When the writing chip 22w is located in the parity sector (S503: Yes), the controller 30 writes the new parity data obtained through the track read operation and stored in the buffer memory 29 into the parity sector (S504). Then, control is transferred to S505.
[0122] If the chip 22w is not located in the parity sector (S503: No), control is transferred to S505.
[0123] In S505, the controller 30 determines whether the disk 11 has completed one revolution since the start of the track write operation. If the disk 11 has not completed one revolution (S505: No), control is transferred to S501.
[0124] With disk 11 having completed one revolution (S505: Yes), the track write operation is complete.
[0125] pass Figure 10The process shown involves writing data stored in the buffer memory 29 to the data sector of the read source, and writing new parity data to the parity sector. This process is completed within one revolution of the disk 11.
[0126] Furthermore, in the example described above, the controller 30 begins the track reading operation without waiting for the read / write head 22 to reach the reference position. The track reading operation can also begin at a timed start when the read / write head 22 reaches the reference position. Even if the controller 30 is configured to begin the track reading operation at a timed start when the read / write head 22 reaches the reference position, subsequent track writing operations can begin once the write core 22w is positioned and ready. This reduces the time required for rewriting operations.
[0127] In addition, Figure 9 In the track read operation shown, in S414 or S416, the new parity check is stored in buffer memory 29. Furthermore, in... Figure 10 In the track write operation shown, the new parity check stored in buffer memory 29 is written to the parity sector. The new parity check does not necessarily have to be stored in buffer memory 29. For example, it could be that the new parity check is calculated in RWC25 during a track read operation and stored in RWC25, and then in a subsequent track write operation, the new parity check stored in RWC25 is written to the parity sector.
[0128] Thus, according to the implementation method, the controller 30 performs a track read operation, acquires a new parity check, and performs a track write operation after the track read operation during the rewrite operation. During the track read operation, the controller 30 sequentially reads data from each data sector and stores the read data sets in the buffer memory 29. The controller 30 acquires a new parity check from the read data sets. During the track write operation, the controller 30 writes each data set stored in the buffer memory 29 to the data sector of the read source and writes the new parity check to the parity sector. The controller 30 begins the track write operation without waiting for the read / write head 22 to reach the reference position.
[0129] As a result, the time required to rewrite the action is suppressed.
[0130] In addition, according to the implementation, the controller 30 performs a new parity check operation whenever it reads data from the data sector during a track read operation.
[0131] Therefore, the controller 30 can obtain a new parity check at the time when the track reading action ends.
[0132] In addition, after obtaining all the data track data from the target track 50, the controller 30 can also calculate a new parity check and then start the track writing operation.
[0133] Furthermore, according to the embodiment, during track reading, the controller 30 reads the old parity check when the read / write head 22 passes through the parity sector. Whenever the controller 30 reads data from a data sector, it performs sector-by-sector error correction on that data. If the sector-by-sector error correction is successful, the data is stored in the buffer memory 29. If the sector-by-sector error correction fails, the controller 30 performs track-by-track error correction using the old parity check, and stores the corrected data in the buffer memory.
[0134] Therefore, even if sector-based error correction fails, data can still be read normally as long as the old parity check is valid.
[0135] Furthermore, according to the embodiment, the controller 30 completes the track read operation during the period when the disk 11 rotates once from the start of the track read operation. After the track read operation is completed, the controller 30 begins the track write operation without waiting for the read / write head 22 to reach the reference position. The controller 30 completes the track write operation during the period when the disk 11 rotates once from the start of the track write operation.
[0136] Therefore, the controller 30 can complete the rewrite operation in a shorter time than the disk 11 takes to rotate three times.
[0137] Furthermore, according to the implementation method, the controller 30 estimates the degree of influence of ATI, and the track 50 that has an influence of ATI exceeding a threshold performs a rewrite operation.
[0138] Furthermore, the trigger for initiating a rewrite action does not necessarily have to be based on the degree of ATI's influence. Designers can arbitrarily set the conditions under which controller 30 performs a rewrite action.
[0139] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.
Claims
1. A disk drive, comprising: The disk has a first track, which is configured with multiple first sectors and multiple second sectors in the write / read direction starting from the first position. Each of the multiple first sectors stores a data segment, and the second sector stores parity checks for first error correction. A magnetic head that performs write / read operations on the first track in the write / read direction; Buffer memory; as well as Controller The controller The first action is to sequentially read the first data segment from each of the plurality of first sectors, which are stored therein, and to store the group of read first data segments in the buffer memory. Obtain the first parity check from the group of the first data segment read. Perform the second action, which is to write each of the first data segments in the group of the first data segments stored in the buffer memory to the first sector of the read source in the plurality of first sectors, and to write the first parity check to the second sector. The timing of the start of the second action is before the timing of the read head reaching the first position.
2. The disk drive according to claim 1, The timing for the start of the first action is prior to the timing of the magnetic head reaching the first position.
3. The disk drive according to claim 1 or 2, In the first action, the controller performs the operation of obtaining the first parity check whenever a first data segment is read.
4. The disk drive according to claim 1 or 2, In the first action, the controller... When the read / write head passes through the second sector, the second parity check, which is stored in the second sector, is read. Each time a first data segment is read, the second error correction is performed on the first data segment. If the second error correction is successful, the first data segment is saved in the buffer memory. If the second error correction fails, the first error correction using the second parity check is performed on the first data segment, and the first data segment after the first error correction is saved in the buffer memory.
5. The disk drive according to claim 1 or 2, The controller completes the second action during the period when the disk completes one revolution from the start of the second action.
6. The disk drive according to claim 1 or 2, The controller completes the first action during the period when the disk completes one revolution from the start of the first action.
7. The disk drive according to claim 1 or 2, The disk is provided with a plurality of second tracks, including the first track. The controller estimates the extent of adjacent track interference (ATI) accumulated in each second track, and executes the first action and the second action if the extent of ATI accumulated in the first track exceeds a threshold.