Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device that operates properly. The semiconductor storage device of the embodiments includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of first semiconductor layers and a plurality of first via electrodes. The peripheral circuit includes a plurality of first nodes provided corresponding to the plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address selection circuit that causes one of the plurality of first nodes to be in conduction with the charging circuit or the discharging circuit in accordance with an input address signal, a plurality of first transistors each provided on a current path between two of the plurality of first nodes, and a plurality of amplification circuits provided corresponding to the plurality of first via electrodes and including an input terminal connected to any one of the plurality of first nodes and an output terminal connected to any one of the plurality of first via electrodes.

Description

[0001] [Reference to related applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-046520 (filed on March 23, 2022). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] Semiconductor memory devices are known to have multiple memory cells stacked in a direction intersecting with the surface of a substrate. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device that operates properly.

[0006] One embodiment of a semiconductor memory device includes a memory cell array and peripheral circuitry. The memory cell array includes a plurality of first semiconductor layers and a plurality of first via electrodes. The plurality of first semiconductor layers extend in a first direction and are arranged in a second direction intersecting the first direction. The plurality of first via electrodes are respectively disposed between two adjacent first semiconductor layers in the second direction. The peripheral circuitry includes a plurality of first nodes, a charging circuit, a discharging circuit, an address selection circuit, a plurality of first transistors, and a plurality of amplifier circuits. The plurality of first nodes are correspondingly disposed to the plurality of first via electrodes. The charging circuit charges the plurality of first nodes. The discharging circuit discharges the plurality of first nodes. The address selection circuit is disposed on a current path between the plurality of first nodes and the charging circuit, or on a current path between the plurality of first nodes and the discharging circuit, and, based on an input address signal, enables one of the plurality of first nodes to be connected to the charging circuit or the discharging circuit. The plurality of first transistors are respectively disposed on a current path between two of the plurality of first nodes. Multiple amplifier circuits are configured corresponding to multiple first through-hole electrodes, and each circuit has an input terminal connected to any one of the multiple first nodes and an output terminal connected to any one of the multiple first through-hole electrodes. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing a portion of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic three-dimensional diagram showing a portion of the structure of the semiconductor memory device.

[0009] Figure 3 This indicates the subarray MCA S A schematic top view consisting of a portion of it.

[0010] Figure 4 It is a schematic three-dimensional diagram representing a part of the array structure AS.

[0011] Figure 5 It is a schematic circuit diagram representing a part of the array structure AS.

[0012] Figure 6 It is a schematic top view representing a portion of the array structure AS.

[0013] Figure 7 It is a schematic cross-sectional view representing a portion of the array structure AS.

[0014] Figure 8 It is a schematic cross-sectional view representing a portion of the array structure AS.

[0015] Figure 9 It represents transistor layer L T A schematic cross-sectional view consisting of a portion of it.

[0016] Figure 10 It represents transistor layer L T A schematic cross-sectional view consisting of a portion of it.

[0017] Figure 11 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment.

[0018] Figure 12 This is a schematic circuit diagram representing a portion of the semiconductor memory device.

[0019] Figure 13 This is a schematic circuit diagram representing a portion of the semiconductor memory device.

[0020] Figure 14 This indicates the drive circuit DRV. SWL A schematic top view of the structure.

[0021] Figure 15 This indicates the drive circuit DRV. SWL A schematic side view of its composition.

[0022] Figure 16 This indicates the drive circuit DRV. SWL A schematic cross-sectional view of its composition.

[0023] Figure 17 It represents the decoding circuit DEC. SG A schematic circuit diagram of the structure.

[0024] Figure 18It is a schematic top view used to illustrate the read operation of the semiconductor memory device.

[0025] Figure 19 It is a schematic top view used to illustrate the readout action.

[0026] Figure 20 It is a schematic circuit diagram used to illustrate the readout action.

[0027] Figure 21 It is a schematic circuit diagram used to illustrate the readout action.

[0028] Figure 22 It is a schematic circuit diagram used to illustrate the readout action.

[0029] Figure 23 This is a schematic circuit diagram used to explain the write operation of the semiconductor memory device of the first embodiment.

[0030] Figure 24 This is a schematic circuit diagram used to explain the write operation of the semiconductor memory device of the first embodiment.

[0031] Figure 25 This is a schematic circuit diagram used to explain the erase operation of the semiconductor memory device of the first embodiment.

[0032] Figure 26 This is a schematic circuit diagram used to explain the erase operation of the semiconductor memory device of the first embodiment.

[0033] Figure 27 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device of the second embodiment.

[0034] Figure 28 DEC represents the decoding circuit of the semiconductor memory device in the third embodiment. SG A schematic circuit diagram of the structure of '.

[0035] Figure 29 This refers to the transistor layer L in the fourth embodiment. T4 A schematic cross-sectional view consisting of a portion of it.

[0036] Figure 30 This refers to the transistor layer L in the fourth embodiment. T4 A schematic cross-sectional view consisting of a portion of it.

[0037] Figure 31 This refers to the transistor layer L in the fifth embodiment. T5 A schematic cross-sectional view consisting of a portion of it.

[0038] Figure 32 This refers to the transistor layer L in the fifth embodiment. T5 A schematic cross-sectional view consisting of a portion of it.

[0039] Figure 33 This is a schematic circuit diagram used to illustrate the semiconductor memory device of the sixth embodiment.

[0040] Figure 34 This refers to the transistor layer L in the sixth embodiment. T6 A schematic cross-sectional view consisting of a portion of it.

[0041] Figure 35 This refers to the transistor layer L in the seventh embodiment. T7 A schematic cross-sectional view consisting of a portion of it.

[0042] Figure 36 This refers to the transistor layer L in the eighth embodiment. T8 A schematic cross-sectional view consisting of a portion of it.

[0043] Figure 37 This refers to the transistor layer L in the ninth embodiment. T9 A schematic cross-sectional view consisting of a portion of it. Detailed Implementation

[0044] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Also, common parts in multiple embodiments may be labeled with the same symbols, and descriptions may be omitted.

[0045] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or it may refer to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it may refer to a device including a host, such as a smartphone, tablet, or personal computer.

[0046] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected to" the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an off state, the first transistor is "electrically connected to" the third transistor.

[0047] Furthermore, in this specification, when referring to the first component as "connected" "between" the second and third components, it means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0048] Furthermore, in this specification, when it is mentioned that a circuit or the like "conducts" two wirings, for example, it means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and the transistor or the like is in a switched-on state.

[0049] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0050] In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specific surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0051] Furthermore, in this specification, the terms "upper" or "lower," etc., are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when referring to a lower surface or lower end of a configuration, it refers to the surface or end of that configuration on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of that configuration on the side opposite to the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0052] [First Implementation]

[0053] [constitute]

[0054] Figure 1 This is a schematic block diagram showing the configuration of a portion of the semiconductor memory device according to the first embodiment.

[0055] The semiconductor memory device of this embodiment includes a memory cell array (MCA). The memory cell array (MCA) includes multiple memory blocks (BLK). Each memory block (BLK) includes multiple pages (PG).

[0056] Furthermore, in the semiconductor memory device of this embodiment, the memory cell array (MCA) is divided into multiple (four in the illustrated example) sub-arrays (MCA). S In addition, multiple storage block BLKs are connected to multiple subarrays MCA. SCorrespondingly, it is divided into multiple (four in the example shown) sub-blocks BLK S In addition, multiple page PGs are connected to multiple subarrays MCA. S Correspondingly, it is divided into multiple (four in the example shown) subpages PG. S .

[0057] The semiconductor memory device of this embodiment can store page PG or subpage PG. S This is set as the execution unit for read and write operations. Furthermore, the semiconductor memory device of this embodiment can classify memory blocks (BLK) or sub-blocks (BLK) as memory blocks. S Set as the unit of execution for the erase action.

[0058] Figure 2 This is a schematic perspective view showing the configuration of a portion of the semiconductor memory device according to the first embodiment. The semiconductor memory device of this embodiment includes a semiconductor substrate Sub and a memory cell array layer L disposed above the semiconductor substrate Sub. MCA and set in the storage cell array layer L MCA The transistor layer above L T .

[0059] The semiconductor substrate Sub is, for example, a silicon (Si) semiconductor substrate containing P-type impurities such as boron (B). A portion of the peripheral circuitry controlling the memory cell array (MCA) may also be disposed on the upper surface of the semiconductor substrate Sub.

[0060] In the storage cell array layer L MCA It contains the memory cell array (MCA). Memory cell array layer L MCA It has 4 sub-arrays MCA arranged in the X direction S Additionally, the first and second subarrays MCA counting from one side of the X direction (e.g., the negative side of the X direction) S Between them, the subarray inter-region R is set. MCAS Additionally, the 3rd and 4th subarrays MCA counting from one side of the X direction (e.g., the negative side of the X direction) S Between them, there is also a subarray region R. MCAS .

[0061] transistor layer L T Equipped with settings in 4 sub-arrays MCA S The four decoding circuits DEC at the corresponding positions SG Additionally, transistor layer L T Equipped with a region R between the two subarrays MCAS The two drive circuits DRV at the corresponding positions SWL .

[0062] Additionally, transistor layer L T Equipped with drive circuits DRV arranged in the X direction relative to these components GWL DRV drive circuit SG and decoding circuit DEC R .

[0063] [Storage cell array layer L] MCA [Composition]

[0064] [Subarray MCA] S [Composition]

[0065] Figure 3 This indicates the subarray MCA S A schematic top view of a portion of the structure. Subarray MCA S It has multiple sub-blocks BLK arranged in the Y direction. S Multiple sub-blocks BLK S Each has multiple arrays arranged in the X direction, forming an AS.

[0066] Figure 4 It is a schematic three-dimensional diagram representing a part of the array structure AS. Figure 5 It is a schematic circuit diagram representing a part of the array structure AS. Figure 6 It is a schematic top view showing the composition of a part of the array structure AS. Figure 7 and Figure 8 It is a schematic cross-sectional view showing the composition of a part of the array structure AS.

[0067] like Figure 4 As shown, the storage cell array layer L MCA It has multiple memory layers ML arranged alternately in the Z direction and multiple insulating layers 101. The insulating layers 101 include silicon oxide (SiO2) and the like.

[0068] like Figure 5 As shown, the array structure AS has multiple string units SU. Each string unit SU has multiple memory units MU, corresponding to multiple memory layers ML. Each memory unit MU has two memory strings MS. One end of each of these two memory strings MS is connected to the peripheral circuit via a bit line BL. The other end of each of these two memory strings MS is connected to the peripheral circuit via a common source line SL.

[0069] The memory string (MS) comprises a drain-side select transistor (STD), multiple memory cells (MCs) (memory transistors), and a source-side select transistor (STS). The STD, MCs, and STS are connected in series between the bit line BL and the source line SL. Hereinafter, the STD and STS are sometimes simply referred to as select transistors (STD, STS).

[0070] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage layer. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage layer. The memory cell MC stores one bit or more bits of data. Furthermore, the gate electrodes of the multiple memory cells MC contained in a memory unit MU are connected to sub-word lines SWL. These sub-word lines SWL are all connected to all memory units MU in an array structure AS.

[0071] The selection transistors (STD, STS) are field-effect transistors. Each selection transistor (STD, STS) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Selection gate lines (SGD, SGS) are connected to the gate electrodes of the selection transistors (STD, STS). The two drain-side selection gate lines corresponding to the two memory strings (MS) are all connected to all memory units (MU) within a single string unit (SU). The two source-side selection gate lines (SGS) corresponding to the two memory strings (MS) are all connected to all memory units (MU) within a single string unit (SU).

[0072] Furthermore, during read and write operations, when constructing a storage block BLK or a sub-block BLK... S In multiple array configurations AS, the drain-side gate selection line SGD corresponding to the address data is selected. Therefore, in each array configuration AS, a string unit SU is selected. Furthermore, during read and write operations, the memory block BLK or sub-block BLK is configured... S In the multiple array configurations AS, the subword line SWL corresponding to the address data is selected. Therefore, in each string unit SU, a memory cell MC is selected. These multiple memory cells MC are related to a reference... Figure 1 The page PG or subpage PG described S correspond.

[0073] like Figure 6 As shown, in the array structure AS, multiple memory cell regions R are arranged alternately in the Y direction. MC and multiple stepped areas R LDAdditionally, a selection transistor region R is located at one end of the array structure AS in the Y direction. SGD and bit line region R BL Additionally, at the other end of the array structure AS in the Y direction, a selection transistor region R is provided. SGS and source pole region R SL .

[0074] The memory layer ML has multiple semiconductor layers 110 arranged in the X direction. These multiple semiconductor layers 110 respectively span a reference. Figure 6 The described multiple memory cell regions R MC Multiple stepped areas R LD and selection of transistor region R SGD R SGS Extending in the Y direction. The semiconductor layer 110 serves, for example, as a plurality of memory cells MC connected in series. Figure 5 ), and the selection transistors (STD, STS) connected to these memory cells MC ( Figure 5 The channel region of the semiconductor layer 110 functions as such. The semiconductor layer 110 may contain either polycrystalline silicon (Si) or monocrystalline silicon (Si). Furthermore, in these cases, the semiconductor layer 110 may contain N-type impurities such as phosphorus (P), P-type impurities such as boron (B), or may not contain any impurities.

[0075] Furthermore, in the following description, there exists a region between two adjacent semiconductor layers 110 in the X direction, referred to as the "inter-channel region R". IC In addition, there exists a situation where the odd-numbered inter-channel region R is counted from one side of the X direction (e.g., the negative side of the X direction). IC It is called "inter-channel region R" ICO In addition, there exists a region R between the even-numbered channels counting from one side in the X direction. IC It is called "inter-channel region R" ICE The situation of "".

[0076] like Figure 6 As shown, in the storage cell region R MC and select transistor region R SGD R SGS ( Figure 6 The inter-channel region R in ) IC Multiple through-hole electrodes 120 arranged in the Y direction are provided. Additionally, in the memory cell region R... MC In the memory layer ML, there are multiple gate insulating layers 130 disposed between the X-direction side of the multiple via electrodes 120 and the semiconductor layer 110.

[0077] The through-hole electrode 120 is disposed in the memory cell region RMC The via electrodes serve as, for example, the gate electrodes of multiple memory cells (MCs) and the sub-word lines (SWLs) connected to these gate electrodes. Figure 5 Part of the function is performed by the through-hole electrode 120, which is located in the selection transistor region R. SGD R SGS The via electrodes serve as the gate electrodes of the select transistors STD and STS, respectively, and the select gate lines SGD and SGS connected to the gate electrodes. Figure 5 To fulfill its function.

[0078] For example, such as Figure 6 As shown, the through-hole electrode 120 may also include a barrier conductive layer 121 such as titanium nitride (TiN) and a conductive layer 122 such as tungsten (W). For example, as Figure 7 As shown, the via electrode 120 extends in the Z direction, penetrating multiple memory layers ML. Furthermore, as... Figure 6 As shown, an insulating layer 123, such as silicon oxide (SiO2), is disposed between two adjacent through-hole electrodes 120 in the Y direction. Figure 6 ).

[0079] Furthermore, in this embodiment, in the selected transistor region R SGD Inter-channel region R IC Two through-hole electrodes 120 arranged in the Y direction are respectively provided.

[0080] Here, the selection transistor region R is set. SGD Inter-channel region R ICO The two through-hole electrodes 120 are located far from the memory cell region R. MC The via electrodes 120 are used to turn the select transistor off. In the illustrated example, these via electrodes 120 are commonly connected to node N0. On the other hand, near the memory cell region R... MC The via electrodes 120 are used to turn the selector transistor on or off. In the illustrated example, these via electrodes 120 are connected to nodes N1 and N3. Nodes N0, N1, and N3 are electrically independent of each other and can transmit independent voltages.

[0081] Additionally, the selection transistor region R is set. SGD Inter-channel region R ICE The two through-hole electrodes 120 are located far from the memory cell region R. MC The via electrodes 120 are used to turn the select transistor on or off. In the illustrated example, these via electrodes 120 are connected to nodes N2 and N4. On the other hand, near the memory cell region R... MCThe via electrodes 120 are used to turn the select transistor off. In the illustrated example, these via electrodes 120 are all connected to node N0. Nodes N0, N2, and N4 are electrically independent of each other and can transmit independent voltages.

[0082] In addition, the inter-channel region R ICO With R ICE The via electrodes 120 can be arranged alternately, and their connection to nodes N0 to N4 can also be R. ICO With R ICE Conversely, for example, it is also possible to set the transistor region R. SGD Inter-channel region R ICO The two through-hole electrodes 120 are located far from the memory cell region R. MC The through-hole electrode 120 is connected to nodes N1 and N3, close to the memory cell region R. MC The through-hole electrode 120 is connected to node N0. In this case, it can also be set in the selection transistor region R. SGD Inter-channel region R ICE The two through-hole electrodes 120 are located far from the memory cell region R. MC The via electrode 120 is connected to node N0, close to the memory cell region R. MC The through-hole electrode 120 is connected to nodes N2 and N4.

[0083] The gate insulating layer 130 includes, for example, a tunnel insulating layer 131 disposed on the X-direction side of the semiconductor layer 110, a charge storage layer 132 disposed on the X-direction side of the semiconductor layer 110, and a barrier insulating layer 133 disposed on the X-direction side of the semiconductor layer 110.

[0084] The tunnel insulation layer 131 may also contain silicon oxide (SiO2), for example.

[0085] The charge storage layer 132 may, for example, contain polycrystalline silicon (Si). In this case, the charge storage layer 132 may contain N-type impurities such as phosphorus (P), P-type impurities such as boron (B), or may not contain any impurities.

[0086] The barrier insulating layer 133 may also include, for example, silicon oxide (SiO2). Alternatively, the barrier insulating layer 133 may also include aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0087] In the stepped region R LD ( Figure 6 The inter-channel region R in ) IC It is equipped with a through-hole electrode 140.

[0088] The via electrode 140 functions, for example, as the gate electrode of a transistor and as a wiring connected to the gate electrode of the transistor. For example, as... Figure 6 As shown, the through-hole electrode 140 may also contain a semiconductor layer 141 such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P) and a conductive layer 142 such as titanium nitride (TiN). For example, as Figure 8 As shown, the via electrode 140 extends in the Z direction, penetrating multiple memory layers ML. Furthermore, an insulating layer 143, such as silicon oxide (SiO2), is provided on the outer peripheral surface of the via electrode 140. Additionally, an insulating layer 144, such as silicon oxide (SiO2), may also be provided in the central portion of the via electrode 140.

[0089] In bit line region R BL ( Figure 6 In the memory layer ML, there are multiple semiconductor layers 160 arranged in the X direction and conductive layers 170 connected to these multiple semiconductor layers 160.

[0090] Semiconductor layer 160 may, for example, contain a semiconductor layer such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P). Semiconductor layers 160 are connected to the ends of semiconductor layer 110 in the Y direction. Furthermore, an insulating layer 161 is provided between two adjacent semiconductor layers 160 in the X direction. Insulating layer 161 may, for example, contain silicon oxide (SiO2). Insulating layer 161 extends in the Z direction, penetrating multiple memory layers ML.

[0091] Conductive layer 170, for example, serves as bit line BL ( Figure 5 The conductive layer 170 may, for example, comprise a conductive layer such as titanium nitride (TiN). The conductive layer 170 extends in the X direction and is electrically connected to the plurality of semiconductor layers 110 via the plurality of semiconductor layers 160.

[0092] In the source pole region R SL ( Figure 6 In the memory layer ML, there are multiple semiconductor layers 160 arranged in the X direction and conductive layers 171 connected to these multiple semiconductor layers.

[0093] Conductive layer 171, for example, serves as source line SL ( Figure 5 The conductive layer 171 may, for example, comprise a conductive layer such as titanium nitride (TiN). The conductive layer 171 extends in the X direction and is connected to the plurality of semiconductor layers 110 via the plurality of semiconductor layers 160.

[0094] [Transistor layer L] T [Composition]

[0095] Figure 9 and Figure 10 It represents transistor layer LT A schematic cross-sectional view of a portion of the composition. Furthermore, Figure 9 and Figure 10 In addition to illustrating the transistor layer L, T In addition, examples are shown of those disposed in transistor layer L. T The wiring layer M0 below, and the transistor layer L T The upper wiring layer M1.

[0096] transistor layer L T Includes such as Figure 9 The illustrated transistor Tr LV and such Figure 10 The illustrated transistor Tr HV Transistor Tr LV This is a low-voltage transistor. Transistor Tr HV It is a high-voltage transistor.

[0097] like Figure 9 As shown, transistor Tr LV Equipped with semiconductor layer 181 L Set in semiconductor layer 181 L The gate insulating layer 182 on the upper surface, the gate electrode 183 disposed on the upper surface of the gate insulating layer 182, and the sidewall insulating layers 184 disposed on both sides of the gate insulating layer 182 and the gate electrode 183 in the X or Y direction.

[0098] Semiconductor layer 181 L It may also contain polycrystalline silicon (Si). The gate insulating layer 182 may, for example, contain at least one of silicon oxide (SiO2) and silicon nitride (SiN), or it may contain aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films. The gate electrode 183 is separated from the semiconductor layer 181 by the gate insulating layer 182. L The upper surface faces each other. The gate electrode 183 may, for example, comprise a polycrystalline silicon (Si), a metal such as tungsten (W) containing N-type or P-type impurities, a silicide, or a multilayer film composed of two or more of these. The gate electrode 183 is connected to the wiring m1 in the wiring layer M1 via a through-hole contact electrode v1. The sidewall insulating layer 184 may, for example, comprise at least one of silicon oxide (SiO2) and silicon nitride (SiN).

[0099] Semiconductor layer 181 L The region overlapping with the gate electrode 183 when viewed from the Z direction is called the gate region 181g. Additionally, the semiconductor layer 181... L The region overlapping with the sidewall insulating layer 184 when viewed from the Z direction is designated as region 181s' or region 181d'. Additionally, the semiconductor layer 181... LThe region that does not overlap with either the gate electrode 183 or the sidewall insulating layer 184 when viewed from the Z direction is called the source region 181s or the drain region 181d. The source region 181s and the drain region 181d are connected to wiring m0 in wiring layer M0 or wiring m1 in wiring layer M1 via via contact electrode v0 or via contact electrode v1. Region 181s' is located between the source region 181s and the gate region 181g. Region 181d' is located between the drain region 181d and the gate region 181g.

[0100] In transistor Tr LV In the case of an N-channel field-effect transistor, the source region 181s, drain region 181d, region 181s', and region 181d' contain N-type impurities such as phosphorus (P) or arsenic (As) and function as N-type semiconductors. The impurity concentration in regions 181s' and 181d' is lower than that in the source region 181s and drain region 181d. Furthermore, the gate region 181g contains P-type impurities such as boron (B) and functions as a P-type semiconductor.

[0101] In transistor Tr LV In the case of a P-channel type field-effect transistor, the source region 181s, drain region 181d, region 181s', and region 181d' contain P-type impurities such as boron (B) and function as P-type semiconductors. The impurity concentration in regions 181s' and 181d' is lower than that in the source region 181s and drain region 181d. Furthermore, the gate region 181g contains N-type impurities such as phosphorus (P) or arsenic (As) and functions as an N-type semiconductor.

[0102] like Figure 10 As shown, transistor Tr HV Basically related to transistor Tr LV They are constructed in the same way. However, the transistor Tr HV Equipped with semiconductor layer 181 H To replace semiconductor layer 181 L Semiconductor layer 181 H Basically with semiconductor layer 181 L They are constructed in the same way. However, in semiconductor layer 181 H The region that does not overlap with the gate electrode 183 or the sidewall insulating layer 184 when viewed from the Z direction is not only provided with the source region 181s or the drain region 181d, but also a part of the region 181s' or the region 181d'.

[0103] In the following description, there is a semiconductor layer 181 L and semiconductor layer 181 HThis is summarized as semiconductor layer 181.

[0104] also, Figure 9 and Figure 10 The image illustrates a transistor Tr with the channel direction (the direction of the long side of semiconductor layer 181) in the Y direction. LV Tr HV However, transistor layer L T It can also include a transistor Tr that oriented the channel in the X direction. LV Tr HV .

[0105] [Driver Circuit DRV] SWL DRV GWL [Composition]

[0106] Figure 11 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to this embodiment. Figure 12 and Figure 13 This is a schematic circuit diagram showing the configuration of a portion of the semiconductor memory device according to this embodiment.

[0107] Figures 11-13 The example shows multiple sets of subword lines (SWL), multiple sets of global word lines (GWL), and one set of bus lines (BWL).

[0108] like Figure 13 As shown, multiple sets of sub-word lines (SWL) are respectively connected to multiple sub-blocks (BLK) arranged in the Y direction. S Corresponding. In a sub-block BLK S The multiple array structures AS contained therein are commonly connected to multiple sub-word lines SWL. Furthermore, as... Figure 11 As shown, the sub-word lines SWL are for each sub-array MCA. S And electrical properties are independent.

[0109] like Figure 13 As shown, the drive circuit DRV SWL Each has multiple sub-blocks BLK arranged in the Y direction. S Multiple DRVS circuits are configured accordingly. Each DRVS circuit is connected to a sub-block BLK. S The multiple sub-word lines SWL correspond to the multiple transistors Tr set. HV These multiple transistors Tr HV The source electrode is connected to the global word line GWL. These multiple transistors Tr HV The drain electrode is connected to the sub-word line SWL. These multiple transistors Tr HV The gate electrode is connected to the DRVSL wiring. The DRVSL wiring is commonly connected to all transistors Tr contained in the DRVS circuit. HVThe gate electrode. The wiring of DRVSL is electrically independent for each circuit DRVS.

[0110] like Figure 12 As shown, the memory cell array MCA is divided into multiple regions (two in the illustrated example) along the Y direction. Each of these regions contains multiple memory blocks (BLKs) (see reference). Figure 13 ).exist Figure 12 In this example, corresponding to these multiple regions, multiple sets (two sets in the illustrated example) of global word lines (GWLs) are set up. These multiple sets of global word lines (GWLs) are electrically connected to all sub-blocks (BLKs) contained in the corresponding regions. S .

[0111] DRV drive circuit GWL It has multiple circuits drvg that are configured to correspond to multiple sets of global word lines (GWL). Each circuit drvg has multiple transistors Tr that are configured to correspond to the multiple global word lines (GWL) contained in a set of global word lines (GWL). HV These multiple transistors Tr HV The source electrode is connected to the bus wiring BWL. These multiple transistors Tr HV The drain electrode is connected to the global word line GWL. These multiple transistors Tr HV The gate electrode is connected to wiring drvgl. Wiring drvgl is commonly connected to all transistors Tr contained in circuit drvg. HV The gate electrode. The wiring drvgl is electrically independent for each circuit drvg.

[0112] Figure 14 This indicates the drive circuit DRV. SWL A schematic top view of the structure. Figure 15 This indicates the drive circuit DRV. SWL A schematic side view of the structure. Figure 16 This indicates the drive circuit DRV. SWL A schematic cross-sectional view of its composition. Furthermore, Figure 14 and Figure 15 This is a schematic diagram illustrating multiple components that do not appear on the same cross-section. Additionally, Figures 14-16 The example shown is set in transistor layer L T The wiring layer M0 below, and the transistor layer L T The wiring layers M1 and M2 above.

[0113] like Figure 14 As shown, the circuit DRVS has multiple transistors Tr arranged in the X direction. HV In the illustrated example, multiple transistors Tr HVThe channel direction (the long side direction of semiconductor layer 181) is the Y direction. These multiple transistors Tr HV The gate electrodes 183 are arranged in the X direction.

[0114] in addition, Figure 14 The diagram illustrates a wiring m1 extending in the X direction. This wiring m1 serves as wiring drvsl ( Figure 13 The wiring drvsl is commonly connected to multiple gate electrodes 183 via multiple through-hole contact electrodes v1 arranged in the X direction.

[0115] in addition, Figure 14 The diagram illustrates multiple wirings m2 extending in the X direction and arranged in the Y direction. These wirings m2 are wirings within wiring layer M2, each functioning as a global word line (GWL). These wirings m2 are positioned on one side of the Y direction relative to the wiring m1 (in...). Figure 14 In the example, (the positive side in the Y direction), and each has a portion that overlaps with a portion of the semiconductor layer 181 when viewed from the Z direction. For example, as Figure 16 As illustrated, these multiple wirings m2 are connected to the semiconductor layer 181 via via contact electrode v2, wiring m1, and via contact electrode v1, respectively.

[0116] In addition, Figure 14 The diagram illustrates multiple wirings m0 extending in the X direction and arranged in the Y direction. Each of the multiple wirings m0 functions as a sub-line SWL. These multiple wirings m0 are positioned on the opposite side of the wiring m1 in the Y direction (in...). Figure 14 In the example, (the negative side in the Y direction), and each has a portion that overlaps with a portion of the semiconductor layer 181 when viewed from the Z direction. For example, as Figure 15 As illustrated, these multiple wirings m0 are connected to the semiconductor layer 181 via via-hole contact electrodes v0. Furthermore, these multiple wirings m0 are connected to multiple via-hole electrodes 120 arranged in the X direction via multiple via-hole contact electrodes vh arranged in the X direction.

[0117] [Decoding circuit DEC] SG [Composition]

[0118] Figure 17 It represents the decoding circuit DEC. SG A schematic circuit diagram of the structure.

[0119] Decoding circuit DEC SG It has multiple address nodes n corresponding to multiple drain-side select gate lines (SGD) and multiple source-side select gate lines (SGS). A The figure illustrates multiple drain-side selected gate lines (SGD). n－1 ~SGDn+1 and multiple source-side gate select lines (SGS) n－1 ~SGS n+1 and the multiple address nodes n corresponding to these selected gate lines. An－1 ~n An+1 .

[0120] In addition, the decoding circuit DEC SG Possessing address node n A Charging circuit C for charging PRC Address node n A Discharge circuit C DSC The address node n selected based on the input address signal. A With discharge circuit C DSC The address selection circuit C is turned on. ADS The address node n to be discharged according to the input signal. A The adjacent address node n A The discharge circuit C for charge discharge 2 / 3D C 2 / 3S and based on address node n A The state of the level shifter circuit C supplies voltage to either the drain-side gate line (SGD) or the source-side gate line (SGS). LSD C LSS .

[0121] Charging circuit C PRC Capable of connecting with multiple address nodes n A The corresponding set multiple transistors Tr SG11 Tr SG12 Transistor Tr SG11 Tr SG12 For example, Tr of P-channel type LV ( Figure 9 Multiple address nodes n A Transistors Tr connected in series SG11 Tr SG12 And connected to voltage node n VDD For voltage node n VDD Supply voltage V DD Multiple transistors Tr SG11 The gate electrodes of multiple transistors are commonly connected to signal line RE. SG12 The gate electrode is commonly connected to the signal line / PRC.

[0122] Discharge circuit C DSC Capable of connecting with multiple address nodes n A The corresponding set multiple transistors Tr SG22 Transistor Tr SG22 For example, Tr of N-channel typeLV ( Figure 9 Multiple address nodes n A via transistor Tr SG22 And connected to voltage node n VSS For voltage node n VSS Supply ground voltage V SS Multiple transistors Tr SG22 The gate electrode is commonly connected to the signal line RE.

[0123] Address selection circuit C ADS Capable of connecting with multiple address nodes n A The corresponding set multiple transistors Tr SG21 Transistor Tr SG21 For example, Tr is an N-channel or P-channel type. LV ( Figure 9 Multiple address nodes n A Each via multiple (in series) Figure 17 In the example, there are 6 transistors Tr SG21 And connected to voltage node n VSS Additionally, it connects to address node n. A and voltage node n VSS Between multiple (in) Figure 17 In the example, there are 6 transistors Tr SG21 The gate electrodes are respectively connected to multiple signal lines A0 to A5 of the output address signal. Multiple signal lines A0 to A5 respectively output multiple signals constituting the address signal (in... Figure 17 In this example, it's 6 bits. Address selection circuit C ADS Based on the multiple bits input to signal lines A0 to A5 (in Figure 17 In the example, the data is 6 bits, with multiple address nodes n. A Only one of the voltage nodes n VSS The conduction method is constituted.

[0124] Discharge circuit C 2 / 3D Equipped with multiple transistors Tr SG31 Tr SG32 Transistor Tr SG31 Tr SG32 For example, Tr of N-channel type LV ( Figure 9 The 2ath (where a is an integer greater than or equal to 0) address node n A For example, via transistor Tr SG31 And connected to the 2a+1th address node n A The 2a+1th address node n A For example, via transistor Tr SG32And connected to the 2a+2nd address node n A In addition, multiple transistors Tr SG31 The gate electrodes of the transistors are commonly connected to signal line A(-1). Additionally, multiple transistors Tr... SG32 The gate electrode is commonly connected to the signal line / A(-1).

[0125] Discharge circuit C 2 / 3S With discharge circuit C 2 / 3D They are identically constructed.

[0126] Level shifter circuit C LSD It has multiple converters configured to correspond to multiple drain-side selected gate lines (SGDs). Each of these multiple converters has a transistor Tr. SG41 Tr SG42 Transistor Tr SG41 For example, a P-channel transistor Tr HV ( Figure 10 ). Transistor Tr SG41 The source electrode is connected to voltage node n VSGD Voltage node n VSGD The voltage is supplied to the drain-side select gate line SGD. Transistor Tr SG41 The drain electrode is connected to the drain-side select gate line SGD. Transistor Tr SG41 The gate electrode is connected to address node n A Transistor Tr SG42 The source electrode is connected to voltage node n VSS Transistor Tr SG42 The drain electrode is connected to the drain-side select gate line SGD. Transistor Tr SG42 The gate electrode is connected to address node n A .

[0127] Level shifter circuit C LSS It has multiple time-controlled converters configured to correspond to multiple source-side selected gate lines (SGS). Each of these multiple time-controlled converters has a transistor Tr. SG51 Tr SG52 Tr SG53 Tr SG54 Transistor Tr SG51 Tr SG52 For example, a P-channel transistor Tr HV ( Figure 10 ). Transistor Tr SG51 Tr SG52 Connected in series at voltage node n VSGS Between the source-side selected gate line SGS and the voltage node n. VSGSThe voltage is supplied to the source-side select gate line SGS. Transistor Tr SG51 The gate electrode is connected to address node n A Transistor Tr SG52 The gate electrode of the transistor is connected to the signal line / RE. SG53 Tr SG54 For example, an N-channel transistor Tr HV ( Figure 10 ). Transistor Tr SG53 Tr SG54 Parallel connection at voltage node n VSS Between the source-side select gate line SGS and the transistor Tr. SG53 The gate electrode is connected to address node n A Transistor Tr SG54 The gate electrode is connected to the signal line / RE.

[0128] [Read the action]

[0129] Figure 18 and Figure 19 This is a schematic top view used to explain the read operation of the semiconductor memory device according to the first embodiment. Furthermore, in Figure 18 and Figure 19 In the diagram, the three semiconductor layers 110 arranged in the X direction are shown as semiconductor layers 110a, 110b, and 110c, respectively. Additionally, in... Figure 18 and Figure 19 In the diagram, one of the multiple memory cells MC disposed on one side of the semiconductor layer 110b in the X direction is designated as the selected memory cell MC. S Examples.

[0130] During the readout process, in the selected transistor region R SGD In the diagram, a voltage V is supplied to two nodes (N2 and N3 in the illustrated example) that correspond to semiconductor layer 110b among nodes N1 to N4. SG A cutoff voltage V is supplied to all other nodes (nodes N0, N1, and N4 in the illustrated example). BB Cutoff voltage V BB The degree to which the selective transistor is turned off is determined. Consequently, an electron channel is formed near the via electrode 120 of the semiconductor layer 110b connected to node N2. Additionally, an electron channel is formed near the via electrode 120 of the semiconductor layer 110b connected to node N3. Thus, the voltage of the conductive layer 170 is transmitted to the stepped region R. LDAccording to this method, the voltage of the conductive layer 170 can be properly transmitted in the semiconductor layer 110b, and the transmission of the voltage of the conductive layer 170 can be properly blocked in the semiconductor layers 110a and 110c.

[0131] Additionally, during the readout operation, in the selected transistor region R... SGS In this process, a voltage V is supplied to two via electrodes 120 disposed on one side and the other side of the semiconductor layer 110b in the X direction. SG Subsequently, electron channels are formed near the two via electrodes 120 in semiconductor layers 110a, 110b, and 110c, transmitting the voltage of conductive layer 171 to the stepped region R. LD .

[0132] Additionally, during the read operation, the settings are configured to not include the selected memory unit MC. S storage cell area R MC Multiple through-hole electrodes 120 and 140 supply readout through voltage V READ Read the voltage V. READ The degree to which the memory cell MC remains switched on regardless of the data recorded in it is sufficient. Thus, in the semiconductor layer 110b, the voltage of the conductive layers 170 and 171 is transmitted to the region containing the selected memory cell MC. S storage cell area R MC Furthermore, in semiconductor layers 110a and 110c, there is also a mechanism for transmitting the voltage of conductive layer 171 to the region containing the selection memory cell MC. S storage cell area R MC The situation.

[0133] Additionally, during the read operation, the settings included in the selection memory unit MC are... S storage cell area R MC Among the multiple via electrodes 120, one side is disposed in the X direction relative to the semiconductor layer 110b (with the selected memory cell MC). S The through-hole electrode (on the same side) supplies the readout through voltage V. READ Therefore, the selection of the memory unit MC S The voltage of the conductive layer 170 is transferred to the drain region. Additionally, the selected memory cell MC... S The source region transmits the voltage of the conductive layer 171.

[0134] Additionally, during the read operation, the selected memory unit MC is... S The through-hole electrode 120, which functions as the gate electrode, supplies the readout voltage V. CGR Read the voltage V CGRThe degree to which the storage unit MC becomes on or off based on the data recorded in it. For example, when selecting the storage unit MC... S The threshold voltage is less than the readout voltage V. CGR In such cases, Figure 18 As shown, in selecting the storage unit MC S In the channel region, an electron channel Nch is formed. Subsequently, conductive layers 170 and 171 become conductive, allowing current to flow through conductive layer 170. On the other hand, in the selection of the memory cell MC... S The threshold voltage is greater than the readout voltage V. CGR In such cases, Figure 19 As shown, do not select storage unit MC S The channel region forms an electron channel Nch. Therefore, conductive layers 170 and 171 are not conductive, and no current flows through conductive layer 170. Therefore, by measuring the current in conductive layer 170, it is possible to determine the current recorded in the selected memory cell MC. S The data in the middle.

[0135] Additionally, during the read operation, the settings are configured in relation to the selected memory unit MC. S Common storage unit area R MC Multiple through-hole electrodes 120 are disposed on the opposite side in the X direction relative to the semiconductor layer 110b (with the selected memory cell MC). S The through-hole electrode on the opposite side supplies the back cell cutoff voltage V. BC Backside cell cutoff voltage V BC It has the capability to ensure that the storage cell MC remains in an off state regardless of the data recorded in it. This allows for the suppression of leakage current through the storage cell MC located on the other side in the X direction.

[0136] Figure 20 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device of the first embodiment.

[0137] During a read operation, for example, the storage block BLK or sub-block BLK of the object being read can also be used. S One corresponding wiring drvgl is set to the "H" state, and the other wirings drvgl are set to the "L" state. Therefore, the storage block BLK or sub-block BLK that becomes the object of the read operation can also be... S The corresponding transistor Tr in a single circuit drvg HV Set it to the ON state, and turn on the transistor Tr contained in the other circuits drvg. HV Set to disconnected state.

[0138] Alternatively, the wiring drvsl corresponding to the memory block BLK that is the object of the read operation can be set to the "H" state, and the other wiring drvsl can be set to the "L" state. Therefore, the transistors Tr contained in the multiple (four in the illustrated example) circuits drvs corresponding to the memory block BLK that is the object of the read operation can also be configured. HV Set it to the ON state, and turn on the transistors Tr contained in the other circuits drvs. HV Set to disconnected state.

[0139] Alternatively, multiple sub-blocks BLK that constitute the storage block BLK can also be combined. S Only a portion of the corresponding wiring DRVSL is set to the "H" state, while the remaining wiring DRVSL is set to the "L" state. Therefore, it is also possible to set only a portion (in the illustrated example, 1 to 3) of the sub-block BLK. S The corresponding transistor Tr in the DRVS circuit HV Set it to the ON state, and turn on the transistors Tr contained in the other circuits drvs. HV Set to the off state. This method reduces the wiring capacity of the Global Word Line (GWL) and enables high-speed read operations.

[0140] Figure 21 and Figure 22 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device of the first embodiment.

[0141] For reference Figure 18 and Figure 19 As explained, during the read operation of the semiconductor memory device in the first embodiment, a voltage V is supplied to two nodes (nodes N2 and N3 in the illustrated example) that correspond to the semiconductor layer 110b among nodes N1 to N4. SG A cutoff voltage V is supplied to all other nodes (nodes N0, N1, and N4 in the illustrated example). BB . Figure 17 DEC decoding circuit SG It is configured in a way that enables such a selection action to be performed. This aspect will be explained below.

[0142] When reading out an action, for example, such as Figure 21 As shown, set signal line RE to "L", signal line / RE to "H", and signal line / PRC to "L". Input specific address data into signal lines A0 to A5 (in... Figure 22 In the example, it is "H, L, H, H, H, L").

[0143] In this state, the charging circuit C PRC transistor Tr inSG11 , Tr SG12 is turned on. As a result, all address nodes n A are charged and brought into the "H" state. In addition, from the level shifter circuit C LSD , the ground voltage V is supplied to all drain-side select gate lines SGD SS , and all the drain-side select gate lines SGD are brought into the "L" state. In addition, from the level shifter circuit C LSS , the ground voltage V is supplied to all source-side select gate lines SGS SS , and all the source-side select gate lines SGS are brought into the "L" state.

[0144] Next, for example, as shown in Figure 22 , the signal line RE is set to the "H" state, the signal line / RE is set to the "L" state, and the signal line / PRC is set to the "H" state. In this stage, the cutoff voltage V may also be supplied to the voltage node n VSS BB .

[0145] Accordingly, all address nodes n A are electrically disconnected from the voltage node n VDD . In addition, among the plurality of address nodes n A , a plurality of (6 in the illustrated example) transistors Tr corresponding to one address node corresponding to the address data (the address node n in the illustrated example) An SG21 are all turned on. Accordingly, this address node n An is brought into conduction with the voltage node n VSS , and this address node n An is brought into the "L" state. Accordingly, the drain-side select gate line SGD n is brought into conduction with the voltage node n VSGD , and the drain-side select gate line SGD n is brought into the "H" state. In addition, the source-side select gate line SGS n is brought into conduction with the voltage node n VSGS , and the source-side select gate line SGS n is brought into the "H" state.

[0146] Further, for example, when the signal line A(-1) is in the "H" state and the signal line / A(-1) is in the "L" state, the transistor Tr SG31 is turned on. Accordingly, the address node n An+1 is brought into conduction with the voltage node n via the address node n A VSS , and the address node n An+1 is also brought into the "L" state. Accordingly, the drain-side select gate line SGD​​​n+1 With voltage node n VSGD On, the drain-side gate selection line SGD n+1 It becomes the "H" state. Additionally, the source-side gate selection line SGS... n+1 With voltage node n VSGS Turn on, source-side select gate line SGS n+1 It becomes the "H" state.

[0147] Additionally, for example, when signal line A(-1) is in the "L" state and signal line / A(-1) is in the "H" state, transistor Tr SG32 It becomes connected. Subsequently, address node n An－1 via address node n A And with voltage node n VSS Conduction, address node n An－1 This also becomes the "L" state. Subsequently, the drain-side gate selection line SGD... n－1 With voltage node n VSGD On, the drain-side gate selection line SGD n－1 It becomes the "H" state. Additionally, the source-side gate selection line SGS... n－1 With voltage node n VSGS Turn on, source-side select gate line SGS n－1 It becomes the "H" state.

[0148] [Write action]

[0149] Figure 23 This is a schematic top view used to explain the write operation of the semiconductor memory device according to the first embodiment. Furthermore, Figure 23 The three semiconductor layers 110 arranged in the X direction are designated as semiconductor layers 110a, 110b, and 110c, respectively. Furthermore, in Figure 23 The image shows that one of the multiple memory cells MC disposed on one side of the semiconductor layer 110b in the X direction is the selected memory cell MC. S Examples.

[0150] In a write operation, for example, for a connection to multiple selectable memory units (MCs) S The selection of the threshold voltage adjustment in the memory cell is based on the bit line BL supply voltage V. SRC Additionally, for connections to multiple selectable memory units (MCs) S The bit line BL supply voltage V of the selected memory cell without threshold voltage adjustment. DD The following describes the possibility of selecting multiple memory units (MCs). SThe memory cell selected for threshold voltage adjustment is called the "write memory cell MC", and the memory cell selected for not adjusting the threshold voltage is called the "disabled memory cell MC".

[0151] Additionally, during the write operation, in the selected transistor region R... SGD In the diagram, a voltage V is supplied to two nodes (N2 and N3 in the illustrated example) that correspond to semiconductor layer 110b among nodes N1 to N4. SGD A cutoff voltage V is supplied to all other nodes (nodes N0, N1, and N4 in the illustrated example). BB Voltage V SGD Greater than voltage V SRC .

[0152] Here, the voltage V SGD With voltage V SRC The voltage difference is greater than the threshold voltage required for the drain-side select transistor STD to function as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side select transistor STD connected to the write memory cell MC, transferring voltage V. SRC .

[0153] On the other hand, voltage V SGD With voltage V DD The voltage difference is less than the threshold voltage at which the drain-side selection transistor STD functions as an NMOS transistor. Therefore, the drain-side selection transistor STD connected to the disable memory cell MC is in the off state.

[0154] Additionally, during the write operation, in the selected transistor region R... SGS In this process, a cutoff voltage V is supplied to two via electrodes 120 disposed on one side and the other side of the semiconductor layer 110b in the X direction. BB Therefore, the source-side selection transistor STS becomes off.

[0155] Additionally, during the write operation, a write pass voltage V is supplied to the multiple via electrodes 120 and 140. PASS Write through voltage V PASS The degree to which the storage cell MC remains switched on regardless of the data recorded in it. Write operation is achieved via voltage V. PASS Greater than the readout voltage V READ Therefore, in the semiconductor layer 110b, the voltage of the conductive layer 170 is transmitted to the selected memory cell MC. S The drain region.

[0156] Additionally, during the write operation, the memory cell MC is selected. SThe gate electrode functions as the through-hole electrode 120, which supplies the programming voltage V. PGM Programming voltage V PGM Greater than the write pass voltage V PASS .

[0157] Here, a voltage V is supplied to the channel of semiconductor layer 110b corresponding to the write memory cell MC. SRC In such a semiconductor layer 110b with the select word line WL S A relatively large electric field is generated between them. As a result, electrons in the channels of semiconductor layer 110b tunnel through tunnel insulating layer 131 into charge storage layer 132. As a result, the threshold voltage for writing to memory cell MC increases.

[0158] On the other hand, the channel of the semiconductor layer 110b corresponding to the disabled memory cell MC becomes electrically floating, and the potential of this channel rises to the write pass voltage V through capacitive coupling with the non-select word line WL. PASS Left and right. In this semiconductor layer 110b, there is a select word line WL. S An electric field smaller than the stated electric field is generated between them. Therefore, electrons in the channels of semiconductor layer 110b will not tunnel into charge storage layer 132. Therefore, the threshold voltage of the storage cell MC is prevented from increasing.

[0159] In the write operation of the semiconductor memory device of the first embodiment, similar to the read operation, the following method is used: Figure 20 The method described performs storage block BLK or sub-block BLK. S The choice.

[0160] Figure 24 This is a schematic circuit diagram used to explain the write operation of the semiconductor memory device of the first embodiment.

[0161] In the write operation of the semiconductor memory device of the first embodiment, the same as in the read operation, a method is used as described in the reference. Figure 21 and Figure 22 The method described provides voltages to the drain-side select gate line SGD and the source-side select gate line SGS.

[0162] Furthermore, during the write operation of the semiconductor memory device in the first embodiment, when referring to Figure 22 After the described action is performed, such as Figure 24 As shown, set signal line RE to the "L" state and signal line / RE to the "H" state.

[0163] In this state, the charging circuit C PRC transistor Tr in SG11 It becomes ON. However, transistor TrSG12 It remains in a disconnected state. Therefore, address node n A The voltage is maintained at the reference. Figure 22 The state described.

[0164] Additionally, in this state, the discharge circuit C DSC transistor Tr in SG22 It becomes disconnected.

[0165] Additionally, in this state, the level shifter circuit C LSS All transistors Tr SG52 The level shifter circuit C becomes disconnected. LSS All transistors Tr SG54 It becomes ON. Therefore, a ground voltage V is supplied to all source-side selected gate lines (SGS). SS All source-side selected gate lines (SGS) are in the "L" state.

[0166] [Erase action]

[0167] Figure 25 and Figure 26 This is a schematic circuit diagram used to explain the erase operation of the semiconductor memory device of the first embodiment.

[0168] like Figure 25 As shown, during the erasure operation, a ground voltage V can also be supplied to the bus wiring BWL. SS .

[0169] Additionally, during an erasure operation, for example, the storage block BLK or sub-block BLK that becomes the object of the erasure operation can be erased. S One corresponding wiring drvgl is set to the "H" state, and the other wiring drvgl are set to the "L" state. Therefore, the storage block BLK or sub-block BLK that becomes the object of the erasure operation can also be set to the "H" state. S The corresponding transistor Tr in a single circuit drvg HV Set it to the ON state, and turn on the transistor Tr contained in the other circuits drvg. HV Set to disconnected state.

[0170] Alternatively, the wiring drvsl corresponding to the memory block BLK that is the target of the erase operation can be set to the "H" state, and the other wiring drvsl can be set to the "L" state. Therefore, the transistors Tr contained in the multiple (four in the illustrated example) circuits drvs corresponding to the memory block BLK that is the target of the erase operation can also be configured. HV Set it to the ON state, and turn on the transistors Tr contained in the other circuits drvs. HV Set to disconnected state.

[0171] In addition, such as Figure 26 As shown, multiple sub-blocks BLK that constitute the storage block BLK can also be combined. S Only a portion of the corresponding wiring DRVSL is set to the "H" state, while the remaining wiring DRVSL is set to the "L" state. Therefore, it is also possible to set only a portion (in the illustrated example, 1 to 3) of the sub-block BLK. S The corresponding transistor Tr in the DRVS circuit HV Set it to the ON state, and turn on the transistors Tr contained in the other circuits drvs. HV Set it to the off state. Using this method, it becomes relatively easy to adjust the object being erased.

[0172] [Effect]

[0173] For reference Figure 12 As explained above, the semiconductor memory device of the first embodiment includes multiple subarrays MCA. S With these multiple subarrays MCA S The corresponding configuration includes multiple sets of sub-word lines (SWL), multiple circuits (drvs) connected to these multiple sets of sub-word lines (SWL), and a set of global word lines (GWL) connected to these multiple circuits (drvs).

[0174] Based on such a structure, for example, as referenced Figure 20 As explained, by performing read operations, write operations, etc., the transistor Tr contained in any one of the multiple DRVS circuits is... HV Set it to the ON state, and turn on the transistors Tr contained in the other circuits drvs. HV Setting it to the off state can reduce the wiring capacity of the global word line (GWL) and enable high-speed read and write operations.

[0175] Additionally, as referenced Figure 26 As explained, by erasing any one of the multiple circuits DRVS during the erase operation, the transistor Tr contained in the DRVS is... HV Set it to the ON state, and turn on the transistors Tr contained in the other circuits drvs. HV Setting it to the disconnected state makes it relatively easy to adjust the object of the erase action.

[0176] Additionally, as referenced Figure 12 As explained, in the first embodiment, the global word line GWL is electrically connected to multiple sub-blocks BLK arranged in the Y direction. S .

[0177] In this configuration, since only one set of global word lines (GWLs) needs to be set for multiple memory blocks (BLKs), the wiring width of the global word lines (GWLs) can be increased. This allows for low resistance in the global word lines (GWLs) and high-speed read operations.

[0178] Additionally, as referenced Figure 17 As described, the decoding circuit DEC in the first embodiment SG Equipped with multiple drain-side selected gate lines (SGD) n－1 ~SGD n+1 and multiple source-side gate select lines (SGS) n－1 ~SGS n+1 The corresponding multiple address nodes n An－1 ~n An+1 .

[0179] In addition, the decoding circuit DEC SG Possessing address node n A Charging circuit C for charging PRC Address node n A Discharge circuit C DSC The address node n selected based on the input address signal. A With discharge circuit C DSC The address selection circuit C is turned on. ADS The address node n to be discharged according to the input signal. A The adjacent address node n A The discharge circuit C for charge discharge 2 / 3D C 2 / 3S and based on address node n A The state of the level shifter circuit C supplies voltage to either the drain-side gate line (SGD) or the source-side gate line (SGS). LSD C LSS .

[0180] This configuration, for example, can be implemented in a smaller area compared to multi-input NAND circuits that use one NMOS transistor and one PMOS transistor for each bit address. Furthermore, based on this configuration, for example, as... Figure 18 and Figure 19 As shown, two nodes N2 and N3 can be appropriately selected.

[0181] [Second Implementation]

[0182] Next, the semiconductor memory device according to the second embodiment will be described. In the following description, the same reference numerals are used for the same parts as in the semiconductor memory device of the first embodiment, and the description is omitted.

[0183] The semiconductor memory device of the second embodiment is configured in the same way as the semiconductor memory device of the first embodiment.

[0184] For reference Figure 12 As illustrated, the memory cell array (MCA) is divided into multiple regions (two in the illustrated example) in the Y direction. Each of these regions contains multiple memory blocks (BLKs).

[0185] Here, the semiconductor memory device of the first embodiment is capable of storing page PG or subpage PG. S This is set as the execution unit for read and write operations. Furthermore, the semiconductor memory device of the first embodiment can classify memory blocks (BLK) or sub-blocks (BLK) into memory blocks (BLK). S Set as the unit of execution for the erase action.

[0186] On the other hand, the semiconductor memory device of the second embodiment can perform read, write and erase operations across multiple regions divided in the Y direction.

[0187] For example, it is possible to select a subpage PG contained in one of multiple regions segmented in the Y direction. S , and the subpage PG contained in another region of multiple regions divided in the Y direction S They perform read and write operations together.

[0188] Similarly, it is possible to process the sub-blocks BLK contained in one of multiple regions divided in the Y direction. S BLK, a sub-block contained in another region of multiple regions divided in the Y direction. S Together, they perform the erasure action.

[0189] Figure 27 This is a schematic circuit diagram used to explain the read operation of the semiconductor memory device of the second embodiment.

[0190] For reference Figure 20 As explained, in the read operation of the first embodiment, for example, one wiring drvgl corresponding to the storage block BLK that is the object of the read operation is set to the "H" state, and the other wiring drvgl is set to the "L" state.

[0191] On the other hand, such as Figure 27 As shown, in the readout operation of the second embodiment, two or more wirings drvgl are set to the "H" state, and the other wirings drvgl are set to the "L" state. Therefore, the transistors Tr included in the two or more circuits drvg are... HV Set it to the ON state, and turn on the transistor Tr contained in the other circuits drvg. HV Set to disconnected state.

[0192] Additionally, it will be associated with multiple sub-blocks of BLK that are the objects of the read operation. S The corresponding multiple wiring lines are set to the "H" state, and the other wiring lines are set to the "L" state. This connects to the multiple sub-blocks BLK that are the objects of the read operation. S The corresponding transistors Tr in the multiple (four in the illustrated example) DRVS circuits HV Set it to the ON state, and turn on the transistors Tr contained in the other circuits drvs. HV Set to disconnected state.

[0193] In such a method, such as Figure 27 As illustrated, the sub-block BLK is connected to a portion of the block. S The sub-line SWL, and the sub-block BLK connected to other sub-blocks. S The sub-word line SWL is connected to the bus wiring BWL via different global word lines GWL. This method reduces the wiring capacity of the global word lines GWL, enabling high-speed read operations.

[0194] [Third Implementation]

[0195] Next, the semiconductor memory device according to the third embodiment will be described. In the following description, the same reference numerals are used for the same parts as in the semiconductor memory device of the first embodiment, and the description is omitted.

[0196] The semiconductor memory device of the third embodiment is configured essentially the same as the semiconductor memory device of the first or second embodiment. However, the semiconductor memory device of the third embodiment includes a decoding circuit DEC that is different from that of the semiconductor memory device of the first or second embodiment. SG '.

[0197] Figure 28 DEC represents the decoding circuit of the semiconductor memory device in the third embodiment. SG A schematic circuit diagram of the structure of '.

[0198] Decoding circuit DEC in the third embodiment SG 'Basically the same as the decoding circuit DEC of the first or second embodiment' SG They are identically constructed.

[0199] However, as Figure 28 As shown, in the third embodiment, the decoding circuit DEC SG In the circuit C of the level shifter... LSD A resistor R is installed in the current path between the output terminal of the converter and the drain-side select gate line SGD.LOAD Additionally, in the decoding circuit DEC SG In the circuit C of the level shifter... LSS A resistor R is installed in the current path between the output terminal of the converter and the source-side select gate line SGS. LOAD .

[0200] Based on this configuration, it is possible to suppress sharp rises and falls in current, and suppress level shifter circuit C. LSD C LSS The degradation of the converter in the process.

[0201] Furthermore, in the third embodiment, the transistor STD and the semiconductor layer 160 can also be selected on the drain side. Figure 6 A virtual storage unit is set between the storage units (MC). The virtual storage unit is constructed in the same way as the storage unit (MC). However, the virtual storage unit does not record data.

[0202] [Fourth Implementation]

[0203] Next, the semiconductor memory device according to the fourth embodiment will be described. In the following description, the same symbols are used for the parts that are the same as those in the semiconductor memory device of the first embodiment, and the description is omitted.

[0204] The semiconductor memory device of the fourth embodiment is configured essentially the same as any of the semiconductor memory devices of the first to third embodiments. However, the semiconductor memory device of the fourth embodiment includes a transistor layer L. T4 to replace reference Figure 9 , Figure 10 The transistor layer L as described above T .

[0205] Figure 29 and Figure 30 This refers to the transistor layer L in the fourth embodiment. T4 A schematic cross-sectional view comprising a portion of it. Furthermore, in Figure 29 and Figure 30 In addition to illustrating the transistor layer L, T4 In addition, examples are shown of those disposed in transistor layer L. T4 The wiring layer M0 below, and the transistor layer L T4 The wiring layers M1 and M2 above.

[0206] transistor layer L T4 Basically with transistor layer L T They are constructed in the same way. However, the transistor layer L T4 Includes such as Figure 29 The illustrated transistor Tr LV4 and such Figure 30The illustrated transistor Tr HV4 At least one of them.

[0207] like Figure 29 As shown, transistor Tr LV4 Basically with reference Figure 9 The transistor Tr described LV They are constructed in the same way. However, the transistor Tr LV4 Equipped with semiconductor layer 181 L The gate insulating layer 182' on the lower surface and the gate electrode 183' disposed on the lower surface of the gate insulating layer 182'.

[0208] The gate insulating layer 182' may, for example, contain silicon oxide (SiO2). The gate electrode 183' is separated from the semiconductor layer 181 by the gate insulating layer 182'. L The lower surfaces of the gate electrode 183' and the semiconductor layer 181 are opposite each other. In the illustrated example, the area of ​​the gate electrode 183' is larger than the area of ​​the gate electrode 183. In the illustrated example, the gate electrode 183' and the semiconductor layer 181 are opposite each other. L The lower surfaces of the gate region 181g, source region 181s, region 181s', and region 181d' face each other. The gate electrode 183' may, for example, comprise a polycrystalline silicon (Si) containing N-type or P-type impurities, a metal such as tungsten (W), a silicide, or a multilayer film composed of two or more of these. The gate electrode 183' is connected to the gate electrode 183 via via contact electrodes v1, v1', wiring m1 in wiring layer M1, via contact electrode v2, and wiring m2 in wiring layer M2.

[0209] like Figure 30 As shown, transistor Tr HV4 Basically with reference Figure 10 The transistor Tr described HV They are constructed in the same way. However, the transistor Tr HV4 Equipped with semiconductor layer 181 H The gate insulating layer 182' on the lower surface and the gate electrode 183' disposed on the lower surface of the gate insulating layer 182'.

[0210] The gate electrode 183' is separated from the semiconductor layer 181 by the gate insulating layer 182'. H The lower surfaces of the gate electrode 183' and the semiconductor layer 181 are opposite each other. In the illustrated example, the area of ​​the gate electrode 183' is larger than the area of ​​the gate electrode 183. In the illustrated example, the gate electrode 183' and the semiconductor layer 181 are opposite each other. H The lower surfaces of the gate region 181g, source region 181s, region 181s' and region 181d' are facing each other.

[0211] Here, in the first to third embodiments, reference is made to... Figure 12 The circuit described is based on the reference. Figure 10 The transistor Tr described HV Composition. Here, when transmitting voltage from the global word line GWL to the sub-word line SWL, if the voltage of the global word line GWL rises, then a voltage is formed on semiconductor layer 181. H The potential in the channel also rises. This could potentially reduce the voltage difference between the channel and the gate, thus reducing the flow to the transistor Tr. HV The current decreases.

[0212] Here, for example, in reference Figure 30 The transistor Tr described HV4 In addition to the semiconductor layer 181 H A gate electrode 183' is disposed above it, and on the semiconductor layer 181 H The gate electrode 183' is also located below it. Therefore, in transistor Tr HV4 When driven, not only in semiconductor layer 181 H The upper surface forms electron channels, and also in semiconductor layer 181 H The lower surface of the transistor forms an electron channel. Therefore, the transistor Tr... HV4 The actual channel width is greater than that of the transistor Tr. HV The actual channel width. Therefore, with the same gate voltage, the current flowing to transistor Tr... HV4 The current flowing to transistor Tr is greater than HV The current.

[0213] In addition, in reference Figure 30 The transistor Tr described HV4 In the middle, it is possible to utilize the semiconductor layer 181 H The gate electrode 183' below it is used to suppress the signal from the semiconductor layer 181. H The influence of the electric field on the wiring m1 (not shown) in the wiring layer M1 below.

[0214] also, Figure 29 and Figure 30 The illustrated transistor can also serve as a reference. Figure 12 The circuit described uses transistors other than those in the DRVS circuit.

[0215] Additionally, transistor layer L T4 It may also not include transistor Tr LV4 Tr HV4 One of them. Additionally, the transistor layer L... T4 It can also contain transistors Tr LV Tr HV At least one of them.

[0216] In addition, Figure 29 and Figure 30 The example shown is a transistor Tr with its channel direction set to the Y direction. LV4 Tr HV4 However, transistor layer L T4 It can also include transistors Tr that set the channel direction to the X direction. LV4 Tr HV4 .

[0217] [Fifth Implementation]

[0218] Next, the semiconductor memory device according to the fifth embodiment will be described. In the following description, the same symbols are used for the parts that are the same as those in the semiconductor memory device of the fourth embodiment, and the description is omitted.

[0219] The semiconductor memory device of the fifth embodiment is configured essentially the same as that of the semiconductor memory device of the fourth embodiment. However, the semiconductor memory device of the fifth embodiment includes a transistor layer L. T5 to replace reference Figure 29 , Figure 30 The transistor layer L as described above T4 .

[0220] Figure 31 and Figure 32 This refers to the transistor layer L in the fifth embodiment. T5 A schematic cross-sectional view of a portion of the composition. Furthermore, in Figure 31 and Figure 32 In addition to illustrating the transistor layer L, T5 In addition, examples are shown of those disposed in transistor layer L. T5 The wiring layer M0 below, and the transistor layer L T5 The wiring layers M1 and M2 above.

[0221] transistor layer L T5 Basically with transistor layer L T4 They are constructed in the same way. However, the transistor layer L T5 Includes such as Figure 31 The illustrated transistor Tr LV5 and such Figure 32 The illustrated transistor Tr HV5 At least one of them.

[0222] Transistor Tr LV5 Tr HV5 Basically related to transistor Tr LV4 Tr HV4 They are constructed in the same way. However, in transistor Tr... LV5 Tr HV5In the transistor, gate electrode 183 and gate electrode 183' are electrically independent. LV5 Tr HV5 It is configured to supply different voltages to the gate electrode 183 and the gate electrode 183'.

[0223] In addition, transistor layer L T5 It may also not include transistor Tr LV5 Tr HV5 One of them. Additionally, the transistor layer L... T5 It can also contain transistors Tr LV Tr HV At least one of them. Additionally, transistor layer L... T5 It can also contain transistors Tr LV4 Tr HV4 At least one of them.

[0224] In addition, Figure 31 and Figure 32 The example shown is a transistor Tr with its channel direction set to the Y direction. LV5 Tr HV5 However, transistor layer L T5 It can also include transistors Tr that set the channel direction to the X direction. LV5 Tr HV5 .

[0225] [Sixth Implementation]

[0226] Next, the semiconductor memory device according to the sixth embodiment will be described. In the following description, the same symbols are used for the parts that are the same as those in the semiconductor memory device of the first embodiment, and the description is omitted.

[0227] The semiconductor memory device of the sixth embodiment is configured in the same manner as the semiconductor memory device of any one of the embodiments of the first to fifth embodiments.

[0228] Figure 33 This is a schematic circuit diagram used to illustrate the semiconductor memory device of the sixth embodiment. Figure 33 The diagram illustrates the memory string MS and the sense amplifier circuit SA.

[0229] In the illustrated example, the drain electrode of the drain-side selection transistor STD is connected to the sense amplifier circuit SA via node N5. The sense amplifier circuit SA includes a readout circuit C. SAR and writing circuit C SAW .

[0230] Readout circuit C SAR Equipped with transistor Tr SA1 Tr SA2 .

[0231] Transistor Tr SA1 One of the source and drain electrodes is connected to voltage node n. VDD Or voltage node n VSS Transistor Tr SA1 The other of the source and drain electrodes is connected to the transistor Tr. SA2 The source electrode or drain electrode of a transistor. SA1 The gate electrode of transistor Tr is connected to node N5. During the readout operation, transistor Tr... SA1 The state of node N5 determines whether it is connected or disconnected.

[0232] Transistor Tr SA2 The source or drain electrode is connected to node N6. Transistor Tr SA2 The gate electrode of transistor Tr is connected to signal line RE. SA2 Based on the read-out enable signal input to signal line RE, node N6 is connected to transistor Tr. SA1 Conduction. In transistor Tr... SA1 When the circuit is on, node N6 is charged to voltage V. DD Until then, or until discharged to ground voltage V SS Up to that point. In transistor Tr SA1 Maintain the voltage at node N6 when it is in the off state.

[0233] Write circuit C SAW Equipped with transistor Tr SA3 Tr SA4 .

[0234] Transistor Tr SA3 The drain electrode is connected to voltage node n VDD Transistor Tr SA3 The source electrode of transistor Tr is connected to node N5. SA3 During the write operation, node N5 is precharged to voltage V. DD until.

[0235] Transistor Tr SA4 The drain electrode of transistor Tr is connected to node N6. SA4 The source electrode of transistor Tr is connected to node N5. SA4 The gate electrode of transistor Tr is connected to signal line WE. SA4 The write enable signal input to signal line WE enables nodes N6 and N5 to conduct. When the voltage of node N6 is in the "H" state, the voltage of node N5 remains at voltage V. DDWith the voltage at node N6 in the "L" state, node N5 is discharged to the ground voltage V. SS until.

[0236] Ideally, here, transistor Tr... SA1 This is a transistor used to detect the voltage at node N5, and it has uniform characteristics. Transistor Tr SA1 For example, it is also possible to utilize, such as Figure 9 The illustrated transistor Tr LV Implementation. However, in transistor Tr LV In the middle, semiconductor layer 181 L It includes polycrystalline silicon (Si), etc. Here, there exists a semiconductor layer 181. L Uneven grain boundary positions within the transistor can lead to problems with the transistor's Tr. SA1 The threshold voltage may also be uneven. In such cases, the readout operation may not be performed properly.

[0237] Therefore, the semiconductor memory device of this embodiment includes a transistor layer L. T6 To replace transistor layer L T Transistor layer L T6 Includes transistors Tr that can suppress threshold voltage non-uniformity LV6 .

[0238] Figure 34 It represents transistor layer L T6 A schematic cross-sectional view of a portion of the composition. Furthermore, in Figure 34 In addition to illustrating the transistor layer L, T6 In addition, examples are shown of those disposed in transistor layer L. T6 The wiring layer M0 below, and the transistor layer L T6 The upper wiring layer M1.

[0239] like Figure 34 As shown, transistor Tr LV6 Basically related to transistor Tr LV They are constructed in the same way. However, in transistor Tr... LV6 Below it, there is a structure with a thermal conductivity different from that of the embedded insulating layer 102, such as silicon dioxide (SiO2).

[0240] exist Figure 34 In this example, a heat sink 185 is shown as having a thermal conductivity different from that of the embedded insulating layer 102. The heat sink 185 extends along the semiconductor layer 181. L The lower surface extends in both the X and Y directions. The heat sink 185 may contain metals such as tungsten (W), conductive metal compounds such as titanium nitride (TiN) or tantalum nitride (TaN), or laminated films of these materials.

[0241] Additionally, a heat dissipation section 186 is disposed on the upper surface of the heat sink 185 at a position overlapping with the gate electrode 183 when viewed from above. The heat dissipation section 186 and the semiconductor layer 181... L The distance between the heat sink 185 and the semiconductor layer 181 is smaller than that between other parts of the heat sink 185 and the semiconductor layer 181. L The distance between the heat sink 186 and the semiconductor layer 181. L The distance is, for example, about 5nm to 10nm. Additionally, other parts of the heat sink 185 are connected to the semiconductor layer 181. L The distance between them is, for example, 10 nm or more. Additionally, the heat sink 186 and the semiconductor layer 181... L The distance is less than that between the wiring m0 and the semiconductor layer 181 L The distance. The heat dissipation part 186 contains the same material as the heat sink 185.

[0242] In addition, an insulating layer 102 is embedded to cover the outer peripheral surface of the through-hole contact electrode v0.

[0243] Based on this configuration, in semiconductor layer 181 L In the crystallization process, semiconductor layer 181 L The heat in the semiconductor layer 181 is dissipated through the heat dissipation portion 186 of the heat sink 185. L In this process, a thermal gradient is formed, where the temperature is lower closer to the heat sink 186 and higher further away from the heat sink 186. Therefore, in the semiconductor layer 181... L Crystallization begins near the heat dissipation section 186. This allows for the suppression of crystallization in the semiconductor layer 181. L When viewed from above, the portion overlapping with the gate electrode 183 (the gate region) forms grain boundaries. This allows for the suppression of crystal boundaries in the transistor Tr. LV6 Uneven threshold voltage.

[0244] In addition, transistor Tr LV6 It can be used as a transistor Tr SA1 ( Figure 33 It can also be used as a transistor Tr. SA1 Other transistors are used.

[0245] Additionally, transistor layer L T6 It can also contain transistors Tr LV5 Tr HV5 At least one of them. Additionally, transistor layer L... T6 It can also contain transistors Tr LV Tr HV At least one of them. Additionally, transistor layer L... T6 It can also contain transistors TrLV4 Tr HV4 At least one of them.

[0246] In addition, Figure 34 The example shown is a transistor Tr with the channel direction set to the Y direction. LV6 However, transistor layer L T6 It can also include transistors Tr that set the channel direction to the X direction. LV6 .

[0247] [Seventh Implementation]

[0248] Next, the semiconductor memory device according to the seventh embodiment will be described. In the following description, the same reference numerals are used for the same parts as in the semiconductor memory device of the sixth embodiment, and the description is omitted.

[0249] The semiconductor memory device of the seventh embodiment is configured in the same way as the semiconductor memory device of the sixth embodiment.

[0250] However, the semiconductor memory device of the seventh embodiment includes a transistor layer L. T7 to replace the transistor layer L T6 .

[0251] Figure 35 It represents transistor layer L T7 A schematic cross-sectional view of a portion of the composition. Furthermore, in Figure 35 In addition to illustrating the transistor layer L, T7 In addition, examples are shown of those disposed in transistor layer L. T7 The wiring layer M0 below, and the transistor layer L T7 The upper wiring layer M1.

[0252] like Figure 35 As shown, transistor layer L T7 Equipped with transistor Tr LV7 .like Figure 35 As shown, transistor Tr LV7 Basically related to transistor Tr LV6 They are constructed in the same way. However, in transistor Tr... LV7 Below the surface, a heat sink 185' is provided, which has a different thermal conductivity than the embedded insulating layer 102. Furthermore, a heat dissipation section 186' is provided on the upper surface of the heat sink 185' at a position overlapping with the gate electrode 183 when viewed from above.

[0253] Here, the heat sink 185' and heat sink 186' are essentially constructed the same as those of the heat sink 185 and heat sink 186. However, the heat sink 186 contains the same material as the heat sink 185. On the other hand, the heat sink 186' contains a different material than the heat sink 185'. For example, the heat sink 186' may also contain conductive metal compounds such as titanium nitride (TiN) or tantalum nitride (TaN). In addition, the heat sink 185' may, for example, contain a metal such as tungsten (W).

[0254] In addition, transistor Tr LV7 It can be used as a transistor Tr SA1 ( Figure 33 It can also be used as a transistor Tr. SA1 Other transistors are used.

[0255] Additionally, transistor layer L T7 It can also contain transistors Tr LV Tr HV At least one of them. Additionally, transistor layer L... T7 It can also contain transistors Tr LV4 Tr HV4 At least one of them. Additionally, transistor layer L... T7 It can also contain transistors Tr LV5 Tr HV5 At least one of them. Additionally, transistor layer L... T7 It can also contain transistors Tr LV6 .

[0256] In addition, Figure 35 The example shown is a transistor Tr with the channel direction set to the Y direction. LV7 However, transistor layer L T7 It can also include transistors Tr that set the channel direction to the X direction. LV7 .

[0257] [Eighth Implementation]

[0258] Next, the semiconductor memory device according to the eighth embodiment will be described. In the following description, the same symbols are used for the same parts as in the semiconductor memory device of the sixth embodiment, and the description is omitted.

[0259] The semiconductor memory device of the eighth embodiment is configured in the same way as the semiconductor memory device of the sixth embodiment.

[0260] However, the semiconductor memory device of the eighth embodiment includes a transistor layer L. T8 to replace the transistor layer L T6 .

[0261] Figure 36It represents transistor layer L T8 A schematic cross-sectional view of a portion of the composition. Furthermore, in Figure 36 In addition to illustrating the transistor layer L, T8 In addition, examples are shown of those disposed in transistor layer L. T8 The wiring layer M0 below, and the transistor layer L T8 The upper wiring layer M1.

[0262] like Figure 36 As shown, transistor layer L T8 Equipped with transistor Tr LV8 Transistor Tr LV8 Basically related to transistor Tr LV6 They are constructed in the same way. However, in transistor Tr... LV8 Below, a plurality of voids CAV are provided, which have a different thermal conductivity than the buried insulating layer 102. In the illustrated example, the plurality of voids CAV are arranged along the semiconductor layer 181. L The lower surfaces are arranged in the Y direction.

[0263] The gap CAV can be formed simultaneously with the contact hole corresponding to the through-hole contact electrode v0. In this case, the lower end of the gap CAV can be positioned at the same height as the lower end of the through-hole contact electrode v0. Alternatively, the lower end of the gap CAV can be positioned below the lower end of the through-hole contact electrode v0. Furthermore, the upper end of the gap CAV can be positioned below the upper end of the through-hole contact electrode v0.

[0264] Based on this configuration, in semiconductor layer 181 L In the crystallization process, semiconductor layer 181 L The heat is dissipated through the through-hole contact electrode v0 and the wiring m0 in the wiring layer M0. Additionally, due to the lower thermal conductivity of the void CAV, the semiconductor layer 181 is located near the void CAV. L Heat is not easily dissipated in the semiconductor layer 181. L In this process, a thermal gradient is formed, where the temperature is lower closer to the via contact electrode v0 and higher further away from the via contact electrode v0. Therefore, in semiconductor layer 181... L In this process, crystallization begins near the via contact electrode v0. This suppresses crystallization in the semiconductor layer 181. L When viewed from above, the portion overlapping with the gate electrode 183 (the gate region) forms grain boundaries. This allows for the suppression of crystal boundaries in the transistor Tr. LV8 Uneven threshold voltage.

[0265] In addition, transistor Tr LV8 It can be used as a transistor TrSA1 ( Figure 33 It can also be used as a transistor Tr. SA1 Other transistors are used.

[0266] Additionally, transistor layer L T8 It can also contain transistors Tr LV Tr HV At least one of them. Additionally, transistor layer L... T8 It can also contain transistors Tr LV4 Tr HV4 At least one of them. Additionally, transistor layer L... T8 It can also contain transistors Tr LV5 Tr HV5 At least one of them. Additionally, transistor layer L... T8 It can also contain transistors Tr LV6 Additionally, transistor layer L T8 It can also contain transistors Tr LV7 .

[0267] In addition, Figure 36 The example shown is a transistor Tr with the channel direction set to the Y direction. LV8 However, transistor layer L T8 It can also include transistors Tr that set the channel direction to the X direction. LV8 .

[0268] [Ninth Implementation]

[0269] Next, the semiconductor memory device according to the ninth embodiment will be described. In the following description, the same reference numerals are used for the same parts as in the semiconductor memory device of the eighth embodiment, and the description is omitted.

[0270] The semiconductor memory device of the ninth embodiment is configured in the same way as the semiconductor memory device of the eighth embodiment.

[0271] However, the semiconductor memory device of the ninth embodiment includes a transistor layer L. T9 to replace the transistor layer L T8 .

[0272] Figure 37 It represents transistor layer L T9 A schematic cross-sectional view of a portion of the composition. Furthermore, in Figure 37 In addition to illustrating the transistor layer L, T9 In addition, examples are shown of those disposed in transistor layer L. T9 The wiring layer M0 below, and the transistor layer L T9 The upper wiring layer M1.

[0273] like Figure 37 As shown, transistor layer L T9 Equipped with transistor Tr LV9 Transistor Tr LV9 Basically related to transistor Tr LV8 They are constructed in the same way. However, in transistor Tr... LV9 Below, a plurality of insulating members 187 are disposed with a thermal conductivity different from that of the embedded insulating layer 102. In the illustrated example, the plurality of insulating members 187 are arranged along the semiconductor layer 181. L The lower surfaces are arranged in the Y direction.

[0274] Although the illustration is omitted, the thermal conductivity of the insulating component 187 is lower than that of the embedded insulating layer 102. The insulating component 187 may also contain, for example, carbon (C).

[0275] The insulating member 187 may, for example, be formed within a through hole formed simultaneously with the contact hole corresponding to the through hole contact electrode v0. In this case, the lower end of the insulating member 187 may be positioned at the same height as the lower end of the through hole contact electrode v0. Alternatively, the lower end of the insulating member 187 may be positioned below the lower end of the through hole contact electrode v0. Furthermore, the upper end of the insulating member 187 may be positioned below the upper end of the through hole contact electrode v0.

[0276] In this configuration, the same effect as the semiconductor memory device of the eighth embodiment can be achieved.

[0277] In addition, transistor Tr LV9 It can be used as a transistor Tr SA1 ( Figure 33 It can also be used as a transistor Tr. SA1 Other transistors are used.

[0278] Additionally, transistor layer L T9 It can also contain transistors Tr LV Tr HV At least one of them. Additionally, transistor layer L... T9 It can also contain transistors Tr LV4 Tr HV4 At least one of them. Additionally, transistor layer L... T9 It can also contain transistors Tr LV5 Tr HV5 At least one of them. Additionally, transistor layer L... T9 It can also contain transistors Tr LV6 Additionally, transistor layer L T9 It can also contain transistors Tr LV7 Additionally, transistor layer L T9 It can also contain transistors TrLV8 .

[0279] In addition, Figure 37 The example shown is a transistor Tr with the channel direction set to the Y direction. LV9 However, transistor layer L T9 It can also include transistors Tr that set the channel direction to the X direction. LV9 .

[0280] [Other implementation methods]

[0281] The semiconductor memory devices according to the first to ninth embodiments have been described above. However, the configurations described above are merely examples, and specific configurations can be adjusted as appropriate.

[0282] For example, Figure 17 The illustrated decoding circuit DEC SG Equipped with 2 discharge circuits C 2 / 3D C 2 / 3S However, for example, these two discharge circuits C can also be omitted. 2 / 3D C 2 / 3S one of.

[0283] Additionally, for example, in Figure 17 The illustrated decoding circuit DEC SG In the middle, the address selection circuit C ADS Set in address node n A With discharge circuit C DSC The current path between them. However, the address selection circuit C ADS It can also be set in address node n A With charging circuit C PRC The current path between them. In such a case, for example, in the reference... Figure 21 In the timing sequence described, it is also possible to refer only to one address node n corresponding to the address data. A Charging can be performed selectively.

[0284] Additionally, for example, in Figure 17 The illustrated decoding circuit DEC SG In the middle, the discharge circuit C 2 / 3D C 2 / 3S The multiple transistors Tr contained therein SG31 Tr SG32 The gate electrodes of these multiple transistors are connected in a common manner, with every other one connected. SG31 Tr SG32 As long as we can get each address node n A Appropriately associated with an address node n A Simply connect them, and connect multiple transistors Tr SG31 TrSG32 The gate electrode connection of multiple transistors can be properly adjusted. SG31 Tr SG32 The gate electrodes can also be connected in a common manner every two or every three.

[0285] Additionally, for example, in Figure 17 The illustrated decoding circuit DEC SG In the middle, the level shifter circuit C LSD It features multiple converters. Additionally, it includes a level shifter circuit C. LSS It features multiple time-controlled converters. However, the level shifter circuit C... LSD C LSS As long as the address node n can be obtained A If the signal is amplified, the specific composition can be adjusted appropriately.

[0286] [other]

[0287] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.

[0288] [Explanation of Symbols]

[0289] 110: Semiconductor layer

[0290] 120: Through-hole electrode

[0291] 130: Gate insulating layer

[0292] 140: Conductive layer

[0293] 150: Conductive layer

[0294] 160: Semiconductor layer

[0295] 170: Conductive layer

[0296] nA: Address node

[0297] CPRC: Charging circuit

[0298] CDSC: Discharge Circuit

[0299] CADS: Address Selection Circuit

[0300] C2 / 3D, C2 / 3S: Discharge circuit

[0301] CLSD, CLSS: Level shifter circuits.

Claims

1. A semiconductor memory device comprising a memory cell array and peripheral circuitry, The storage cell array includes: A plurality of first semiconductor layers extend in a first direction and are arranged in a second direction intersecting the first direction; and A plurality of first through-hole electrodes are respectively disposed between two adjacent first semiconductor layers in the second direction; The peripheral circuitry includes: Multiple first nodes are provided, corresponding to the multiple first through-hole electrodes; A charging circuit that charges the plurality of first nodes; The discharge circuit discharges the plurality of first nodes; An address selection circuit is configured on the current path between the plurality of first nodes and the charging circuit, or on the current path between the plurality of first nodes and the discharging circuit, and, based on the input address signal, enables one of the plurality of first nodes to be connected to the charging circuit or the discharging circuit. A plurality of first transistors are respectively disposed on the current path between two nodes of the plurality of first nodes; as well as Multiple amplifier circuits are provided corresponding to the multiple first through-hole electrodes, and each circuit has an input terminal connected to any one of the multiple first nodes and an output terminal connected to any one of the multiple first through-hole electrodes.

2. The semiconductor memory device according to claim 1, wherein... It includes a resistive element disposed on the current path between any one of the plurality of first through-hole electrodes and the output terminal of any one of the plurality of amplifier circuits.

3. The semiconductor memory device according to claim 2, wherein... It has a dummy storage unit, which is disposed on the current path between any one of the plurality of first through-hole electrodes and the resistive element.

4. The semiconductor memory device according to claim 1, wherein In at least one of the read and write operations, The address signal is input to the address selection circuit. A voltage is supplied to a portion of the gate electrodes of the plurality of first transistors to turn the first transistors on.

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