Memory device and method of operation thereof

Abstract

A memory device and an operating method thereof are provided herein. The memory device can include a memory cell string including a plurality of memory cells coupled with a plurality of word lines, a peripheral circuit configured to perform an operation of applying an operating voltage to a selected word line and an operation of applying a pass voltage to an unselected word line among the plurality of word lines, and an operation controller configured to control the peripheral circuit to perform a discharge operation sequentially lowering a voltage of the plurality of word lines from at least one center word line located in a center portion with respect to the memory cell string, to a word line located in an outermost portion with respect to the memory cell string, adjacent to a selection line, among the plurality of word lines, after the operation has been performed.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0037659, filed on March 25, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to electronic devices, and more particularly to memory devices and methods of operating such memory devices. Background Technology

[0004] Memory devices are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Memory devices are broadly classified into volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices in which the data stored is lost when power is interrupted. Representative examples of volatile memory devices include static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices that retain the stored data even when power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is broadly classified into NOR and NAND types. Summary of the Invention

[0006] One embodiment of this disclosure may provide a memory device. The memory device may include: a memory cell string including a plurality of memory cells coupled to a plurality of word lines; peripheral circuitry configured to perform operations of applying an operating voltage to selected word lines among the plurality of word lines, and operations of applying a voltage to unselected word lines among the plurality of word lines; and an operation controller configured to control the peripheral circuitry to perform a discharge operation after an operation has been performed, the discharge operation sequentially reducing the voltage of the plurality of word lines from at least one central word line located at the center of the plurality of word lines relative to the memory cell string, to the outermost word line located relative to the memory cell string and adjacent to the selected line.

[0007] One embodiment of this disclosure provides a method for operating a memory device. The method may include: applying an operating voltage to selected word lines among a plurality of word lines coupled to a plurality of memory cells included in a memory cell string; performing an operation to apply voltage to unselected word lines among the plurality of word lines; and, after the operation has been performed, performing a discharge operation, the discharge operation sequentially reducing the voltage of the plurality of word lines from at least one central word line located at the center of the plurality of word lines relative to the memory cell string, to the outermost word line located relative to the memory cell string and adjacent to the selected line. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0009] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0010] Figure 3 It's a diagram. Figure 2 A diagram showing the structure of any one of the multiple memory blocks BLK1 to BLKz.

[0011] Figure 4 It is a diagram illustrating the threshold voltage distribution of memory cells based on the programming operations of memory devices.

[0012] Figure 5 This is a diagram illustrating the read operation of a memory device.

[0013] Figure 6 It is a diagram illustrating the changes in channel potential during programming and reading operations.

[0014] Figure 7 This is a diagram illustrating a discharge operation according to an embodiment of the present disclosure.

[0015] Figure 8 This is a diagram illustrating a first embodiment of a discharge operation according to an embodiment of the present disclosure.

[0016] Figure 9 This is a diagram illustrating a second embodiment of the discharge operation according to one embodiment of the present disclosure.

[0017] Figure 10 This is a diagram illustrating a third embodiment of the discharge operation according to one embodiment of the present disclosure.

[0018] Figure 11 This is a flowchart illustrating a discharge operation according to an embodiment of the present disclosure.

[0019] Figure 12 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0020] Figure 13 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0021] Figure 14 This is a block diagram illustrating a user system employing a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural or functional descriptions of the embodiments of this disclosure described in this specification or application are illustrated to illustrate embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in the specification or application.

[0023] Various embodiments of this disclosure relate to memory devices capable of improving negative boost during word line discharge operation, and methods of operating such memory devices.

[0024] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0025] refer to Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device that stores data under the control of a host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system.

[0026] The memory system 50 can be manufactured as any of a variety of storage devices based on a host interface for communicating with the host 300. For example, the memory system 50 can be implemented as any of a variety of storage devices, such as solid-state drives (SSDs), multimedia cards (eMMC, mini-MMC, RS-MMC, or micro-MMC), secure digital cards (eMMC, mini-SD, or micro-SD), universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, PCI express (PCI-E) card-type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0027] The memory system 50 can be manufactured in any of the various package types. For example, the memory system 50 can be manufactured in any of the various package types, such as point-of-purchase (POP), system-in-package (SIP), system-on-a-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0028] The memory device 100 can store data. The memory device 100 can operate based on the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0029] Each memory cell in the memory unit can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0030] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A single memory block may include multiple pages. In one embodiment, a page may be a unit where data is stored in memory device 100 or where data stored in memory device 100 is read. A memory block may be a unit for erasing data.

[0031] In one embodiment, memory device 100 may be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory device, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). In this specification, for ease of description, it is described based on the assumption that memory device 100 is NAND flash memory.

[0032] Memory device 100 can receive commands and addresses from memory controller 200 and can access regions of the memory cell array selected by address. Memory device 100 can perform operations instructed by commands on the regions selected by address. For example, memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a write operation, memory device 100 can program data into the regions selected by address. During a read operation, memory device 100 can read data from the regions selected by address. During an erase operation, memory device 100 can erase the data stored in the regions selected by address.

[0033] In one embodiment, the memory device 100 may include an operation controller 140.

[0034] The operation controller 140 can control programming and reading operations performed on memory cells. A programming operation can be an operation that stores data in a memory cell. Specifically, a programming operation can be an operation that increases the threshold voltage of a memory cell based on the data to be stored in the memory cell. When a programming operation is performed, each memory cell in the memory cell can have a threshold voltage corresponding to any one of a plurality of programming states. The plurality of programming states can be specified based on the number of data bits stored in a memory cell. For example, when data is programmed according to a three-level cell (TLC) scheme where three bits of data are stored in a memory cell, the plurality of programming states can indicate an erase state and first through seventh programming states. After a programming operation has been performed, the threshold voltage of the memory cell can be determined based on the data to be stored in the memory cell. Based on the data to be stored in the corresponding memory cell, each memory cell in the memory cell can use any one of the plurality of programming states as the target programming state.

[0035] In one embodiment, the programming operation may include multiple programming cycles. Each programming cycle may include a programming voltage application operation and a verification operation. The programming voltage application operation may be an operation of increasing the threshold voltage of a memory cell by using a programming voltage. The verification operation may be an operation of identifying whether the threshold voltage of each memory cell has reached the threshold voltage corresponding to the target programming state by using a verification voltage.

[0036] In one embodiment, a read operation may be an operation of applying a read voltage to a word line coupled to a memory cell and sensing the data stored in the memory cell. A read operation may also be an operation of retrieving the data stored in the memory cell. Since the threshold voltage of the memory cell is determined based on the stored data, a read operation may be an operation of identifying the programming state corresponding to the threshold voltage of the memory cell among multiple programming states. For example, when the memory cell is programmed according to a TLC scheme, seven read voltages may be applied to identify which of the erase state and the first through seventh programming states corresponds to each of the threshold voltages of the memory cell.

[0037] In one embodiment, the operation controller 140 can control a discharge operation included in each of the programming and reading operations. The discharge operation can be an operation that reduces word line voltages. For example, the operation controller 140 can perform a discharge operation during programming and reading operations to reduce the voltages applied to multiple word lines to ground. Specifically, the operation controller 140 can reduce the programming voltage, verification voltage, verification pass voltage, and programming pass voltage applied to multiple word lines to ground during programming operations. The operation controller 140 can reduce the read voltage and read pass voltage applied to multiple word lines to ground during reading operations.

[0038] The memory controller 200 can control the overall operation of the memory system 50.

[0039] When power is applied to the memory system 50, the memory controller 200 can run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include: a host interface layer (HIL) that controls communication with the host 300; a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100; and a flash interface layer (FIL) that controls communication with the memory device 100.

[0040] In one embodiment, the memory controller 200 can receive data and a logical block address (LBA) from the host 300, and can translate the logical block address (LBA) into a physical block address (PBA), which indicates the address of a memory cell included in the memory device 100 where data is to be stored. In this specification, the terms "logical block address (LBA)" and "logical address" are used interchangeably. In this specification, the terms "physical block address (PBA)" and "physical address" are used interchangeably.

[0041] The memory controller 200 can control the memory device 100 to perform write, read, or erase operations in response to requests received from the host 300. During a write operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erase operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0042] In one embodiment, regardless of whether a request is received from host 300, memory controller 200 can autonomously generate commands, addresses, and data, and can send the commands, addresses, and data to memory device 100. For example, memory controller 200 can provide memory device 100 with commands, addresses, and data required for read and write operations involved in performing wear leveling, read recycling, garbage collection, etc.

[0043] In one embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 using an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for controlling the memory devices 100 such that the operation of at least two memory devices 100 overlaps with each other.

[0044] The host 300 can communicate with the memory system 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0045] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0046] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0047] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz may be coupled to the address decoder 121 via row lines RL. The memory blocks BLK1 to BLKz may be coupled to the page buffer group 123 via bit lines BL1 to BLm. Each memory block in BLK1 to BLKz may include multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Among the multiple memory cells, memory cells coupled to the same word line are defined as a page. In other words, the memory cell array 110 may include multiple pages. In one embodiment of this disclosure, each memory block in the memory cell array 110 including memory blocks BLK1 to BLKz may include multiple dummy cells. For a dummy cell, one or more dummy cells may be coupled in series between a drain-select transistor and a memory cell, and between a source-select transistor and a memory cell.

[0048] Each memory cell in the memory cell of the memory device 100 can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0049] Peripheral circuitry 120 can drive memory cell array 110. In one example, peripheral circuitry 120 can drive memory cell array 110 to perform programming, reading, and erasing operations under the control of control logic 130. In other examples, peripheral circuitry 120 can apply various drive voltages Vop to row lines RL and bit lines BL1 to BLm, or it can discharge the applied voltage under the control of control logic 130.

[0050] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0051] Address decoder 121 can be coupled to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to one embodiment of this disclosure, word lines may include ordinary word lines and pseudo word lines. According to one embodiment, row lines RL may also include pipe select lines.

[0052] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 can receive addresses from control logic 130.

[0053] Address decoder 121 can decode the block address among the received addresses. Address decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address RADD among the received addresses. Address decoder 121 can select at least one word line of the selected memory block by applying the voltage provided by voltage generator 122 to at least one word line according to the decoded row address RADD.

[0054] During programming operations, address decoder 121 can apply a programming voltage to the selected word line and can apply a pass voltage with a lower voltage level than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word line and can apply a verification pass voltage with a higher voltage level than the verification voltage to the unselected word line.

[0055] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and can apply a read voltage with a higher voltage level to the unselected word line.

[0056] Erasing operations on memory device 100 can be performed on a block-by-block basis. During an erase operation, the address ADDR input to memory device 100 may include a block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During an erase operation, address decoder 121 may apply a ground voltage to the word line coupled to the selected memory block.

[0057] Address decoder 121 can decode the column address in the received address ADDR. The decoded column address can be sent to page buffer set 123. In one embodiment, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0058] Voltage generator 122 can generate multiple drive voltages Vop using the external power supply voltage provided to memory device 100. Voltage generator 122 can operate under the control of control logic 130.

[0059] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the driving voltage of memory device 100.

[0060] In one embodiment, voltage generator 122 can generate various drive voltages Vop for programming, reading, and erasing operations in response to an operation signal OPSIG. Voltage generator 122 can generate multiple drive voltages Vop using either an external or internal power supply voltage. Voltage generator 122 can generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple programming pass voltages, multiple read voltages, and multiple read pass voltages.

[0061] Voltage generator 122 may include multiple pump capacitors that receive an internal power supply voltage to generate multiple drive voltages Vop with various voltage levels, and the multiple drive voltages Vop can be generated by selectively enabling the multiple pump capacitors under the control of control logic 130.

[0062] The generated driving voltage Vop can be provided to the memory cell array 110 through the address decoder 121.

[0063] Page buffer group 123 includes first to m page buffers PB1 to PBm. The first to m page buffers PB1 to PBm are coupled to memory cell array 110 through first to m bit lines BL1 to BLm, respectively. The first to m page buffers PB1 to PBm operate under the control of control logic 130.

[0064] The first to m-th page buffers PB1 to PBm can send data DATA to and receive data DATA from the data input / output circuit 124. During programming operations, the first to m-th page buffers PB1 to PBm can receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0065] During programming operations, when a programming pulse is applied to the selected word line, the first to m-th page buffers PB1 to PBm can transfer the DATA to be stored, received by the data input / output circuit 124, to the selected memory cell via bit lines BL1 to BLm. The memory cell in the selected page can be programmed based on the received data DATA. Memory cells coupled to bit lines with applied programming enable voltages (e.g., ground voltage) can have increased threshold voltages. The threshold voltage of memory cells coupled to bit lines with applied programming disable voltages (e.g., power supply voltage) can be maintained. During programming verification operations, the first to m-th page buffers PB1 to PBm can read the data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 to BLm.

[0066] During a read operation, page buffer group 123 can read data DATA from the memory cell in the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first to m-th page buffers PB1 to PBm.

[0067] During an erase operation, page buffer group 123 may allow bit lines BL1 to BLm to float. In one embodiment, page buffer group 123 may include column select circuitry.

[0068] In one embodiment, when data segments stored in some of the page buffers included in the page buffer group 123 are programmed into the memory cell array 110, the remaining page buffers can receive new data from the memory controller 200 and then store the new data.

[0069] The data input / output circuit 124 can be coupled to the first to m-th page buffers PB1 to PBm via the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0070] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 may output data DATA received from the first page buffer PB1 to the m-th page buffer PBm included in the page buffer group 123 to the external controller.

[0071] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current. In one example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 can output a pass signal to the control logic 130. In another example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 can output a failure signal to the control logic 130.

[0072] Control logic 130 can be coupled to address decoder 121, voltage generator 122, page buffer group 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0073] Control circuit 130 can control peripheral circuit 120 by generating various types of signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, page buffer control signal PBSIGNALS to page buffer group 123, and enable bit VRYBIT to sensing circuit 125. Additionally, control logic 130 can determine whether the verification operation passes or fails in response to pass / fail signal PASS / FAIL output from sensing circuit 125.

[0074] Figure 1 The operation controller 140 shown can be included Figure 2 The control logic 130 shown.

[0075] Operation controller 140 can control peripheral circuitry 120 to apply drive voltage Vop to the row lines RL and bit lines BL1 to BLm, to be used during programming and read operations. In one example, during a programming operation, operation controller 140 can control peripheral circuitry 120 to apply programming voltage, verification voltage, programming pass voltage, and verification pass voltage to multiple word lines. In one example, during a read operation, operation controller 140 can control peripheral circuitry 120 to apply read voltage and read pass voltage to multiple word lines. In one embodiment, during programming and read operations, operation controller 140 can control peripheral circuitry 120 to change the magnitude of the voltages on the multiple word lines. For example, after the verification voltage, verification pass voltage, read voltage, and read pass voltage have been applied to the multiple word lines, operation controller 140 can control peripheral circuitry 120 to apply a ground voltage to the multiple word lines.

[0076] More specifically, the operation controller 140 can control the voltage generator 122 to generate a drive voltage Vop for programming and reading operations. The voltage generator 122 can then provide the generated drive voltage Vop to the address decoder 121. The address decoder 121 can transmit the drive voltage Vop to multiple word lines. During programming and reading operations, the magnitude of the voltages on the multiple word lines can be varied based on the magnitude of the drive voltage Vop provided by the address decoder 121. Specifically, the magnitude of the voltages on the multiple word lines can be varied based on the drive voltage Vop applied during programming and reading operations.

[0077] Figure 3 It's a diagram. Figure 2A diagram showing the structure of any one of the multiple memory blocks BLK1 to BLKz.

[0078] Memory block BLKi can indicate, for example Figure 2 The memory blocks BLKi shown are any one of the memory blocks BLKl to BLKz.

[0079] refer to Figure 3 Multiple word lines arranged in parallel to each other can be coupled between a first select line and a second select line. Here, the first select line can be the source select line SSL, and the second select line can be the drain select line DSL. Specifically, the memory block BLKi can include multiple memory cell strings ST coupled between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be individually coupled to memory cell strings ST, and the source line SL can be commonly coupled to memory cell strings ST. Strings ST can be configured identically, and therefore, the memory cell string ST coupled to the first bit line BL1 will be described in detail by way of example.

[0080] A memory cell string ST may include a source selection transistor SST coupled in series with each other between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A single memory cell string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more memory cells than the memory cells MC1 to MC16 shown in the figure.

[0081] The source of the source select transistor SST can be coupled to the source line SL, and the drain of the drain select transistor DST can be coupled to the first bit line BL1. Memory cells MC1 to MC16 can be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different memory cell strings ST can be coupled to the source select line SSL, the gates of the drain select transistors DST included in different memory cell strings ST can be coupled to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be coupled to multiple word lines WL1 to WL16 respectively. Among the memory cells included in different memory cell strings ST, the group of memory cells coupled to the same word line can be referred to as a "physical page (PG)". Therefore, the memory block BLKi can include the same number of physical pages (PG) as the number of word lines WL1 to WL16.

[0082] A memory cell can store one bit of data. This cell is usually called a "single-level cell (SLC)". In this case, a physical page (PG) can store the data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include the same number of data bits as the number of cells included in a physical page (PG).

[0083] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store data corresponding to two or more logical pages (LPG).

[0084] Figure 4 It is a diagram illustrating the threshold voltage distribution of memory cells based on the programming operations of memory devices.

[0085] exist Figure 4 In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells (the number of cells).

[0086] refer to Figure 4 The threshold voltage distribution of memory cells can be changed from the initial state to the final programmed state based on programming operations.

[0087] exist Figure 4 In this context, the data is described based on the assumption that the programming is based on a TLC scheme where three bits of data are stored in a single memory cell.

[0088] The initial state can be a state where no programming operation is performed and the threshold voltage distribution of the memory cell is in the erase state E.

[0089] The final programming state can be the threshold voltage distribution of the memory cells to which the programming operation is performed. Each memory cell in the memory cells to which the programming operation is performed can have a threshold voltage corresponding to any one of a plurality of programming states. For example, in the case where data is programmed according to a three-level cell (TLC) scheme that stores three bits of data in a memory cell, the plurality of programming states can indicate an erase state E and first to seventh programming states PV1 to PV7. In one embodiment, each memory cell in the memory cells to which the programming operation is performed can have a threshold voltage corresponding to either erase state E or any one of the first to seventh programming states PV1 to PV7. Through the programming operation, the threshold voltage of each memory cell in the initial state can be increased to the threshold voltage corresponding to either erase state E or any one of the first to seventh programming states PV1 to PV7.

[0090] Each memory cell can use either the erase state E or any of the programming states PV1 through PV7 as its target programming state. The target programming state can be determined based on the data to be stored in the corresponding memory cell. Through the corresponding programming operation, each memory cell can have a threshold voltage corresponding to the target programming state in the final programming state.

[0091] In one embodiment, the memory device 100 can perform a verification operation to identify whether a threshold voltage of a memory cell has reached a threshold voltage corresponding to a target programming state. When a verification voltage is applied to a word line coupled to the memory cell, the memory device 100 can identify the threshold voltage of the memory cell by sensing the current flowing through the bit line coupled to the memory cell. For example, the memory device 100 can perform the verification operation by applying a first verification voltage Vvfy1 to a memory cell whose target programming state is a first programming state PV1. The first verification voltage Vvfy1 can be a threshold voltage corresponding to the first programming state PV1. The verification operation can pass when the threshold voltage of the memory cell whose target programming state is the first programming state PV1 is greater than the first verification voltage Vvfy1. The verification operation may fail when the threshold voltage of the memory cell whose target programming state is the first programming state PV1 is less than the first verification voltage Vvfy1. Similarly, the memory device 100 can perform the verification operation by applying second to seventh verification voltages Vvfy2 to Vvfy7 to memory cells whose target programming states are the second to seventh programming states PV2 to PV7.

[0092] Figure 5 This is a diagram illustrating the read operation of a memory device.

[0093] exist Figure 5 The text describes the data based on the assumption that the programming follows a TLC scheme where three bits of data are stored in a single memory cell. (See reference.) Figure 5The threshold voltage of each memory cell in a plurality of memory cells can be increased through a programming operation to a threshold voltage corresponding to any one of the erase state E and the first to seventh programming states PV1 to PV7. Thereafter, the memory device 100 can perform a read operation to retrieve data stored in the memory cell. Specifically, when a read voltage is applied to a word line coupled to a selected memory cell among the plurality of memory cells, the memory device 100 can sense the data stored in the selected memory cell by detecting a change in current on the bit line coupled to the selected memory cell. The data stored in the memory cell can vary based on the programming state of the memory cell. Specifically, different data segments can be stored based on any one of the erase state E and the first to seventh programming states PV1 to PV7 corresponding to the threshold voltage of each memory cell. Therefore, the memory device 100 can retrieve data by applying a first read voltage Vr1 to a memory cell storing data corresponding to the first programming state PV1. The first read voltage Vr1 can be a voltage used to distinguish between the erase state E and the first programming state PV1. Similarly, memory device 100 can acquire data segments stored in multiple memory cells using second to seventh read voltages Vr2 to Vr7. During a read operation, memory device 100 can apply read voltages Vr1 to Vr7 of different magnitudes to the multiple memory cells based on the programming state corresponding to threshold voltages of the multiple memory cells.

[0094] Figure 6 It is a diagram illustrating the changes in channel potential during programming and reading operations.

[0095] exist Figure 6 In the diagram, the horizontal axis represents the position of the transistor coupled between the source line SL and the bit line BL, and the vertical axis represents the channel potential.

[0096] exist Figure 6 For ease of description, this will be based on the assumption that seven word lines WL1 to WL7 are coupled to a single memory cell string. However, the embodiments are not limited to this and may have more or fewer word lines.

[0097] Figure 6 The channel potential shown can be a channel potential that has changed after the programming voltage application operation, verification operation, and read operation have terminated. The programming voltage application operation can be an operation that applies a programming voltage to the selected word line and applies a programming pass voltage to the unselected word line. The verification operation can be an operation that applies a verification voltage to the selected word line and applies a verification pass voltage to the unselected word line. The read operation can be an operation that applies a read voltage to the selected word line and applies a read pass voltage to the unselected word line.

[0098] After the programming voltage application operation, verification operation, and read operation have been terminated, the memory device 100 can perform a discharge operation to reduce the voltage of multiple word lines. For example, the memory device 100 can perform a discharge operation to apply a ground voltage to multiple word lines after the programming voltage application operation, verification operation, and read operation have been terminated. During the discharge operation, the transistors coupled to the source select line SSL and the drain select line DSL can be turned off. During the discharge operation, the voltage of the word lines coupled to the memory cells in the programming state can be discharged to the ground voltage first. Furthermore, the memory cell corresponding to the higher programming state among the multiple programming states can have a higher threshold voltage. For example, when a memory cell is programmed according to the TLC scheme, the memory cell programmed to the seventh programming state PV7 can have the highest threshold voltage. Furthermore, as the word line voltage decreases during the discharge operation, the memory cells with higher threshold voltages are first reduced to voltages below the threshold voltage, and therefore, the channels corresponding to the memory cells with higher threshold voltages may be turned off first. For example, as Figure 6 As shown, when the first and second memory cells, coupled to the outermost first word line WL1 and the seventh word line WL7 of the multiple word lines WL1 to WL7 relative to the memory cell string, are programmed to the seventh programming state PV7, the channels corresponding to the first and second memory cells can be cut off first during the discharge operation. Thereafter, the charge in the cutoff channel interval may undergo negative downward coupling, and therefore, the potential of all channels coupled to the memory cell string may be reduced to a negative state. The phenomenon of the potential of each channel coupled to the memory cell string decreasing to a negative state during the discharge operation is called "negative boost." That is, because the potential of each channel coupled to the memory cell string remains negative during the discharge operation, interference from changes in the threshold voltage of the memory cells may occur. Such interference may become severe when the first and second memory cells, coupled to the outermost first word line WL1 and the seventh word line WL7 of the multiple word lines WL1 to WL7 relative to the memory cell string, are programmed to the highest programming state.

[0099] Figure 7 This is a diagram illustrating a discharge operation according to an embodiment of the present disclosure.

[0100] exist Figure 7 The discharge operation shown will be described using examples. Figure 6 The multiple word lines WL1 to WL7 are shown.

[0101] refer to Figure 7The memory device 100 can perform word line setup (WL setup) and discharge operations. The word line setup (WL setup) can be any of a programming voltage application operation, a verification operation, and a read operation. In one embodiment, when the word line setup (WL setup) is a programming voltage application operation, the verification operation can be performed after the discharge operation has terminated. In one embodiment, when the word line setup (WL setup) is a verification operation, the programming voltage application operation can be performed after the discharge operation has terminated, using a read voltage with a different voltage level compared to the previous read voltage. In one embodiment, when the word line setup (WL setup) is a read operation, a subsequent read operation can be performed after the discharge operation has terminated, using a read voltage with a different voltage level than the previous read voltage.

[0102] During the time period from t1 to t2, memory device 100 may perform a word line setup operation (WL setup). Memory device 100 may apply an operating voltage Vs to a selected word line Sel_WL. The operating voltage Vs may be any of a programming voltage, a verification voltage, and a read voltage. In one embodiment, memory device 100 may increase the threshold voltage of a memory cell coupled to a selected word line Sel_WL by applying a programming voltage to the selected word line Sel_WL. In one embodiment, memory device 100 may identify whether the threshold voltage of a memory cell coupled to a selected word line Sel_WL has reached a threshold voltage corresponding to a target programming state by applying a verification voltage to the selected word line Sel_WL. In one embodiment, memory device 100 may sense data stored in a memory cell coupled to a selected word line Sel_WL by applying a read voltage to the selected word line Sel_WL.

[0103] During the time period from t1 to t2, memory device 100 may apply a pass voltage Vpass to the unselected word lines among a plurality of word lines, excluding the selected word line Sel_WL. The unselected word lines may include the center word line Center_WL, the first adjacent word line adj1_WL, the second adjacent word line adj2_WL, and the third adjacent word line adj3_WL. In one embodiment, when the operating voltage Vs is the programming voltage, the voltage of the pass voltage Vpass may be lower than the operating voltage Vs. In one embodiment, when the operating voltage Vs is the verification voltage or the read voltage, the voltage of the pass voltage Vpass may be higher than the operating voltage Vs. The pass voltage Vpass may be any one of the programming pass voltage, the verification pass voltage, and the read pass voltage. In one embodiment, when the programming voltage is applied to the selected word line Sel_WL, memory device 100 may apply a programming pass voltage to the unselected word lines. In one embodiment, when the verification voltage is applied to the selected word line Sel_WL, memory device 100 may apply a verification pass voltage to the unselected word lines. In one embodiment, when a read voltage is applied to the selected word line Sel_WL, the memory device 100 can apply a read voltage to an unselected word line.

[0104] During the time period from t1 to t2, memory device 100 may apply a turn-on voltage Von to the drain select line DSL and the source select line SSL. The voltage of the turn-on voltage Von may be higher than the threshold voltage of the transistor coupled to the drain select line DSL and the source select line SSL.

[0105] During the time period from t2 to t3, memory device 100 can perform a discharge operation. The voltages of multiple word lines Sel_WL, Center_WL, adj1_WL, adj2_WL, and adj3_WL can be reduced to the ground voltage Gnd through the discharge operation.

[0106] Specifically, during the time period from t2 to t2-1, memory device 100 can apply a ground voltage Gnd to the center word line Center_WL. The center word line Center_WL can be the central word line among multiple word lines Sel_WL, Center_WL, adj1_WL, adj2_WL, and adj3_WL. For example, in Figure 6 In this implementation, the center word line Center_WL can be the fourth word line WL4. However, in other embodiments, the number of center word lines can be different. For example, in... Figure 3In this context, the center word line Center_WL can correspond to two word lines, the eighth and ninth word lines WL8 and WL9. During a discharge operation, the memory device 100 can first apply the ground voltage Gnd to the center word line Center_WL, thereby causing the voltage of the center word line Center_WL to be discharged first.

[0107] During the period from t2 to t2-1, memory device 100 can apply ground voltage Gnd to drain select line DSL and source select line SSL.

[0108] During the time period from t2-1 to t2-2, memory device 100 can apply a ground voltage Gnd to the first adjacent word line adj1_WL. The first adjacent word line adj1_WL can be a word line directly adjacent to both sides of the center word line Center_WL. For example, in Figure 6 In this context, the center word line Center_WL can be the fourth word line WL4, and therefore, the first adjacent word line adj1_WL can correspond to the third word line WL3 and the fifth word line WL5. That is, after applying the ground voltage Gnd to the center word line Center_WL, the memory device 100 can apply the ground voltage Gnd to the first adjacent word line adj1_WL.

[0109] During the time period from t2-2 to t2-3, memory device 100 can apply a ground voltage Gnd to the second adjacent word line adj2_WL. The second adjacent word line adj2_WL can be a word line directly adjacent to the first adjacent word line adj1_WL and opposite to the center word line Center_WL. For example, in Figure 6 In this context, the first adjacent word line adj1_WL can correspond to the third and fifth word lines WL3 and WL5, and therefore, the second adjacent word line adj2_WL can correspond to the second word line WL2 and the sixth word line WL6. Furthermore, during the time period from t2-2 to t2-3, such as... Figure 6 As shown, when the sixth word line WL6 is the selected word line Sel_WL, the ground voltage Gnd can be applied to the selected word line Sel_WL. However, unlike this example, the memory device 100 can apply the ground voltage to the selected word line Sel_WL during the period from t2 to t2-1 when the ground voltage is applied to the center word line. That is, the discharge operation of the selected word line can be performed together with the discharge operation of the center word line Center_WL, or it can be performed at different times based on the degree of adjacency between the selected word line Sel_WL and the center word line Center_WL. After applying the ground voltage Gnd to the first adjacent word line adj1_WL, the memory device 100 can apply the ground voltage Gnd to the second adjacent word line adj2_WL.

[0110] During the time period from t2-3 to t3, memory device 100 can apply a ground voltage Gnd to the third adjacent word line adj3_WL. The third adjacent word line adj3_WL can be a word line directly adjacent to the second adjacent word line adj2_WL and opposite to the first adjacent word line adj1_WL. For example, in Figure 6 In this context, the second adjacent word line adj2_WL can correspond to the second word line WL2 and the sixth word line WL6, and therefore, the third adjacent word line adj3_WL can correspond to the first word line WL1 and the seventh word line WL7. After applying the ground voltage Gnd to the second word line adj2_WL, the memory device 100 can apply the ground voltage Gnd to the third adjacent word line adj3_WL. The third adjacent word line adj3_WL can be a word line directly adjacent to the select lines SSL and DSL. That is, the ground voltage Gnd can be finally applied to the third adjacent word line adj3_WL, which is directly adjacent to the select lines SSL and DSL.

[0111] The voltage of multiple word lines can be increased through a word line setup operation (WL setup) and decreased through a discharge operation. During the discharge operation, the memory device 100 can sequentially decrease the voltage of multiple word lines from the center word line Center_WL to the third adjacent word line adj3_WL directly adjacent to the select line. Specifically, during the discharge operation, the memory device 100 can sequentially apply a ground voltage to multiple word lines from the center word line Center_WL to the third adjacent word line adj3_WL directly adjacent to the select line. The select line can be a drain select line DSL or a source select line SSL.

[0112] In one embodiment, the memory device 100 may divide multiple word lines into multiple word line groups. During a discharge operation, the memory device 100 may sequentially apply a ground voltage to word line groups from the center sub-group located at the center of the memory cell string within the multiple word line groups, to the word line group adjacent to the select line and located at the outermost portion relative to the memory cell string within the multiple word line groups. Each word line group may include two or more word lines. For example, in Figure 3 In the middle, the word line group located in the center part can include the seventh to ninth word lines WL7 to WL9.

[0113] According to one embodiment of this disclosure, during a discharge operation, the voltage of the word line directly adjacent to the select line can be discharged to ground last. Therefore, even if the threshold voltage of the memory cell coupled to the word line directly adjacent to the select line is high, the phenomenon of the channel being cut off first during the discharge operation can be prevented. Furthermore, since the channel corresponding to the memory cell coupled to the word line directly adjacent to the select line is not cut off first during the discharge operation, the phenomenon of negative voltage boost can be resolved.

[0114] Figure 8 This is a diagram illustrating a first embodiment of a discharge operation according to an embodiment of the present disclosure.

[0115] exist Figure 8 Lieutenant General (omitted) Figure 7 Repeated descriptions of the same configuration. (See reference) Figure 8 The memory device 100 can perform word line setup and discharge operations.

[0116] During the time period from t1 to t2, memory device 100 can perform a word line setup operation (WL setup). Memory device 100 can apply an operating voltage Vs to the selected word line Sel_WL.

[0117] During the time period from t1 to t2, memory device 100 can apply voltage Vpass to the unselected word lines among the multiple word lines except for the selected word line Sel_WL.

[0118] During the time period from t2 to t3, memory device 100 can perform a discharge operation. Specifically, during the time period from t2 to t2-1, memory device 100 can apply an intermediate voltage Vm to the center word line Center_WL. The intermediate voltage Vm can be a voltage lower than the pass voltage Vpass.

[0119] During the time period from t2-1 to t2-2, memory device 100 may apply a ground voltage Gnd to the center word line Center_WL. Additionally, memory device 100 may apply an intermediate voltage Vm to the first adjacent word line adj1_WL.

[0120] During the time period from t2-2 to t2-3, memory device 100 may apply a ground voltage Gnd to the first adjacent word line adj1_WL. Additionally, memory device 100 may apply an intermediate voltage Vm to the second adjacent word line adj2_WL and the selected word line Sel_WL.

[0121] During the time period from t2-3 to t3, memory device 100 may apply a ground voltage Gnd to the second adjacent word line adj2_WL and the selected word line Sel_WL. Additionally, memory device 100 may apply an intermediate voltage Vm to the third adjacent word line adj3_WL.

[0122] During the period following t3, memory device 100 may apply ground voltage Gnd to the third adjacent word line adj3_WL.

[0123] During discharge operation, the memory device 100 according to an embodiment of the present disclosure may sequentially apply an intermediate voltage Vm to word lines from the center word line Center_WL to the third adjacent word line adj3_WL which is directly adjacent to the select lines SSL and DSL, and thereafter may apply a ground voltage Gnd to them.

[0124] Figure 9 This is a diagram illustrating a second embodiment of the discharge operation according to one embodiment of the present disclosure.

[0125] exist Figure 9 Lieutenant General (omitted) Figure 7 Repeated descriptions of the same configuration. (See reference) Figure 9 The memory device 100 can perform word line setup and discharge operations.

[0126] During the time period from t1 to t2, memory device 100 can perform a word line setup operation (WL setup). Memory device 100 can apply an operating voltage Vs to the selected word line Sel_WL.

[0127] During the time period from t1 to t2, memory device 100 can apply voltage Vpass to the unselected word lines among the multiple word lines except for the selected word line Sel_WL.

[0128] During the time period from t2 to t3, memory device 100 can perform a discharge operation. Specifically, during the time period from t2 to t2-1, memory device 100 can apply a ground voltage Gnd to the center word line Center_WL. When the voltage of the center word line Center_WL drops from the pass voltage Vpass to the ground voltage Gnd during the discharge operation, the difference in voltage magnitude can be the zeroth discharge magnitude ΔVdis0.

[0129] During the time period from t2 to t3, the memory device 100 may also apply a first discharge voltage Vdis1 to the first adjacent word line adj1_WL. The voltage of the first discharge voltage Vdis1 may be higher than the voltage of the ground voltage Gnd. When the voltage of the first adjacent word line adj1_WL drops from the pass voltage Vpass to the first discharge voltage Vdis1 during the discharge operation, the difference in voltage magnitude may be a first discharge size ΔVdis1. The first discharge size ΔVdis1 may be less than the zeroth discharge size ΔVdis0.

[0130] During the time period from t2 to t3, the memory device 100 may also apply a second discharge voltage Vdis2 to the second adjacent word line adj2_WL and the selected word line Sel_WL. The voltage of the second discharge voltage Vdis2 may be higher than the voltage of the first discharge voltage Vdis1. When the voltage of each second adjacent word line adj2_WL decreases from the pass voltage Vpass to the second discharge voltage Vdis2 during the discharge operation, the difference in voltage magnitude may be a second discharge size ΔVdis2. The second discharge size ΔVdis2 may be less than the first discharge size ΔVdis1. When the voltage of the selected word line Sel_WL decreases from the operating voltage Vs to the second discharge voltage Vdis2 during the discharge operation, the difference in voltage magnitude may be a fourth discharge size ΔVdis4. When the operating voltage Vs is a verification voltage or a read voltage, the fourth discharge size ΔVdis4 may be less than the second discharge size ΔVdis2. When the operating voltage Vs is a programming voltage, the fourth discharge size ΔVdis4 may be greater than the second discharge size ΔVdis2.

[0131] During the time period from t2 to t3, the memory device 100 may also apply a third discharge voltage Vdis3 to the third adjacent word line adj3_WL. The voltage of the third discharge voltage Vdis3 may be higher than the voltage of the second discharge voltage Vdis2. When the voltage of the third adjacent word line adj3_WL drops from the pass voltage Vpass to the third discharge voltage Vdis3 during the discharge operation, the difference in voltage magnitude may be the third discharge size ΔVdis3. The third discharge size ΔVdis3 may be less than the second discharge size ΔVdis2.

[0132] The memory device 100 according to embodiments of the present disclosure can apply discharge voltages of different magnitudes to multiple word lines during a discharge operation. Specifically, the memory device 100 can apply a smaller discharge voltage to word lines closer to the center of the memory cell string during a discharge operation. During the discharge operation, the magnitude of the discharge voltage applied to each word line can increase as the word line gets closer to the select line.

[0133] Figure 10 This is a diagram illustrating a third embodiment of the discharge operation according to one embodiment of the present disclosure.

[0134] exist Figure 10 Lieutenant General (omitted) Figure 7 and Figure 9 Repeated descriptions of the same configuration. (See reference) Figure 10 The memory device 100 can perform word line setup and discharge operations.

[0135] During the time period from t1 to t2, memory device 100 can perform a word line setup operation (WL setup). Memory device 100 can apply an operating voltage Vs to the selected word line Sel_WL.

[0136] During the time period from t1 to t2, memory device 100 can apply voltage Vpass to the unselected word lines among the multiple word lines except for the selected word line Sel_WL.

[0137] During the period from t2 to t3, the memory device 100 can perform a discharge operation. Specifically, during the period from t2 to t2-1, the memory device 100 can apply the ground voltage Gnd to the center word line Center_WL.

[0138] During the time period from t2-1 to t2-2, the memory device 100 may apply a first discharge voltage Vdisl to the first adjacent word line adjl_WL.

[0139] During the period from t2-2 to t2-3, the memory device 100 may apply a second discharge voltage Vdis2 to the second adjacent word line adj2_WL and the selected word line Sel_WL.

[0140] During the time period from t2-3 to t3, memory device 100 can apply a third discharge voltage Vdis3 to the third adjacent word line adj3_WL. The magnitudes of the first to third discharge voltages Vdis1 to Vdis3 can be set to a reference value. Figure 9 The same method of description is used to ensure that the third discharge voltage Vdis3 is the highest and the first discharge voltage Vdis1 is the lowest. The voltage of the first discharge voltage Vdis1 can be higher than the voltage of the ground voltage Gnd.

[0141] According to one embodiment of the present disclosure, a memory device 100 may perform discharge operations sequentially, starting with at least one center word line located at the center portion of the memory cell string and ending with the outermost word line adjacent to the select line relative to the memory cell string. In this case, the magnitude of the discharge voltage applied to the multiple word lines can be set such that the voltage applied to the center word line is the lowest, and the voltage applied to the word line directly adjacent to the select line is the highest.

[0142] Figure 11 This is a flowchart illustrating a discharge operation according to an embodiment of the present disclosure.

[0143] refer to Figure 11 In step S1101, the memory device 100 may apply an operating voltage to a selected word line among a plurality of word lines. The operating voltage may be any one of a programming voltage, a verification voltage, and a read voltage.

[0144] At step S1103, the memory device may apply a pass voltage to an unselected word line among a plurality of word lines. The pass voltage may be any of a programming pass voltage, a verification pass voltage, and a read pass voltage. The pass voltage may be a voltage lower than the operating voltage.

[0145] At step S1105, the memory device 100 may perform a discharge operation, which sequentially reduces the voltage of multiple word lines from at least one center word line located at the center of the memory cell string to the word line located at the outermost portion of the memory cell string and directly adjacent to the select line. In one embodiment, during the discharge operation, the memory device 100 may sequentially apply a ground voltage to at least one center word line located at the center of the memory cell string to the word line located at the outermost portion of the memory cell string and directly adjacent to the select line.

[0146] Figure 12 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0147] refer to Figure 12 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0148] Memory controller 2100 can be coupled to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read, write, erase, and background operations of memory device 2200. Memory controller 2100 can provide an interface between memory device 2200 and a host. Memory controller 2100 can run firmware for controlling memory device 2200. Memory controller 2100 can be used in conjunction with the above references. Figure 1 The memory controller 200 described is implemented in the same manner. The memory device 2200 can be implemented in the same manner as described above. Figure 1 The memory device 100 described is implemented in the same way.

[0149] In one embodiment, the memory controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry.

[0150] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) based on specific communication standards or protocols. In one embodiment, the memory controller 2100 can communicate with external devices via at least one of various communication standards or protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Express (NVMe). In one embodiment, connector 2300 can be defined by at least one of the aforementioned communication standards or protocols.

[0151] In one embodiment, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetoresistive RAM (STT-MRAM).

[0152] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card such as a PC card (PCMCIA), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), or universal flash storage (UFS).

[0153] Figure 13 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0154] refer to Figure 13 The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and can receive power through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0155] According to one embodiment of this disclosure, the SSD controller 3210 can perform the above-mentioned references. Figure 1 The functions of the memory controller 200 are described.

[0156] SSD controller 3210 can control multiple flash memories 3221 to 322n in response to signals received from host 3100. In one embodiment, the signals may be signals based on the interface between host 3100 and SSD 3200. For example, the signals may be signals defined by at least one of a variety of interfaces, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Express (NVMe) interface.

[0157] Auxiliary power supply 3230 can be coupled to host 3100 via power connector 3002. Auxiliary power supply 3230 can be supplied with power from host 3100 and can be charged. When power supply from host 3100 is not successfully implemented, auxiliary power supply 3230 can supply power to SSD 3200. In one embodiment, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located within the motherboard and can provide auxiliary power to SSD 3200.

[0158] Buffer memory 3240 can be used as a buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it can temporarily store metadata (e.g., a mapping table) of flash memories 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0159] Figure 14 This is a block diagram illustrating a user system employing a memory system according to an embodiment of the present disclosure.

[0160] refer to Figure 14 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0161] Application processor 4100 can run components included in user system 4000, operating system (OS), or user programs. In one embodiment, application processor 4100 may include controllers, interfaces, graphics engines, etc., to control components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0162] Memory module 4200 can be used as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile RAM, such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or memory module 4200 may include non-volatile RAM, such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, application processor 4100 and memory module 4200 may be packaged based on a stacked package (POP) and may subsequently be provided as a single semiconductor package.

[0163] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communication such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi communication. In one embodiment, network module 4300 may be included in application processor 4100.

[0164] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send the data stored in storage module 4400 to application processor 4100. In one embodiment, storage module 4400 can be implemented as a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In one embodiment, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive device), such as a memory card of user system 4000 or an external drive device.

[0165] In one embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above. Figure 1 The memory device 100 described above operates in the same manner. The memory module 4400 can operate in the same manner as described above. Figure 1 The storage system described operates in the same manner as the storage system 50.

[0166] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In one embodiment, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and display.

[0167] According to this disclosure, a memory device capable of improving negative boost during word line discharge operation and a method for operating the memory device are provided.

Claims

1. A memory device, comprising: A memory cell string includes multiple memory cells coupled to multiple word lines respectively; The peripheral circuitry is configured to perform operations of applying an operating voltage to selected word lines among the plurality of word lines, and operations of applying a voltage to unselected word lines among the plurality of word lines. as well as An operation controller is configured to control the peripheral circuitry to perform a discharge operation after the operation has been executed. The discharge operation sequentially decreases the voltage of the plurality of word lines, from at least one center word line located at the center of the memory cell string relative to the memory cell string, to the outermost word line located relative to the memory cell string and adjacent to the select line. The threshold voltage of the memory cell among the plurality of memory cells coupled to the word line located at the outermost portion of the memory cell string and adjacent to the select line is higher than the threshold voltage of the memory cell among the plurality of memory cells coupled to the at least one center word line located at the central portion of the memory cell string.

2. The memory device of claim 1, wherein the operation controller is configured to control the peripheral circuitry to apply a ground voltage to the select line during the discharge operation.

3. The memory device of claim 2, wherein the operation controller is configured to control the peripheral circuitry to apply the ground voltage to the plurality of word lines during the discharge operation.

4. The memory device of claim 3, wherein the operation controller is configured to control the peripheral circuitry to apply the ground voltage to the plurality of word lines after a discharge voltage lower than the pass voltage has been applied to the plurality of word lines for a preset time.

5. The memory device of claim 2, wherein the operation controller is configured to control the peripheral circuitry to apply a first discharge voltage to the at least one center word line during the discharge operation, and to apply a second discharge voltage higher than the first discharge voltage to a first word line directly adjacent to the at least one center word line.

6. The memory device of claim 5, wherein the operation controller is configured to control the peripheral circuitry to apply a third discharge voltage, higher than the second discharge voltage, to a second word line that is directly adjacent to the first word line and opposite to the at least one center word line.

7. The memory device of claim 6, wherein the further each of the plurality of word lines is from the at least one center word line, the higher the discharge voltage applied to each of the plurality of word lines.

8. The memory device according to claim 1, wherein: The operating voltage is a sensing voltage lower than the through voltage, and The operation is a sensing operation that identifies the threshold voltage of the selected memory cell coupled to the selected word line.

9. The memory device according to claim 1, wherein: The operating voltage is a programming voltage that is higher than the pass voltage, and The operation is a programming voltage application operation that increases the threshold voltage of the plurality of memory cells.

10. A method of operating a memory device, comprising: An operating voltage is applied to a selected word line among multiple word lines coupled to multiple memory cells included in a string of memory cells; Perform the operation of applying voltage to the unselected word lines among the plurality of word lines; as well as After the operation has been performed, a discharge operation is performed, wherein the voltage of the plurality of word lines is sequentially reduced from at least one center word line located in the center portion relative to the memory cell string, to the outermost word line located in the outermost portion relative to the memory cell string and adjacent to the select line. The threshold voltage of the memory cell among the plurality of memory cells coupled to the word line located at the outermost portion of the memory cell string and adjacent to the select line is higher than the threshold voltage of the memory cell among the plurality of memory cells coupled to the at least one center word line located at the central portion of the memory cell string.

11. The method of claim 10, wherein a ground voltage is applied to the select line during the discharge operation.

12. The method of claim 11, wherein performing the discharge operation comprises: The ground voltage is applied to the multiple word lines.

13. The method of claim 12, wherein performing the discharge operation further comprises: After applying a discharge voltage lower than the pass voltage to the multiple word lines for a preset time, the ground voltage is applied to the multiple word lines.

14. The method of claim 11, wherein performing the discharge operation further comprises: Apply a first discharge voltage to the at least one center word line, and A second discharge voltage higher than the first discharge voltage is applied to the first word line directly adjacent to the at least one center word line.

15. The method of claim 14, wherein performing the discharge operation further comprises: A third discharge voltage higher than the second discharge voltage is applied to a second word line that is directly adjacent to the first word line and opposite to the at least one center word line.

16. The method of claim 15, wherein the further each of the plurality of word lines is from the at least one center word line, the higher the discharge voltage applied to each of the plurality of word lines.

17. The method of claim 10, wherein: The operating voltage is a sensing voltage lower than the through voltage, and The operation is a sensing operation that identifies the threshold voltage of the selected memory cell coupled to the selected word line.

18. The method of claim 10, wherein: The operating voltage is a programming voltage that is higher than the pass voltage, and The operation is a programming voltage application operation that increases the threshold voltage of the plurality of memory cells.

Images