A semiconductor structure and memory

Abstract

The present disclosure provides a semiconductor structure and a memory, the semiconductor structure comprising A anti-fuse arrays and A comparison modules; the A comparison modules are arranged in sequence along a first direction, the A anti-fuse arrays are arranged in sequence along the first direction, and one comparison module and one anti-fuse array are arranged along a second direction; each anti-fuse array stores two damaged row addresses, and each comparison module is used to form two address comparators, and the address comparators are used to compare a target row address with one damaged row address.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to a semiconductor structure and a memory. Background Technology

[0002] Taking Dynamic Random Access Memory (DRAM) chips as an example, they have a redundancy replacement function to repair damaged memory rows using redundant memory rows, thereby improving the lifespan of the memory. However, the circuit structure involved in the redundancy replacement function still has many shortcomings, such as the large number of signal lines and the large overall device area, which limits the improvement of chip performance. Summary of the Invention

[0003] This disclosure provides a semiconductor structure and a memory.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor structure comprising A antifuse arrays and A comparison modules, where A is a positive integer; the A comparison modules are arranged sequentially along a first direction, the A antifuse arrays are arranged sequentially along the first direction, and one comparison module and one antifuse array are arranged along a second direction; each antifuse array stores two corrupted row addresses, and each comparison module is used to form two address comparators, the address comparators being used to compare a target row address with one of the corrupted row addresses.

[0006] In some embodiments, each of the comparison modules is divided into a first device region and a second device region, and the first device region, the second device region and the antifuse array are arranged sequentially along a second direction;

[0007] The first device region includes a first output unit, a first comparison unit, a second output unit, and a second comparison unit arranged sequentially along the second direction;

[0008] The second device region includes a plurality of mirror units arranged along a second direction, and each mirror unit includes one first comparison unit and one second comparison unit, wherein the first comparison unit and the second comparison unit in the same mirror unit are arranged along the second direction, or the second comparison unit and the first comparison unit in the same mirror unit are arranged along the second direction;

[0009] The first output unit and all the first comparison units constitute the first address comparator, and the second output unit and all the second comparison units constitute the second address comparator.

[0010] In some embodiments, each of the first comparison units or each of the second comparison units includes a control module and a latch module, and the control module and the latch module are electrically connected.

[0011] In each of the mirror units, the first comparison unit and the second comparison unit are mirror symmetrical, and the axis of symmetry extends along a first direction. The control module is distributed close to the axis of symmetry, and the latch module is distributed away from the axis of symmetry.

[0012] The latch module receives the system clock signal and one bit of the damaged row address and outputs an intermediate address signal. The control module compares the intermediate address signal and one bit of the target row address based on the comparison enable signal and outputs a comparison result signal.

[0013] In some embodiments, each of the mirror units further includes a first address signal metal line, a first complementary address signal metal line, and a first reset signal metal line, wherein the first address signal metal line, the first complementary address signal metal line, and the first reset signal metal line all extend along a second direction and are located in the same layer.

[0014] Each of the first comparison units further includes a second address signal metal line, a second complementary address signal metal line, and a second reset signal metal line; each of the second comparison units includes a third address signal metal line, a third complementary address signal metal line, and a third reset signal metal line; the second address signal metal line, the second complementary address signal metal line, the second reset signal metal line, the third address signal metal line, the third complementary address signal metal line, and the third reset signal metal line all extend along a first direction and are located on the same layer, and the layer where the second address signal metal line is located is located below the layer where the first address signal metal line is located;

[0015] For the same mirror unit, the second address signal metal line and the third address signal metal line are both electrically connected to the first address signal metal line, the second complementary address signal metal line and the third complementary address signal metal line are both electrically connected to the first complementary address signal metal line, and the second reset signal metal line and the third reset signal metal line are both electrically connected to the first reset signal metal line.

[0016] In this configuration, the first address signal metal line, the second address signal metal line, and the third address signal metal line jointly transmit one bit of the target row address; the first complementary address signal metal line, the second complementary address signal metal line, and the third complementary address signal metal line jointly transmit the inverted signal of one bit of the target row address; and the first reset address signal metal line, the second reset address signal metal line, and the third reset address signal metal line jointly transmit a reset signal, which is used to reset the latch module.

[0017] In some embodiments, the comparison module further includes a first enable signal metal line, a first result signal metal line, and a first result complementary signal metal line, wherein the first enable signal metal line, the first result signal metal line, and the first result complementary signal metal line all extend along a second direction and are located in the same layer.

[0018] Each of the first comparison units further includes a third enable signal metal line, a third result signal metal line, and a third result complementary signal metal line; wherein, the third enable signal metal line, the third result signal metal line, and the third result complementary signal metal line all extend along a first direction and are located in the same layer, and the layer where the third enable signal metal line is located is located in the lower layer where the first enable signal metal line is located.

[0019] In the same comparison module, all third enable signal metal lines are electrically connected to the first enable signal metal line, all third result signal metal lines are electrically connected to the first result signal metal line, and all third result complementary signal metal lines are electrically connected to the first result complementary signal metal line.

[0020] Wherein, the first enable signal metal line and the third enable signal metal line jointly transmit the comparison enable signal of the first address comparator, the first result signal metal line and the third result signal metal line jointly transmit the comparison result signal of the first address comparator, and the first result complementary signal metal line and the third result complementary signal metal line jointly transmit the inverted signal of the comparison result signal of the first address comparator.

[0021] In some embodiments, the comparison module further includes a second enable signal metal line, a second result signal metal line, and a second result complementary signal metal line, wherein the second enable signal metal line, the second result signal metal line, and the second result complementary signal metal line all extend along a second direction and are located on the same layer; each of the second comparison units includes a fourth enable signal metal line, a fourth result signal metal line, and a fourth result complementary signal metal line, wherein the fourth enable signal metal line, the fourth result signal metal line, and the fourth result complementary signal metal line all extend along a first direction and are located on the same layer, and the layer where the fourth enable signal metal line is located is located below the layer where the second enable signal metal line is located;

[0022] In the same comparison module, all fourth enable signal metal lines are electrically connected to the second enable signal metal line, all fourth result signal metal lines are electrically connected to the second enable signal metal line, and all fourth result complementary signal metal lines are electrically connected to the second result complementary signal metal line.

[0023] Wherein, the second enable signal metal line and the fourth enable signal metal line jointly transmit the comparison enable signal of the second address comparator, the second result signal metal line and the fourth result signal metal line jointly transmit the comparison result signal of the second address comparator, and the second result complementary signal metal line and the fourth result complementary signal metal line are used to transmit the inverted signal of the comparison result signal of the second address comparator.

[0024] In some embodiments, for two adjacent mirror units, a first comparison unit in one mirror unit is adjacent to a first comparison unit in the other mirror unit; or, a second comparison unit in one mirror unit is adjacent to a second comparison unit in the other mirror unit.

[0025] In some embodiments, the comparison module further includes a first clock signal metal line, a first complementary clock signal metal line, a second clock signal metal line, and a second complementary clock signal metal line, wherein the first clock signal metal line, the first complementary clock signal metal line, the second clock signal metal line, and the second complementary clock signal metal line all extend along a second direction and are located in the same layer;

[0026] For the first comparison unit, a third clock signal metal line is distributed inside it, and a third complementary clock signal metal line is distributed on the side away from the adjacent second comparison unit; and two adjacent first comparison units along the second direction share the third complementary clock signal metal line; for the second comparison unit, a fourth clock signal metal line is distributed inside it, and a fourth complementary clock signal metal line is distributed on the side away from the adjacent first comparison unit; and two adjacent second comparison units along the second direction share the fourth complementary clock signal metal line.

[0027] In the same comparison module, all third clock signal metal lines are electrically connected to the first clock signal metal line, all third complementary clock signal metal lines are electrically connected to the first complementary clock signal metal line, all fourth clock signal metal lines are electrically connected to the second clock signal metal line, and all fourth complementary clock signal metal lines are electrically connected to the second complementary clock signal metal line.

[0028] The first clock signal metal line, the second clock signal metal line, all third clock signal metal lines, and all fourth clock signal metal lines jointly transmit the system clock signal, and the first complementary clock signal metal line, the second complementary clock signal metal line, all third complementary clock signal metal lines, and all fourth complementary clock signal metal lines jointly transmit the inverted signal of the system clock signal.

[0029] In some embodiments, the semiconductor structure further includes a plurality of power metal lines and a plurality of standard ground metal lines, wherein the power metal lines and the standard ground metal lines extend along a second direction;

[0030] In the first direction, each of the comparison modules has a power supply metal line distributed along one side of the first direction, and each of the comparison modules has a standard ground metal line distributed along the other side of the first direction, and adjacent comparison modules share the power supply metal line or the standard ground metal line.

[0031] In some embodiments, two adjacent comparison modules along a first direction are mirror-symmetrical, and the axis of symmetry extends along a second direction.

[0032] In some embodiments, the first enable signal metal line, the first result signal metal line, and the first result complementary signal metal line are arranged adjacent to each other along a first direction to form a first metal line group.

[0033] The second enable signal metal line, the second result signal metal line, and the second result complementary signal metal line are arranged adjacently along the first direction to form a second metal line group;

[0034] The first clock signal metal line and the first complementary clock signal metal line are arranged adjacently along the first direction to form a third metal line group;

[0035] The second clock signal metal line and the second complementary clock signal metal line are arranged adjacently along the first direction to form a fourth metal line group;

[0036] For one of the mirror units, the first address signal metal line, the standard ground metal line, the first complementary address signal metal line, the first metal line group, the second metal line group, the third metal line group, the fourth metal line group, the first reset signal metal line, and the power supply metal line are arranged sequentially along a first direction; or, the power supply metal line, the first reset signal metal line, the fourth metal line group, the third metal line group, the second metal line group, the first metal line group, the first complementary address signal metal line, the standard ground metal line, and the first address signal metal line are arranged sequentially along a first direction.

[0037] Secondly, embodiments of this disclosure provide a memory, including the semiconductor structure as described in the first aspect.

[0038] This disclosure provides a semiconductor structure and memory that enables the circuit structure associated with redundant replacement functions to be arranged in a regular manner, reducing the number of channels and the layout area. Attached Figure Description

[0039] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0040] Figure 2 A specific schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0041] Figure 3 This is a partial structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0042] Figure 4 This is a schematic diagram of a signal connection of a semiconductor structure provided in an embodiment of the present disclosure;

[0043] Figure 5A This is a schematic diagram of the structure of a mirror unit provided in an embodiment of the present disclosure;

[0044] Figure 5B This is a schematic diagram of another mirror unit provided in an embodiment of the present disclosure;

[0045] Figure 6 A detailed structural schematic diagram of a mirror unit provided in an embodiment of this disclosure;

[0046] Figure 7A detailed structural schematic diagram of another mirror unit provided in an embodiment of this disclosure;

[0047] Figure 8 A schematic diagram of another semiconductor structure provided in an embodiment of this disclosure;

[0048] Figure 9 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0049] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described.

[0050] Static Random-Access Memory (SRAM) semiconductor chips;

[0051] Dynamic Random Access Memory (DRAM) semiconductor chips;

[0052] Synchronous Dynamic Random Access Memory (SDRAM) semiconductor chips;

[0053] Double Data Rate SDRAM (DDR).

[0054] Before introducing the embodiments of this disclosure, three directions for describing the three-dimensional structure that may be used in the plane involved in the following embodiments are defined. Taking a Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis directions (not involved in the embodiments of this disclosure). The semiconductor structure may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the semiconductor structure is defined as the third direction. In the direction of the top and bottom surfaces of the semiconductor structure (i.e., the plane in which the semiconductor structure is located), two intersecting directions are defined: a first direction and a second direction, that is, the planar orientation of the semiconductor structure can be determined based on the first and second directions. In the embodiments of this disclosure, the first and second directions may be perpendicular to each other; in other embodiments, the first and second directions may not be perpendicular.

[0055] In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device package, signal pin array, or component thereof, but are merely idealized representations for describing illustrative embodiments. Therefore, the illustrations are not necessarily to scale.

[0056] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0057] It should be understood that memory (such as DRAM, SRAM, SDRAM, LPDDR, etc.) has a redundancy repair function, which can use redundant rows to repair damaged memory rows (or word lines) to improve the yield of chips. Taking DRAM as an example, before DRAM performs certain operations (such as activation operation, read operation, write operation, etc.) on the selected memory row, it is necessary to compare the target row address (i.e. the input row address) with the address library of the damaged row: (1) If the target row address is different from all the damaged row addresses, it means that the memory row has not been repaired and can be directly operated with the target row address as the final addressing information; (2) If the target row address is the same as a damaged row address, it means that the memory row has been repaired and needs to be repositioned to the redundant row that repaired the memory row for operation.

[0058] To achieve the above functions, in one embodiment of this disclosure, see [link to embodiment]. Figure 1 This illustrates a schematic diagram of a semiconductor structure 10 provided in an embodiment of the present disclosure. For example... Figure 1 As shown, the semiconductor structure 10 includes A antifuse arrays 11 ( Figure 1 (Taking only 1 as an example for numbering) and A comparison modules 12 ( Figure 1 (Taking only 1 as an example for numbering), A is a positive integer; A comparison modules 12 are arranged sequentially along the first direction, A antifuse arrays 11 are arranged sequentially along the first direction, and 1 comparison module 12 and 1 antifuse array 11 are arranged along the second direction.

[0059] Here, each antifuse array 11 stores two corrupted row addresses, and each comparison module 12 is used to form two address comparators, which are used to compare the target row address with a corrupted row address.

[0060] It should be noted that the semiconductor structure 10 provided in this disclosure can be applied to various types of electronic devices, such as DRAM, SDRAM, DDR, DPDDR, etc. In other words, any microelectronic device designed with the aforementioned redundancy replacement function can adopt the semiconductor structure designed in this disclosure.

[0061] exist Figure 1 In the example, the semiconductor structure includes eight comparator modules 12 and eight antifuse arrays 11, but this is only an illustration. In reality, the number of comparator modules 12 / antifuse arrays 11 can be more or less.

[0062] It should be understood that both the damaged row address and the target row address include multi-bit sub-signals. The antifuse array 11 includes multiple antifuse cells, each storing one bit of the damaged row address. For example, if the damaged row address has 15 bits, then the antifuse array 11 includes 30 antifuse cells. Each antifuse cell includes a fuse transistor and a select transistor. If the fuse transistor has not been blown, it is in a high-impedance state and can be considered as not connected; if the fuse transistor has been blown, it is in a low-impedance state and can be considered as connected. The select transistor is used to control whether the signal path between the fuse transistor and other circuits is connected.

[0063] In simple terms, when a memory row is corrupted, it needs to be replaced with an inactive redundant row, and the address of the corrupted row is stored in the antifuse array 11. Here's just one example: if the corrupted row address is a first value (e.g., 1), the fuse transistor in the corresponding antifuse cell is blown; if the corrupted row address is a second value (e.g., 0), the fuse transistor in the corresponding antifuse cell is not blown, thus completing the address storage process. In this way, all corrupted row addresses in the memory are stored in the corresponding antifuse array 11. During memory operation, when the memory receives a target row address, it uses an address comparator to compare the target row address with the corrupted row address. Based on the comparison result, it can be determined whether the target row address has undergone redundancy repair, for subsequent addressing operations.

[0064] like Figure 1As shown, each antifuse array stores two damaged row addresses, and each comparison module includes two address comparators to share some traces (see subsequent descriptions for details), which can reduce the number of signal metal wirings and improve the problem of large area along the first direction. In addition, one antifuse array 11 and one comparison module 12 form a minimum repeating unit. The number of this minimum repeating unit can be set according to the needs of the actual application scenario, which can easily form a regular arrangement and increase layout efficiency.

[0065] In some embodiments, such as Figure 2 As shown, each comparison module 12 is divided into a first device area and a second device area, and the first device area, the second device area and the antifuse array 11 are arranged sequentially along the second direction;

[0066] The first device area includes a first output unit 20A, a first comparison unit 21A_1, a second output unit 20B, and a second comparison unit 21B_1 arranged sequentially along the second direction.

[0067] The second device region includes multiple mirror cells arranged along the second direction (e.g., Figure 2 The mirror units 2 to 15 are provided, and each mirror unit includes one first comparison unit and one second comparison unit; for example, mirror unit 2 includes a first comparison unit 21A_2 and a second comparison unit 21B_2, mirror unit 3 includes a first comparison unit 21A_3 and a second comparison unit 21B_3, etc. The first comparison unit and the second comparison unit in the same mirror unit are arranged along the second direction, or the second comparison unit and the first comparison unit in the same mirror unit are arranged along the second direction; for example, in mirror unit 2, the first comparison unit 21A_2 and the second comparison unit 21B_2 are arranged along the second direction; in mirror unit 3, the second comparison unit 21B_3 and the first comparison unit 21A_3 are arranged along the second direction.

[0068] The first output unit and all the first comparison units constitute the first address comparator, i.e. Figure 2 The first output unit 20A, first comparison unit 21A_1, first comparison unit 21A_2, first comparison unit 21A_3...first comparison unit 21A_15 form the first address comparator; the second output unit and all the second comparison units constitute the second address comparator, i.e. Figure 2 The second output unit 20B, the second comparison unit 21B_1, the second comparison unit 21B_2, ..., the second comparison unit 21B_15 constitute the second address comparator.

[0069] The following example illustrates this: Assume that the target row address and the corrupted row address are each 15 bits long. The target row address is represented as RA<15:1>, and the different corrupted row addresses are represented as EA0<15:1>, EA1<15:1>, and so on.

[0070] Specifically, for the first address comparator, the first comparison unit 21A_1 is used to compare RA <1> and EA0 <1> Compare, if RA <1> and EA0 <1> If they are the same, the output of the first comparison unit 21A_1 is low; if RA <1> and EA0 <1> If they are different, the output of the first comparison unit 21A_1 will be high; similarly, the first comparison unit 21A_2 is used to compare RA. <2> and EA0 <2> The first comparison unit 21A_3 is used to compare RA. <3> and EA0 <3> Comparison... The first comparison unit 21A_15 is used to compare RA <15> and EA0 <15> The comparison is performed. Next, the outputs of all the first comparison units are connected together to output an intermediate comparison signal. If the target row address and the corrupted row address correspond one-to-one, the intermediate comparison signal is low; if the target row address and the corrupted row address differ by at least one bit of a sub-signal, the intermediate comparison signal is high. Finally, the first output unit 20A receives the intermediate comparison signal and the output enable signal, and outputs the intermediate comparison signal as the comparison result when the output enable signal is valid, to indicate whether RA<15:1> and EA0<15:1> are the same.

[0071] Similar to the operation of the first address comparator, the second address comparator can compare whether RA<15:1> and EA1<15:1> are the same, the third address comparator can compare whether RA<15:1> and EA2<15:1> are the same, and so on, thus determining whether the storage row corresponding to the target row address is corrupted.

[0072] In particular, Figure 2 In the comparison module 12, there are a total of 14 mirror units (mirror unit 2 to mirror unit 15), 15 first comparison units (21A_1 to 21A_15) and 15 second comparison units (21B_1 to 21B_15). However, the above numbers are just an example, and there may be more or fewer in actual application scenarios.

[0073] In this embodiment of the disclosure, since the first comparison unit 21A_1 and the first output unit 20A are closer in circuit connection, the first comparison unit 21A_1 is placed in the first device area rather than the second device area; similarly, the second comparison unit 21B_1 is also placed in the first device area rather than the second device area.

[0074] In some embodiments, see Figure 2For two adjacent mirror units, the first comparison unit in one mirror unit is adjacent to the first comparison unit in the other mirror unit, for example, the first comparison unit 21A_2 and the first comparison unit 21A_3 are adjacent; or, the second comparison unit in one mirror unit is adjacent to the second comparison unit in the other mirror unit, for example, the second comparison unit 21B_2 and the second comparison unit 21B_3 are adjacent.

[0075] At the same time, only for Figure 2 The second comparator in the first mirror unit is adjacent to the second comparator in the first device region, and the second comparator in the last mirror unit is adjacent to the antifuse array 11, but this does not constitute a corresponding restriction.

[0076] In this way, the components in two adjacent mirror units are identical, but their positions are mirror images of each other.

[0077] In some embodiments, see Figure 3 Each first comparison unit or each second comparison unit includes a control module 22 and a latch module 21, and the control module 22 and the latch module 21 are electrically connected.

[0078] Please see Figure 4 The latch module 21 receives the system clock signal and one bit of the corrupted row address and outputs the intermediate address signal. The control module 22 is used to compare the intermediate address signal and one bit of the target row address based on the comparison enable signal and outputs the comparison result signal.

[0079] Please see Figure 5A It shows the specific structure of mirror unit 2; please refer to Figure 5B It shows the specific structure of mirror unit 3. Figure 5A and Figure 5B The circuit structures are essentially the same, but Figure 5A The upper part is the first comparison unit, and the lower part is the second comparison unit; conversely, Figure 5B The upper half is the second comparison unit, and the lower half is the first comparison unit. Other mirror units are selected based on their positions. Figure 5A or Figure 5B The structure.

[0080] Specifically, please see Figure 5A or Figure 5B In each mirror unit, the first comparison unit and the second comparison unit are mirror-symmetrical, and the axis of symmetry extends along a first direction; and the control module 22 is distributed close to the axis of symmetry, while the latch module 21 is distributed away from the axis of symmetry. That is, although the first comparison unit and the second comparison unit have the same device composition, their positions are mirror images of each other. Note that in Figure 5A or Figure 5B In the middle, the horizontal direction along the paper is the first direction.

[0081] In this embodiment of the disclosure, every two address comparators together form a comparator module 12. The first comparison unit in the first address comparator and the second comparison unit in the second address comparator are arranged alternately along the second direction so as to share some signal metal lines and save layout area. The following is a detailed description of the arrangement of the signal metal lines.

[0082] In some embodiments, see Figure 6 Each mirror unit further includes a first address signal metal line 30, a first complementary address signal metal line 31, and a first reset signal metal line 32, wherein the first address signal metal line 30, the first complementary address signal metal line 31, and the first reset signal metal line 32 all extend along the second direction and are located on the same layer.

[0083] Please see Figure 6 Each first comparison unit further includes a second address signal metal line 40a, a second complementary address signal metal line 41a, and a second reset signal metal line 42a. Each second comparison unit includes a third address signal metal line 40b, a third complementary address signal metal line 41b, and a third reset signal metal line 42b. The second address signal metal line 40a, the second complementary address signal metal line 41a, the second reset signal metal line 42a, the third address signal metal line 40b, the third complementary address signal metal line 41b, and the third reset signal metal line 42b all extend along a first direction and are located in the same layer. The layer containing the second address signal metal line 40a is located below the layer containing the first address signal metal line 30. Here, "below" refers to a direction closer to the semiconductor substrate.

[0084] Please see Figure 6 For the same mirror unit, the second address signal metal line 40a and the third address signal metal line 40b are both electrically connected to the first address signal metal line 30, the second complementary address signal metal line 41a and the third complementary address signal metal line 41b are both electrically connected to the first complementary address signal metal line 31, and the second reset signal metal line 42a and the third reset signal metal line 42b are both electrically connected to the first reset signal metal line 32. Here, the electrical connections can be achieved through the contact structure shown in the figure.

[0085] It should be noted that the first address signal metal line 30, the second address signal metal line 40a, and the third address signal metal line 40b jointly transmit one bit of the target row address; the first complementary address signal metal line 31, the second complementary address signal metal line 41a, and the third complementary address signal metal line 41b jointly transmit the inverted signal of one bit of the target row address; and the first reset signal metal line 32, the second reset signal metal line 42a, and the third reset signal metal line 42b jointly transmit the reset signal, which is used to reset the latch module.

[0086] Here, taking the target row address (represented as RA<15:1>) and the corrupted row address (represented as EA<15:1>) each comprising 15 sub-signals as an example, each comparison module 12 includes 15 first comparison units and 15 second comparison units. The 14 first comparison units and 14 second comparison units together constitute 14 mirror units. For different mirror units, the target row address transmitted by the first address signal is different. For example, in mirror unit 2, the first address signal metal line 30, the second address signal metal line 40a, and the third address signal metal line 40b transmit RA. <2> In mirror unit 2, the first complementary address signal metal line 31, the second complementary address signal metal line 41a, and the third complementary address signal metal line 41b transmit RAB. <2> In mirror unit 2, the first reset signal metal line 32, the second reset signal metal line 42a, and the third reset signal metal line 42b transmit the reset signal RST; in mirror unit 3, the first address signal metal line 30 transmits RA. <3> The transmission RAB of the first complementary address signal metal line 31 in mirror unit 3 <3> In mirror unit 3, the first reset signal metal line 32 transmits the reset signal RST...

[0087] Meanwhile, the first comparison unit and the second comparison unit in the same mirror unit share the first address signal metal line 30, the first complementary address signal metal line 31 and the first reset signal metal line 32, which improves the utilization efficiency of the signal metal lines and reduces the layout area.

[0088] In some embodiments, see Figure 6 The comparison module 12 also includes a first enable signal metal line 33, a first result signal metal line 34, and a first result complementary signal metal line 35, and the first enable signal metal line 33, the first result signal metal line 34, and the first result complementary signal metal line 35 all extend along the second direction and are located in the same layer.

[0089] Please see Figure 6Each first comparison unit further includes a third enable signal metal line 43, a third result signal metal line 44, and a third result complementary signal metal line 45; wherein the third enable signal metal line 43, the third result signal metal line 44, and the third result complementary signal metal line 45 all extend along the first direction and are located in the same layer, and the layer where the third enable signal metal line 43 is located is located in the lower layer of the layer where the first enable signal metal line 33 is located.

[0090] Please see Figure 6 In the same comparison module 12, all third enable signal metal lines 43 are electrically connected to the first enable signal metal line 33, all third result signal metal lines 44 are electrically connected to the first result signal metal line 34, and all third result complementary signal metal lines 45 are electrically connected to the first result complementary signal metal line 35. That is, all first comparison units in the same comparison module 12 share the first enable signal metal line 33, the first result signal metal line 34, and the first result complementary signal metal line 35. Here, the electrical connection can be achieved through the contact structure shown in the figure.

[0091] It should be noted that the first enable signal metal line 33 and the third enable signal metal line 43 jointly transmit the comparison enable signal of the first address comparator, the first result signal metal line 34 and the third result signal metal line 44 are used to transmit the comparison result signal of the first address comparator, and the first result complementary signal metal line 35 and the third result complementary signal metal line 45 are used to transmit the inverted signal of the comparison result signal of the first address comparator.

[0092] In some embodiments, see Figure 6 The comparison module 12 further includes a second enable signal metal line 36, a second result signal metal line 37, and a second result complementary signal metal line 38. All three lines extend along a second direction and are located on the same layer. Each second comparison unit includes a fourth enable signal metal line 46, a fourth result signal metal line 47, and a fourth result complementary signal metal line 48. These lines extend along a first direction and are located on the same layer. The layer containing the fourth enable signal metal line 46 is located below the layer containing the second enable signal metal line 36.

[0093] Please see Figure 6Within the same comparison module 12, all fourth enable signal metal lines 46 are electrically connected to the second enable signal metal line 36, all fourth result signal metal lines 47 are electrically connected to the second enable signal metal line 36, and all fourth result complementary signal metal lines 48 are electrically connected to the second result complementary signal metal line 38. Simultaneously, the fourth enable signal metal lines 46, fourth result signal metal lines 47, and fourth result complementary signal metal lines 48 are all connected to their respective control modules 22. Here, the electrical connections can be achieved through the contact structure shown in the figure.

[0094] In other words, all the second comparison units in the same comparison module 12 share the second enable signal metal line 36, the second result signal metal line 37, and the second result complementary signal metal line 38.

[0095] Among them, the second enable signal metal line 36 and the fourth enable signal metal line 46 jointly transmit the comparison enable signal of the second address comparator, the second result signal metal line 37 and the fourth result signal metal line 47 jointly transmit the comparison result signal of the second address comparator, and the second result complementary signal metal line 38 and the fourth result complementary signal metal line 48 are used to transmit the inverted signal of the comparison result signal of the second address comparator.

[0096] In some embodiments, see Figure 6 The comparison module 12 also includes a first clock signal metal line 50, a first complementary clock signal metal line 51, a second clock signal metal line 52, and a second complementary clock signal metal line 53. The first clock signal metal line 50, the first complementary clock signal metal line 51, the second clock signal metal line 52, and the second complementary clock signal metal line 53 all extend along the second direction and are located on the same layer.

[0097] For the first comparison unit, a third clock signal metal line 60 is distributed inside it, and a third complementary clock signal metal line 61 is distributed on the side away from the adjacent second comparison unit; and two adjacent first comparison units along the second direction share the third complementary clock signal metal line 61. For the second comparison unit, a fourth clock signal metal line 62 is distributed inside it, and a fourth complementary clock signal metal line 63 is distributed on the side away from the adjacent first comparison unit; and two adjacent second comparison units along the second direction share the fourth complementary clock signal metal line 63.

[0098] In the same comparison module 12, all third clock signal metal lines 60 are electrically connected to the first clock signal metal line 50, all third complementary clock signal metal lines 61 are electrically connected to the first complementary clock signal metal line 51, all fourth clock signal metal lines 62 are electrically connected to the second clock signal metal line 52, and all fourth complementary clock signal metal lines 63 are electrically connected to the second complementary clock signal metal line 53; here, the electrical connection can be achieved through the contact structure shown in the figure.

[0099] The system clock signal is transmitted via the first clock signal metal line 50, the second clock signal metal line 52, the third clock signal metal line 60, and the fourth clock signal metal line 62. The system clock signal is transmitted via the first complementary clock signal metal line 51, the second complementary clock signal metal line 53, the third complementary clock signal metal line 61, and the fourth complementary clock signal metal line 63. In simpler terms, all first comparison units can share the first clock signal metal line 50 and the first complementary clock signal metal line 51, and all second comparison units can share the second clock signal metal line 52 and the second complementary clock signal metal line 53.

[0100] It should be noted that, please refer to... Figure 2 Since two adjacent mirror units are mirror images of each other, meaning the first comparison unit of one mirror unit is located outside the first comparison unit of another mirror unit, there is a third complementary clock signal metal line 61 and the first comparison unit of another mirror unit on the side of the first comparison unit away from the second comparison unit (within the same mirror unit). Therefore, these two first comparison units can share the third complementary clock signal metal line 61. Similarly, on the side of the second comparison unit away from the first comparison unit (within the same mirror unit), there is a fourth complementary clock signal metal line 63 and the second comparison unit of another mirror unit. Therefore, these two second comparison units can share the fourth complementary clock signal metal line 63, thus saving the number of metal lines and traces.

[0101] In some embodiments, see Figure 6 The semiconductor structure 10 also includes a plurality of power metal lines 54 and a plurality of standard ground metal lines 55, and both the power metal lines 54 and the standard ground metal lines 55 extend along a second direction.

[0102] Please see Figure 8 In the first direction, each comparison module 12 has a power supply metal line 54 distributed along one side of the first direction, and each comparison module 12 has a standard ground metal line 55 distributed along the other side of the first direction, and adjacent comparison modules 12 share the power supply metal line 54 or the standard ground metal line 55.

[0103] In some embodiments, two adjacent comparison modules 12 are mirror-symmetrical along a first direction, and the axis of symmetry extends along a second direction.

[0104] That is, for two adjacent comparison modules 12 along the first direction, the mirror unit 2 in one comparison module 12 is as follows: Figure 6 As shown, the mirror unit 2 in another comparison module 12 is as follows: Figure 7 As shown, the two adjacent comparison modules 12 along the first direction are also mirror images of each other, so they can share the power supply metal line 54 or the standard ground metal line 55 between them.

[0105] It should be noted that the first address signal metal line 30, the first complementary address signal metal line 31, the first reset signal metal line 32, the first enable signal metal line 33, the first result signal metal line 34, the first result complementary signal metal line 35, the second enable signal metal line 36, the second result signal metal line 37, the second result complementary signal metal line 38, the first clock signal metal line 50, the first complementary clock signal metal line 51, the second clock signal metal line 52, the second complementary clock signal metal line 53, the power supply metal line 54, and the standard ground metal line 55 are all located in the first metal layer.

[0106] The second address signal metal line 40a, the second complementary address signal metal line 41a, the second reset signal metal line 42a, the third address signal metal line 40b, the third complementary address signal metal line 41b, the third reset signal metal line 42b, the third enable signal metal line 43, the third result signal metal line 44, the third result complementary signal metal line 45, the fourth enable signal metal line 46, the fourth result signal metal line 47, the fourth result complementary signal metal line 48, the third clock signal metal line 60, the third complementary clock signal metal line 61, the fourth clock signal metal line 62, and the fourth complementary clock signal metal line 63 are all located in the second metal layer, and the second metal layer is located below the first metal layer. Here, the electrical connection between the first metal layer and the second metal layer can be achieved through the contact structure shown in the figure.

[0107] In some embodiments, the first enable signal metal line 33, the first result signal metal line 34, and the first result complementary signal metal line 35 are arranged adjacently along the first direction to form a first metal line group; the second enable signal metal line 36, the second result signal metal line 37, and the second result complementary signal metal line 38 are arranged adjacently along the first direction to form a second metal line group; the first clock signal metal line 50 and the first complementary clock signal metal line 51 are arranged adjacently along the first direction to form a third metal line group; and the second clock signal metal line 52 and the second complementary clock signal metal line 53 are arranged adjacently along the first direction to form a fourth metal line group.

[0108] For a mirror unit, please refer to Figure 6 The first address signal metal line 30, the standard ground metal line 55, the first complementary address signal metal line 31, the first metal line group, the second metal line group, the third metal line group, the fourth metal line group, the first reset signal metal line 32, and the power supply metal line 54 are arranged sequentially along the first direction; or, please refer to [link to relevant documentation]. Figure 7 The power supply metal line 54, the first reset signal metal line 32, the fourth metal line group, the third metal line group, the second metal line group, the first metal line group, the first complementary address signal metal line 31, the standard ground metal line 55, and the first address signal metal line 30 are arranged sequentially along the first direction.

[0109] In summary, the present disclosure provides a semiconductor structure 10 for implementing a redundancy replacement function. By using this structure, trace waste can be reduced, the problem of excessive lateral area of ​​the circuit can be improved, and the above circuit structure (comparator module + antifuse array) can be made into an array-like structure, thereby improving the efficiency of layout fabrication.

[0110] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 9 This illustrates a schematic diagram of the composition structure of a memory 70 provided in an embodiment of this disclosure. For example... Figure 9 As shown, the memory 70 includes at least the aforementioned semiconductor structure 10.

[0111] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes A antifuse arrays and A comparator modules, where A is a positive integer; A comparison modules are arranged sequentially along the first direction, A antifuse arrays are arranged sequentially along the first direction, and 1 comparison module and 1 antifuse array are arranged along the second direction; Each of the antifuse arrays stores two corrupted row addresses, and each of the comparison modules is used to form two address comparators, which are used to compare a target row address with one of the corrupted row addresses.

2. The semiconductor structure according to claim 1, characterized in that, Each of the comparison modules is divided into a first device area and a second device area, and the first device area, the second device area and the antifuse array are arranged sequentially along a second direction; The first device region includes a first output unit, a first comparison unit, a second output unit, and a second comparison unit arranged sequentially along the second direction; The second device region includes a plurality of mirror units arranged along a second direction, and each mirror unit includes one first comparison unit and one second comparison unit, wherein the first comparison unit and the second comparison unit in the same mirror unit are arranged along the second direction, or the second comparison unit and the first comparison unit in the same mirror unit are arranged along the second direction; The first output unit and all the first comparison units constitute the first address comparator, and the second output unit and all the second comparison units constitute the second address comparator.

3. The semiconductor structure according to claim 2, characterized in that, Each of the first comparison units or each of the second comparison units includes a control module and a latch module, and the control module and the latch module are electrically connected. In each of the mirror units, the first comparison unit and the second comparison unit are mirror symmetrical, and the axis of symmetry extends along a first direction. The control module is distributed close to the axis of symmetry, and the latch module is distributed away from the axis of symmetry. The latch module receives the system clock signal and one bit of the damaged row address and outputs an intermediate address signal. The control module compares the intermediate address signal and one bit of the target row address based on the comparison enable signal and outputs a comparison result signal.

4. The semiconductor structure according to claim 3, characterized in that, Each of the aforementioned mirror units further includes a first address signal metal line, a first complementary address signal metal line, and a first reset signal metal line, wherein the first address signal metal line, the first complementary address signal metal line, and the first reset signal metal line all extend along the second direction and are located in the same layer; Each of the first comparison units further includes a second address signal metal line, a second complementary address signal metal line, and a second reset signal metal line; each of the second comparison units includes a third address signal metal line, a third complementary address signal metal line, and a third reset signal metal line; the second address signal metal line, the second complementary address signal metal line, the second reset signal metal line, the third address signal metal line, the third complementary address signal metal line, and the third reset signal metal line all extend along a first direction and are located on the same layer, and the layer where the second address signal metal line is located is located below the layer where the first address signal metal line is located; For the same mirror unit, the second address signal metal line and the third address signal metal line are both electrically connected to the first address signal metal line, the second complementary address signal metal line and the third complementary address signal metal line are both electrically connected to the first complementary address signal metal line, and the second reset signal metal line and the third reset signal metal line are both electrically connected to the first reset signal metal line. The first address signal metal line, the second address signal metal line, and the third address signal metal line jointly transmit one bit of the target row address; the first complementary address signal metal line, the second complementary address signal metal line, and the third complementary address signal metal line jointly transmit the inverted signal of one bit of the target row address; and the first reset signal metal line, the second reset signal metal line, and the third reset signal metal line jointly transmit a reset signal, which is used to reset the latch module.

5. The semiconductor structure according to claim 4, characterized in that, The comparison module further includes a first enable signal metal line, a first result signal metal line, and a first result complementary signal metal line, wherein the first enable signal metal line, the first result signal metal line, and the first result complementary signal metal line all extend along the second direction and are located in the same layer. Each of the first comparison units further includes a third enable signal metal line, a third result signal metal line, and a third result complementary signal metal line; wherein, the third enable signal metal line, the third result signal metal line, and the third result complementary signal metal line all extend along a first direction and are located in the same layer, and the layer where the third enable signal metal line is located is located in the lower layer where the first enable signal metal line is located. In the same comparison module, all third enable signal metal lines are electrically connected to the first enable signal metal line, all third result signal metal lines are electrically connected to the first result signal metal line, and all third result complementary signal metal lines are electrically connected to the first result complementary signal metal line. Wherein, the first enable signal metal line and the third enable signal metal line jointly transmit the comparison enable signal of the first address comparator, the first result signal metal line and the third result signal metal line jointly transmit the comparison result signal of the first address comparator, and the first result complementary signal metal line and the third result complementary signal metal line jointly transmit the inverted signal of the comparison result signal of the first address comparator.

6. The semiconductor structure according to claim 5, characterized in that, The comparison module further includes a second enable signal metal line, a second result signal metal line, and a second result complementary signal metal line, wherein the second enable signal metal line, the second result signal metal line, and the second result complementary signal metal line all extend along the second direction and are located in the same layer; Each of the second comparison units includes a fourth enable signal metal line, a fourth result signal metal line, and a fourth result complementary signal metal line. The fourth enable signal metal line, the fourth result signal metal line, and the fourth result complementary signal metal line all extend along a first direction and are located in the same layer. The layer where the fourth enable signal metal line is located is located below the layer where the second enable signal metal line is located. In the same comparison module, all fourth enable signal metal lines are electrically connected to the second enable signal metal line, all fourth result signal metal lines are electrically connected to the second enable signal metal line, and all fourth result complementary signal metal lines are electrically connected to the second result complementary signal metal line. Wherein, the second enable signal metal line and the fourth enable signal metal line jointly transmit the comparison enable signal of the second address comparator, the second result signal metal line and the fourth result signal metal line jointly transmit the comparison result signal of the second address comparator, and the second result complementary signal metal line and the fourth result complementary signal metal line are used to transmit the inverted signal of the comparison result signal of the second address comparator.

7. The semiconductor structure according to claim 6, characterized in that, For two adjacent mirror units, the first comparison unit in one mirror unit is adjacent to the first comparison unit in the other mirror unit; or, the second comparison unit in one mirror unit is adjacent to the second comparison unit in the other mirror unit.

8. The semiconductor structure according to claim 7, characterized in that, The comparison module further includes a first clock signal metal line, a first complementary clock signal metal line, a second clock signal metal line, and a second complementary clock signal metal line. The first clock signal metal line, the first complementary clock signal metal line, the second clock signal metal line, and the second complementary clock signal metal line all extend along the second direction and are located in the same layer. For the first comparison unit, a third clock signal metal line is distributed inside it, and a third complementary clock signal metal line is distributed on the side of it away from the adjacent second comparison unit. Furthermore, two adjacent first comparison units along the second direction share the third complementary clock signal metal line; for each second comparison unit, a fourth clock signal metal line is distributed inside, and a fourth complementary clock signal metal line is distributed on the side away from the adjacent first comparison unit; and two adjacent second comparison units along the second direction share the fourth complementary clock signal metal line. In the same comparison module, all third clock signal metal lines are electrically connected to the first clock signal metal line, all third complementary clock signal metal lines are electrically connected to the first complementary clock signal metal line, all fourth clock signal metal lines are electrically connected to the second clock signal metal line, and all fourth complementary clock signal metal lines are electrically connected to the second complementary clock signal metal line. The first clock signal metal line, the second clock signal metal line, all third clock signal metal lines, and all fourth clock signal metal lines jointly transmit the system clock signal, and the first complementary clock signal metal line, the second complementary clock signal metal line, all third complementary clock signal metal lines, and all fourth complementary clock signal metal lines jointly transmit the inverted signal of the system clock signal.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes a plurality of power metal lines and a plurality of standard ground metal lines, and the power metal lines and the standard ground metal lines extend along a second direction; In the first direction, each of the comparison modules has a power supply metal line distributed along one side of the first direction, and each of the comparison modules has a standard ground metal line distributed along the other side of the first direction, and adjacent comparison modules share the power supply metal line or the standard ground metal line.

10. The semiconductor structure according to claim 9, characterized in that, The two adjacent comparison modules along the first direction are mirror-symmetric, and the axis of symmetry extends along the second direction.

11. The semiconductor structure according to claim 10, characterized in that, The first enable signal metal line, the first result signal metal line, and the first result complementary signal metal line are arranged adjacently along the first direction to form a first metal line group. The second enable signal metal line, the second result signal metal line, and the second result complementary signal metal line are arranged adjacently along the first direction to form a second metal line group; The first clock signal metal line and the first complementary clock signal metal line are arranged adjacently along the first direction to form a third metal line group; The second clock signal metal line and the second complementary clock signal metal line are arranged adjacently along the first direction to form a fourth metal line group; For one of the mirror units, the first address signal metal line, the standard ground metal line, the first complementary address signal metal line, the first metal line group, the second metal line group, the third metal line group, the fourth metal line group, the first reset signal metal line, and the power supply metal line are arranged sequentially along a first direction; or, the power supply metal line, the first reset signal metal line, the fourth metal line group, the third metal line group, the second metal line group, the first metal line group, the first complementary address signal metal line, the standard ground metal line, and the first address signal metal line are arranged sequentially along a first direction.

12. A memory, characterized in that, The memory includes a semiconductor structure as described in any one of claims 1-11.

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