A method for processing a resistive structure

Abstract

This invention discloses a method for processing a resistor structure, comprising the following steps: forming a first insulating layer on the upper surface of a resistor layer; forming a plurality of electrode regions in the first insulating layer, the plurality of electrode regions being arranged along the length direction of the first insulating layer; forming a limiting layer on the upper surface of the first insulating layer; forming an electrode layer in the electrode regions, the two sides of the electrode layer being connected to the adjacent first insulating layer, and the upper surface of the electrode layer being in contact with the limiting layer; and removing the limiting layer to obtain the finished resistor structure. The technical solution of this invention utilizes the limiting layer to form a flat surface on the upper surface of the electrode layer, precisely controlling the shape of the upper surface of the electrode layer in the resistor structure, avoiding the formation of a convex structure in the electrode layer, and improving the production quality of the resistor structure; at the same time, it avoids the top of the electrode layer extending into the first insulating layer, improving the production stability of the resistance value of the resistor structure.

Description

Technical Field

[0001] This invention relates to the field of electronic component processing technology, and in particular to a method for processing a resistor structure. Background Technology

[0002] With the development of technology, the requirements for the precision of high-precision electronic equipment production are becoming increasingly stringent. Existing resistor structures generally include a substrate, a resistive layer, electrodes, and an insulating layer. The resistive layer is set on the substrate, the electrodes are located on both sides of the resistive layer, and the insulating layer covers the resistive layer. During processing, the electrodes can easily spread into the insulating layer, thus affecting the resistance value of the resistor structure. Furthermore, during electrode electroplating, protrusions may form on the upper surface of the electrodes, which in severe cases can cause the electrodes to be plated onto the insulating layer, thereby affecting the resistance value of the resistor structure. Electrode spread and electrode shape are difficult to precisely control with existing technologies, resulting in poor resistance stability of the produced resistor structures. Summary of the Invention

[0003] The main objective of this invention is to propose a method for processing resistor structures, which aims to solve the problem of poor resistance stability in currently produced resistor structures.

[0004] To achieve the above objectives, the present invention proposes a method for processing a resistor structure, comprising the following steps:

[0005] A first insulating layer is formed on the upper surface of the resistive layer;

[0006] A plurality of electrode regions are formed in a first insulating layer, and the plurality of electrode regions are arranged along the length direction of the first insulating layer;

[0007] A limiting layer is formed on the upper surface of the first insulating layer;

[0008] An electrode layer is formed in the electrode region, the two sides of the electrode layer are connected to the adjacent first insulating layer, and the upper surface of the electrode layer is in contact with the limiting layer.

[0009] The resistor structure is obtained by removing the limiting layer.

[0010] Optionally, the step of forming a plurality of electrode regions in the first insulating layer, wherein the plurality of electrode regions are arranged along the length direction of the first insulating layer; and forming a limiting layer on the upper surface of the first insulating layer, includes the following steps:

[0011] The setting area of ​​the plurality of electrode regions is defined by exposing the first insulating layer;

[0012] After forming a limiting layer on the upper surface of the first insulating layer, the unexposed areas of the first insulating layer are removed by development to form the plurality of electrode areas.

[0013] Optionally, the step of forming a first insulating layer on the upper surface of the resistive layer includes the following steps:

[0014] The thickness of the first insulating layer ranges from 10µm to 200µm.

[0015] Optionally, the step of forming a limiting layer on the upper surface of the first insulating layer includes the following steps:

[0016] A plurality of limiting layers are formed on the upper surface of the insulating layer, the number of the limiting layers being equal to the number of the electrode regions; the limiting layers are located above the electrode regions.

[0017] The first insulating layer is divided into several first insulating blocks by the several electrode regions, and the two ends of the limiting layer are respectively connected to the adjacent first insulating blocks.

[0018] Optionally, the step of forming a plurality of electrode regions in the first insulating layer, wherein the plurality of electrode regions are arranged along the length direction of the first insulating layer; and forming a limiting layer on the upper surface of the first insulating layer, includes the following steps:

[0019] The setting area of ​​the plurality of electrode regions is defined by exposing the first insulating layer;

[0020] The unexposed areas of the first insulating layer are removed by development to form the plurality of electrode areas;

[0021] A second insulating layer is formed above the first insulating layer and within the plurality of electrode regions;

[0022] By exposing the area of ​​the second insulating layer other than the aforementioned electrode regions;

[0023] The exposed area of ​​the second insulating layer is removed by development, and the remaining part forms a plurality of second insulating pillars, which protrude from the first insulating layer;

[0024] The limiting layer is formed on the upper part of the second insulating pillar, and the limiting layer is connected to the first insulating layer.

[0025] Optionally, the step of forming a limiting layer covering the second insulating post, wherein the limiting layer is connected to the first insulating layer, includes the following steps:

[0026] The first insulating layer is divided into several first insulating blocks by the several electrode regions; the limiting layer covers the upper part of the second insulating pillar, and the two ends of the limiting layer are connected to the top of the adjacent first insulating block.

[0027] Optionally, the step of forming a second insulating layer over the first insulating layer and in the plurality of electrode regions includes the following steps:

[0028] A third insulating layer is formed on the outer surface of the first insulating block;

[0029] A second insulating layer is formed above the third insulating layer and within the plurality of electrode regions; and / or,

[0030] The thickness of the first insulating layer ranges from 10µm to 100µm;

[0031] The thickness of the portion of the second insulating layer located on the upper surface of the first insulating layer ranges from 10 μm to 100 μm.

[0032] Optionally, the step of forming a second insulating layer above the first insulating layer and in the plurality of electrode regions, wherein the first insulating layer and the second insulating layer are made of different insulating materials, further includes the following steps:

[0033] The first insulating layer includes a solder resist ink layer, and the second insulating layer includes a positive photoresist layer; and / or,

[0034] The first insulating layer includes a solder resist ink layer, and the second insulating layer includes a positive photoresist layer or a negative photoresist layer.

[0035] Optionally, the step of forming a limiting layer on the upper surface of the first insulating layer includes the following steps:

[0036] The thickness of the limiting layer ranges from 0.1 μm to 20 μm; and / or,

[0037] The limiting layer includes a silicon dioxide layer.

[0038] Optionally, the step of forming an electrode layer in the electrode region, wherein both sides of the electrode layer are connected to the adjacent first insulating layer, and the upper surface of the electrode layer is in contact with the limiting layer, further includes the following steps:

[0039] Electrodes are formed in the electrode area through electroplating.

[0040] The technical solution of this invention involves forming a first insulating layer on the upper surface of a resistive layer; subsequently forming a plurality of electrode regions within the first insulating layer, with the electrode regions arranged along the length of the first insulating layer; then forming a limiting layer on the upper surface of the first insulating layer; subsequently forming an electrode layer within the electrode regions, with both sides of the electrode layer connected to adjacent first insulating layers, and the upper surface of the electrode layer in contact with the limiting layer; finally removing the limiting layer to obtain the finished resistive structure. By utilizing the limiting layer, a flat surface is formed on the upper surface of the electrode layer, precisely controlling the shape of the upper surface of the electrode layer in the resistive structure, avoiding the formation of a convex structure in the electrode layer, and improving the production quality of the resistive structure; at the same time, it avoids the top of the electrode layer from extending into the first insulating layer, improving the production stability of the resistance value of the resistive structure. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0042] Figure 1 This diagram illustrates the processing steps of an embodiment of the method for processing the resistor structure of the present invention.

[0043] Figure 2 This is a schematic diagram of the processing steps of an embodiment of the processing method for the resistor structure of the present invention.

[0044] Figure 3 This is a schematic diagram of the processing steps for another embodiment of the processing method for the resistive structure of the present invention.

[0045] Figure 4 This is a schematic diagram of the processing steps for another embodiment of the processing method for the resistor structure of the present invention.

[0046] Explanation of icon numbers:

[0047] 1 resistive layer 2 First insulating layer 21 First insulating block 3 Electrode region 4 High-rise buildings are limited 5 Electrode layer 6 Second insulating layer 61 Second insulating post

[0048] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0050] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0051] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0052] This invention proposes a method for fabricating a resistor structure.

[0053] Example 1

[0054] Reference Figures 1 to 2 In one embodiment of the present invention, the method for processing the resistor structure includes the following steps:

[0055] A first insulating layer 2 is formed on the upper surface of the resistive layer 1;

[0056] A plurality of electrode regions 3 are formed in the first insulating layer 2, and the plurality of electrode regions 3 are arranged along the length direction of the first insulating layer 2.

[0057] A limiting layer 4 is formed on the upper surface of the first insulating layer 2;

[0058] An electrode layer 5 is formed in the electrode region 3. The two sides of the electrode layer 5 are connected to the adjacent first insulating layer 2, and the upper surface of the electrode layer 5 is in contact with the limiting layer 4.

[0059] The resistor structure is obtained by removing the limiting layer 4.

[0060] During the formation of electrode layer 5, the height is increased by electroplating. The processing method of this resistor structure uses the limiting layer 4 to make the upper surface of electrode layer 5 flat, precisely control the shape of the upper surface of electrode layer 5 in resistor structure, avoid the electrode layer 5 from producing a convex structure, and improve the production quality of resistor structure. At the same time, it avoids the electrode layer 5 from spreading to the top of the first insulating layer 2, and improves the production stability of the resistance value of resistor structure.

[0061] Optionally, a plurality of electrode regions 3 are formed in the first insulating layer 2, and the plurality of electrode regions 3 are arranged along the length direction of the first insulating layer 2; the step of forming a limiting layer 4 on the upper surface of the first insulating layer 2 includes the following steps:

[0062] The setting area of ​​several electrode regions 3 is defined by exposing the first insulating layer 2;

[0063] After forming a limiting layer 4 on the upper surface of the first insulating layer 2, the unexposed areas of the first insulating layer 2 are removed by development to form several electrode areas 3.

[0064] Based on the preset positions of several electrode regions 3, the setting area of ​​several electrode regions 3 is defined by exposure imaging. Then, a limiting layer 4 is formed on the upper surface of the first insulating layer 2, so that the lower surface of the limiting layer 4 forms a flat plane. After the limiting layer 4 is formed, the unexposed area of ​​the first insulating layer 2 is removed by developing process, and the removed part forms several electrode regions 3. That is, the first insulating layer 2 is divided by several electrode regions 3 to form several first insulating blocks 21, and two adjacent first insulating blocks 21 and the limiting layer 4 form an electrode region 3.

[0065] Optionally, the step of forming the first insulating layer 2 on the upper surface of the resistive layer 1 includes the following steps:

[0066] The thickness of the first insulating layer 2 ranges from 10um to 200um.

[0067] The first insulating layer 2 includes a solder resist ink layer, which is formed by coating the resist ink onto the upper surface of the resistive layer 1 and then drying and curing it with an ultraviolet dryer or by heating and drying. By controlling the thickness of the first insulating layer 2, it is possible to avoid the insulation failure caused by the first insulating layer 2 being too thin, and it is also possible to avoid the curing time being too long due to the first insulating layer 2 being too thick, as well as the loss of raw materials caused by the first insulating layer 2 being too thick.

[0068] Optionally, the step of forming the limiting layer 4 on the upper surface of the first insulating layer 2 includes the following steps:

[0069] A plurality of limiting layers 4 are formed on the upper surface of the insulating layer, the number of limiting layers 4 being equal to the number of electrode regions 3; the limiting layers 4 are located above the electrode regions 3.

[0070] The first insulating layer 2 is divided into several electrode regions 3 to form several first insulating blocks 21, and the two ends of the limiting layer 4 are respectively connected to the adjacent first insulating blocks 21.

[0071] The number of electrodes to be formed is equal to the number of limiting layers 4. Forming several limiting layers 4 is easier to remove later than forming only one support layer. In addition, the limiting layers 4 have the function of restricting the shape of the upper surface of the electrode layer 5.

[0072] Optionally, the step of forming the limiting layer 4 on the upper surface of the first insulating layer 2 includes the following steps:

[0073] The thickness of the confined layer 4 ranges from 0.1 μm to 20 μm; the confined layer 4 includes a silicon dioxide layer.

[0074] Since the limiting layer 4 is used to restrict the height and shape of the upper surface of the electrode layer 5, it does not require high strength. Furthermore, due to the high hardness of silicon dioxide, the thickness of the limiting layer 4 is controlled within the range of 0.1µm to 20µm. This satisfies the function of the limiting layer 4 in restricting the height and shape of the upper surface of the electrode layer 5 while also reducing raw material consumption. Simultaneously, silicon dioxide also possesses high stability and strong corrosion resistance, ensuring that the limiting layer 4 remains stable and undamaged during electrode formation.

[0075] Optionally, the step of forming an electrode layer 5 within the electrode region 3, with both sides of the electrode layer 5 connected to the adjacent first insulating layer 2, and the upper surface of the electrode layer 5 in contact with the limiting layer 4, further includes the following steps:

[0076] Electrodes are formed in electrode region 3 by electroplating.

[0077] Electroplating can quickly form the electrode layer 5, and the electroplated electrode layer 5 formed by electroplating has the advantages of high surface quality and strong corrosion resistance.

[0078] Example 2

[0079] Reference Figure 1 , Figure 3 Compared with Embodiment 1, the difference in this embodiment is that a plurality of electrode regions 3 are formed in the first insulating layer 2, and the plurality of electrode regions 3 are arranged along the length direction of the first insulating layer 2; the step of forming a limiting layer 4 on the upper surface of the first insulating layer 2 includes the following steps:

[0080] The setting area of ​​several electrode regions 3 is defined by exposing the first insulating layer 2;

[0081] The unexposed areas of the first insulating layer 2 are removed by development to form several electrode areas 3;

[0082] A second insulating layer 6 is formed above the first insulating layer 2 and within several electrode regions 3;

[0083] By exposing the area of ​​the second insulating layer 6 other than certain electrode regions 3;

[0084] The exposed area of ​​the second insulating layer 6 is removed by development, and the remaining part forms a plurality of second insulating pillars 61, which protrude from the first insulating layer 2;

[0085] A limiting layer 4 is formed on the upper part of the second insulating column 61, and the limiting layer 4 is connected to the first insulating layer 2.

[0086] By adding a second insulating layer 6, a number of second insulating pillars 61 are ultimately formed. The second insulating pillars 61 are then used to support the limiting layer 4. After the limiting layer 4 is formed, the second insulating pillars 61 are removed. Since the upper part of the second insulating pillar 61 protrudes from the first insulating layer 2, the area between the adjacent first insulating block 21 and the limiting layer 4 is the expanded electrode area 3. The electrode layer 5 formed in this expanded electrode space also has the characteristic of protruding from the first insulating layer 2. The electrodes protruding from the first insulating layer 2 are more conducive to the subsequent soldering of the resistor structure to the circuit board, which has the effect of improving the connection stability between the resistor structure and the circuit board.

[0087] Optionally, the step of forming a limiting layer 4 covering the second insulating post 61, and connecting the limiting layer 4 to the first insulating layer 2, includes the following steps:

[0088] The first insulating layer 2 is divided into several first insulating blocks 21 by several electrode regions 3; the limiting layer 4 covers the upper part of the second insulating column 61, and the two ends of the limiting layer 4 are connected to the top of the adjacent first insulating block 21.

[0089] The limiting layer 4 has an inverted U-shaped structure. The limiting layer 4 covers the second insulating post 61, which protrudes from the upper part of the first insulating block 21. Both ends of the limiting layer 4 are connected to the top of the adjacent first insulating block 21 to ensure the stability of the limiting layer 4 and prevent the limiting layer 4 from falling off and affecting the formation of the electrode.

[0090] Optionally, the step of forming the second insulating layer 6 above the first insulating layer 2 and within a plurality of electrode regions 3 includes the following steps:

[0091] The thickness of the first insulating layer 2 ranges from 10µm to 100µm;

[0092] The thickness of the portion of the second insulating layer 6 located on the upper surface of the first insulating layer 2 ranges from 10 μm to 100 μm.

[0093] The thickness of the second insulating layer 6 is equal to the height of the electrode layer 5 protruding from the first insulating layer 2. By controlling the thickness of the first insulating layer 2 and the second insulating layer 6, the overall thickness of the resistor structure can be controlled, thereby achieving precise control of the resistance value.

[0094] Optionally, forming a second insulating layer 6 above the first insulating layer 2 and within a plurality of electrode regions 3, wherein the first insulating layer 2 and the second insulating layer 6 are made of different insulating materials, further includes the following steps:

[0095] The first insulating layer 2 includes a solder resist ink layer, and the second insulating layer 6 includes a positive photoresist layer.

[0096] The second insulating layer 6 includes a positive photoresist layer, which has the advantage of being easy to remove. The second insulating layer 6 can be removed simply by exposure and development, while avoiding any impact on the structure of the first insulating layer 2, thus offering the advantage of simple operation.

[0097] Example 3

[0098] Reference Figure 1 , Figure 4 Compared with Embodiment 2, the difference in this embodiment lies in the step of forming the second insulating layer 6 above the first insulating layer 2 and within the plurality of electrode regions 3, which includes the following steps:

[0099] A third insulating layer 7 is formed on the outer surface of the first insulating block 21;

[0100] A second insulating layer 6 is formed above the third insulating layer 7 and within several electrode regions 3;

[0101] The first insulating layer 2 includes a solder resist ink layer, and the second insulating layer 6 includes a positive photoresist layer or a negative photoresist layer.

[0102] The third insulating layer 7 is made of silicon dioxide, and the second insulating layer 6 includes either a positive photoresist layer or a negative photoresist layer. The second insulating layer 6 can be removed simply by exposure and development, avoiding any impact on the structure of the first insulating layer 2, thus offering the advantage of simple operation. By adding the third insulating layer 7, the second insulating layer 6 can be made of various materials, providing a high degree of adaptability.

[0103] The technical solution of this invention involves forming a first insulating layer 2 on the upper surface of a resistive layer 1; subsequently forming a plurality of electrode regions 3 in the first insulating layer 2, with the electrode regions 3 arranged along the length of the first insulating layer 2; then forming a limiting layer 4 on the upper surface of the first insulating layer 2; subsequently forming an electrode layer 5 within the electrode regions 3, with both sides of the electrode layer 5 connected to the adjacent first insulating layer 2, and the upper surface of the electrode layer 5 in contact with the limiting layer 4; finally removing the limiting layer 4 to obtain the finished resistor structure. By utilizing the limiting layer 4 to form a flat surface on the upper surface of the electrode layer 5, the shape of the upper surface of the electrode layer 5 in the resistor structure is precisely controlled, avoiding the formation of a convex structure in the electrode layer 5 and improving the production quality of the resistor structure; at the same time, it avoids the electrode layer 5 from spreading to the top of the first insulating layer 2, thus improving the production stability of the resistance value of the resistor structure.

[0104] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a resistor structure, characterized in that, Includes the following steps: A first insulating layer is formed on the upper surface of the resistive layer; A plurality of electrode regions are formed in a first insulating layer, and the plurality of electrode regions are arranged along the length direction of the first insulating layer; A limiting layer is formed on the upper surface of the first insulating layer; An electrode layer is formed in the electrode region, the two sides of the electrode layer are connected to the adjacent first insulating layer, and the upper surface of the electrode layer is in contact with the limiting layer. The resistor structure is obtained by removing the limiting layer. The step of forming a plurality of electrode regions in a first insulating layer, wherein the plurality of electrode regions are arranged along the length direction of the first insulating layer; and forming a limiting layer on the upper surface of the first insulating layer includes the following steps: The setting area of ​​the plurality of electrode regions is defined by exposing the first insulating layer; The unexposed areas of the first insulating layer are removed by development to form the plurality of electrode areas; A second insulating layer is formed above the first insulating layer and within the plurality of electrode regions; By exposing the area of ​​the second insulating layer other than the aforementioned electrode regions; The exposed area of ​​the second insulating layer is removed by development, and the remaining part forms a plurality of second insulating pillars, which protrude from the first insulating layer; The limiting layer is formed on the upper part of the second insulating pillar, and the limiting layer is connected to the first insulating layer.

2. The method for processing the resistor structure as described in claim 1, characterized in that, The step of forming a plurality of electrode regions in a first insulating layer, wherein the plurality of electrode regions are arranged along the length direction of the first insulating layer; and forming a limiting layer on the upper surface of the first insulating layer includes the following steps: The setting area of ​​the plurality of electrode regions is defined by exposing the first insulating layer; After forming a limiting layer on the upper surface of the first insulating layer, the unexposed areas of the first insulating layer are removed by development to form the plurality of electrode areas.

3. The method for processing the resistor structure as described in claim 2, characterized in that, The step of forming a first insulating layer on the upper surface of the resistive layer includes the following steps: The thickness of the first insulating layer ranges from 10µm to 200µm.

4. The method of processing a resistive structure of claim 2, wherein, The step of forming a limiting layer on the upper surface of the first insulating layer includes the following steps: A plurality of limiting layers are formed on the upper surface of the insulating layer, the number of the limiting layers being equal to the number of the electrode regions; the limiting layers are located above the electrode regions. The first insulating layer is divided into several first insulating blocks by the several electrode regions, and the two ends of the limiting layer are respectively connected to the adjacent first insulating blocks.

5. The method of processing a resistive structure of claim 1, wherein, The step of forming the limiting layer on the upper part of the second insulating post, wherein the limiting layer is connected to the first insulating layer, includes the following steps: The first insulating layer is divided into several first insulating blocks by the several electrode regions; the limiting layer covers the upper part of the second insulating column, and the two ends of the limiting layer are connected to the top of the adjacent first insulating block.

6. The method of processing a resistive structure of claim 5, wherein, The step of forming a second insulating layer above the first insulating layer and within the plurality of electrode regions includes the following steps: A third insulating layer is formed on the outer surface of the first insulating block; A second insulating layer is formed above the third insulating layer and within the plurality of electrode regions; and / or, The thickness of the first insulating layer ranges from 10µm to 100µm; The thickness of the portion of the second insulating layer located on the upper surface of the first insulating layer ranges from 10µm to 100µm.

7. The method of processing a resistive structure of claim 6, wherein, The step of forming a second insulating layer above the first insulating layer and within the plurality of electrode regions further includes the following steps: The first insulating layer includes a solder resist ink layer, and the second insulating layer includes a positive photoresist layer; and / or, The first insulating layer includes a solder resist ink layer, and the second insulating layer includes a positive photoresist layer or a negative photoresist layer.

8. The method for processing the resistor structure according to any one of claims 1 to 7, characterized in that, The step of forming a limiting layer on the upper surface of the first insulating layer includes the following steps: The thickness of the limiting layer ranges from 0.1µm to 20µm; and / or, The limiting layer includes a silicon dioxide layer.

9. The method for processing the resistor structure according to any one of claims 1 to 7, characterized in that, The step of forming an electrode layer in the electrode region, wherein both sides of the electrode layer are connected to the adjacent first insulating layer, and the upper surface of the electrode layer is in contact with the limiting layer, further includes the following steps: The electrode layer is formed in the electrode region by electroplating.

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