Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, wherein the preparation method comprises the following steps: (1) providing a substrate with an epitaxial layer; (2) inputting a reaction gas with an i-th flow rate to form an i-th sub-column layer, and the distribution proportion of the input reaction gas gradually increases from the center to the edge; (3) etching back the i-th sub-column layer, and the etching rate gradually increases from the center to the edge; (4) repeatedly executing steps 2-3; (5) inputting a reaction gas with an N+1-th flow rate to form an N+1-th sub-column layer, and the N+1-th flow rate is less than the N-th flow rate; (6) removing the N+1-th sub-column layer above the epitaxial layer. By executing the above steps, the ion doping concentration in the combined column layer in each groove can be reduced with the increase of the thickness of the combined column layer, and the ion doping concentration of the column layer in different regions can be simultaneously reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a semiconductor device and its fabrication method. Background Technology

[0002] In the manufacturing process of deep trench-filled superjunction products, EPI is widely used in the epitaxial growth of substrate surface layers. Epitaxial growth includes epitaxial layer growth and pillar filling in deep trenches within the epitaxial layer.

[0003] Currently, epitaxy is commonly available in single-layer and double / multi-layer concentrations. Typically, single-layer epitaxial superjunction products exhibit strong nonlinearity in both the Crss (output capacitance) and Coss (output transfer capacitance) curves, which affects the switching characteristics of the superjunction product. In contrast, double / multi-layer epitaxial superjunction products show significantly slower Coss and Crss curves, which can improve the switching characteristics of the device.

[0004] However, superjunction products deplete their breakdown voltage through charge balance between the epitaxial layer and the pillar layer. If a multi-layer epitaxial layer is used, the pillar layer needs to be matched with the corresponding concentration. The PN matching of small-pitch superjunction products is extremely sensitive, and it is very easy for the concentration matching of the pillar layer in the wafer center region and the wafer edge region to be unbalanced, resulting in a low and discrete BV (breakdown voltage). Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method, which can solve the problem of low and discrete BV (breakdown voltage) caused by the imbalance of pillar layer concentration in different regions of the wafer surface in traditional deep trench filled superjunction products.

[0006] On one hand, embodiments of this application provide a method for fabricating a semiconductor device, including: First step: Provide a substrate on which an epitaxial layer is formed, and an array of trenches are formed in the epitaxial layer, wherein the concentration of doped ions in the epitaxial layer gradually decreases as the thickness of the epitaxial layer increases; the substrate, from the center to the edge, sequentially includes: a circular central region, an annular transition region, and an annular edge region; The second step is to introduce the reaction gas at a flow rate of i into the process chamber to form the i-th sub-pillar layer in the trench. The distribution ratio of the introduced reaction gas gradually increases from the center of the substrate to the edge of the substrate, so that the thickness of the i-th sub-pillar layer gradually increases from the center of the substrate to the edge of the substrate. The third step is to etch back a certain thickness of the i-th sub-pillar layer in the trench, wherein the etching rate of the i-th sub-pillar layer in the central region is less than the etching rate of the i-th sub-pillar layer in the transition region, and the etching rate of the i-th sub-pillar layer in the transition region is less than the etching rate of the i-th sub-pillar layer in the edge region. Fourth step: Repeat the second step to the third step for a total of N-1 times, with i increasing each time, until the upper surface of the Nth sub-pillar layer in the edge region of the second step is flush with or higher than the upper surface of the epitaxial layer, where N is an integer greater than or equal to 2, and the flow rate of the dopant gas in the reaction gas introduced in the later step is less than the flow rate of the dopant gas in the reaction gas introduced in the previous step. Fifth step: Introduce the reaction gas at a flow rate of N+1 into the process chamber to form the N+1 sub-pillar layer in the trench, wherein the flow rate of the doping gas in the reaction gas at the N+1 flow rate is less than the Nth flow rate, so that the ion doping concentration in each sub-pillar layer in each trench decreases layer by layer from bottom to top. Step 6: Grinding removes the N+1th sub-pillar layer that extends beyond the top of the trench and the surface of the epitaxial layer to obtain a combined pillar layer; Where i is the sequence number of the cyclic process, and its value is an integer from 1 to N.

[0007] Optionally, in the method for preparing the semiconductor device, the reaction gas includes: H2, SiH2Cl2 (DCS), HCl and B2H6.

[0008] Optionally, in the method for fabricating the semiconductor device, the number of gas pipelines for introducing the reaction gas in the process chamber is at least two.

[0009] Optionally, in the method for fabricating the semiconductor device, there are two gas pipelines in the process chamber for introducing the reaction gas: one gas pipeline is located above the edge region, and the other gas pipeline is located above the center region.

[0010] Optionally, in the semiconductor device fabrication method, in the second step, a reaction gas with an i-th flow rate is introduced into the process chamber to form an i-th sub-pillar layer in the trench, wherein the gas distribution ratio in the central region is less than the gas distribution ratio in the edge region, so that the ion doping concentration in the i-th sub-pillar layer in the edge region is greater than the ion doping concentration in the i-th sub-pillar layer in the central region.

[0011] Optionally, in the method for fabricating the semiconductor device, the gas distribution ratio of the central region is equal to 1 minus the gas distribution ratio of the edge region.

[0012] Optionally, in the method for fabricating the semiconductor device, the gas pipeline for introducing the reaction gas in the process chamber is three-way: the first gas pipeline is located above the edge region, the second gas pipeline is located above the transition region, and the third gas pipeline is located above the center region.

[0013] Optionally, in the semiconductor device fabrication method, in the second step, a reaction gas with an i-th flow rate is introduced into the process chamber to form an i-th sub-pillar layer in the trench, wherein the gas distribution ratio in the central region is less than the gas distribution ratio in the transition region, and the gas distribution ratio in the transition region is less than the gas distribution ratio in the edge region, so that the ion doping concentration in the i-th sub-pillar layer in the edge region is greater than the ion doping concentration in the i-th sub-pillar layer in the transition region, and the ion doping concentration in the i-th sub-pillar layer in the transition region is greater than the ion doping concentration in the i-th sub-pillar layer in the central region.

[0014] Optionally, in the method for fabricating the semiconductor device, the gas distribution ratio of the central region = 1 - the gas distribution ratio of the edge region - the gas distribution ratio of the transition region.

[0015] Optionally, in the semiconductor device fabrication method, the process parameters for etching back the pillar layer in the third step include: a process chamber pressure of 10 Torr to 700 Torr; a process chamber temperature of 900°C to 1150°C; and a gas involved in the etching back including HCl, wherein the flow rate of HCl is 100 slm to 10000 slm, wherein, from the center of the substrate to the edge of the substrate, the flow rate of HCl in the edge region is greater than the flow rate of HCl in the transition region, and the flow rate of HCl in the transition region is greater than the flow rate of HCl in the center region, and / or the temperature of the edge region is greater than the temperature of the transition region, and the temperature of the transition region is greater than the temperature of the center region.

[0016] On the other hand, embodiments of this application also provide a semiconductor device, wherein the method for fabricating the semiconductor device includes: A substrate on which an epitaxial layer is formed, wherein an array of trenches is formed in the epitaxial layer, wherein the concentration of doped ions in the epitaxial layer gradually decreases as the thickness of the epitaxial layer increases; the substrate, from the center to the edge, sequentially includes: a circular central region, an annular transition region, and an annular edge region. A composite pillar layer fills the trench. From bottom to top, the composite pillar layer includes stacked first sub-pillar layers, second sub-pillar layers to N+1th sub-pillar layers. The ion doping concentration of the first sub-pillar layer is greater than that of the second sub-pillar layer, the ion doping concentration of the second sub-pillar layer is greater than that of the third sub-pillar layer, and so on, with the ion doping concentration of the Nth sub-pillar layer being greater than that of the N+1th sub-pillar layer, where N is an integer greater than or equal to 2.

[0017] The technical solution of this application has at least the following advantages: This application obtains a first sub-pillar layer, a second sub-pillar layer, and an N+1th sub-pillar layer with progressively decreasing doping concentration from bottom to top by executing steps one through six. The first sub-pillar layer, the second sub-pillar layer, and the N+1th sub-pillar layer are combined to form a final combined pillar layer. This not only allows the ion doping concentration in the combined pillar layer in each trench to decrease layer by layer as the thickness of the combined pillar layer increases, thus matching the ion doping concentration at different thickness positions in the combined pillar layer with the ion doping concentration at different thickness positions in the epitaxial layer, but also simultaneously lowers the ion doping concentration of the pillar layer in different regions of the wafer surface. This avoids the situation in traditional deep trench filled superjunction products where the pillar layer concentration mismatch in different regions of the wafer surface leads to a low and discrete BV (breakdown voltage). This improves the imbalance of pillar layer concentration mismatch in different regions of the wafer surface, increases the overall BV (breakdown voltage) of the device, and balances the BV in different regions of the wafer surface. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the semiconductor structure in the first step of an embodiment of the present invention; Figure 3 This is a schematic diagram of the semiconductor structure after the second step is executed for the first time in an embodiment of the present invention; Figure 4 This is a schematic diagram of the semiconductor structure after the first execution of the third step in an embodiment of the present invention; Figure 5This is a schematic diagram of the semiconductor structure after the second step is executed for the second time in an embodiment of the present invention; Figure 6 This is a schematic diagram of the semiconductor structure after the second execution of the third step in an embodiment of the present invention; Figure 7 This is a schematic diagram of the semiconductor structure after the fifth execution of the third step and the continued execution of the fifth and sixth steps in an embodiment of the present invention. The reference numerals in the attached figures are explained as follows: 10-Substrate, 20-Epipolar layer, 30-Trench, 41-First sub-pillar layer, 42-Second sub-pillar layer, 43-Third sub-pillar layer, 44-Fourth sub-pillar layer, 45-Fifth sub-pillar layer, 46-Sixth sub-pillar layer. Detailed Implementation

[0020] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0024] The inventors discovered that simultaneously reducing the ion doping concentration of the pillar layers in both the wafer center and edge regions can specifically enhance the high-voltage breakdown resistance and reduce the imbalance of BV in different regions within the wafer plane. However, the dopant gas distribution ratios in the wafer center and edge regions are contradictory. Adjusting the dopant gas distribution will either expand or decrease the doping concentration range of the pillar layers within the plane. Expanding the range results in a reduction of the ion doping concentration in the wafer edge region and an increase in the ion doping concentration in the wafer center region, while decreasing the range results in a reduction in the wafer center region and an increase in the wafer edge region. It is impossible to simultaneously reduce the ion doping concentration of the pillar layers in both the wafer center and edge regions. In this embodiment, the range can be understood as the difference between the maximum and minimum doping concentrations of the wafer.

[0025] Furthermore, the inventors discovered that forming a columnar layer through multiple doping reactions is a simple and direct method. Specifically, by gradually reducing the overall flow rate of each reaction and distributing the gas pipelines inside and outside the reaction equally in each reaction, it is theoretically possible to obtain a columnar with a concentration that is simultaneously diluted at the center and the edge. However, in actual engineering, due to the influence of multiple factors such as wafer rotation, gas distribution, patterning effects, and growth, it is difficult to obtain a columnar with a uniform concentration distribution from the center to the edge on patterned wafers.

[0026] To address the aforementioned problems, the inventors have provided a novel method for fabricating semiconductor devices, which will be described in detail below.

[0027] This application provides a method for fabricating a semiconductor device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The method for fabricating the semiconductor device includes: First step: Provide a substrate on which an epitaxial layer is formed, and an array of trenches are formed in the epitaxial layer, wherein the concentration of doped ions in the epitaxial layer gradually decreases as the thickness of the epitaxial layer increases; the substrate, from the center to the edge, sequentially includes: a circular central region, an annular transition region, and an annular edge region; The second step is to introduce the reaction gas at a flow rate of i into the process chamber to form the i-th sub-pillar layer in the trench. The distribution ratio of the introduced reaction gas gradually increases from the center of the substrate to the edge of the substrate, so that the thickness of the i-th sub-pillar layer gradually increases from the center of the substrate to the edge of the substrate. The third step is to etch back a certain thickness of the i-th sub-pillar layer in the trench, wherein the etching rate of the i-th sub-pillar layer in the central region is less than the etching rate of the i-th sub-pillar layer in the transition region, and the etching rate of the i-th sub-pillar layer in the transition region is less than the etching rate of the i-th sub-pillar layer in the edge region. Fourth step: Repeat the second step to the third step for a total of N-1 times, with i increasing each time, until the upper surface of the Nth sub-pillar layer in the edge region of the second step is flush with or higher than the upper surface of the epitaxial layer, where N is an integer greater than or equal to 2, and the flow rate of the dopant gas in the reaction gas introduced in the later step is less than the flow rate of the dopant gas in the reaction gas introduced in the previous step. Fifth step: Introduce the reaction gas at a flow rate of N+1 into the process chamber to form the N+1 sub-pillar layer in the trench, wherein the flow rate of the doping gas in the reaction gas at the N+1 flow rate is less than the Nth flow rate, so that the ion doping concentration in each sub-pillar layer in each trench decreases layer by layer from bottom to top. Step 6: Grinding removes the N+1th sub-pillar layer that extends beyond the top of the trench and the surface of the epitaxial layer to obtain a combined pillar layer; Where i is the sequence number of the cyclic process, and its value is an integer from 1 to N.

[0028] refer to Figures 2-7 This embodiment takes N=5 as an example to specifically introduce the fabrication method of the semiconductor device.

[0029] Step S1: Reference Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure in the first step of an embodiment of the present invention. A substrate 10 is provided, on which an epitaxial layer 20 is formed. A plurality of trenches 30 are formed in an array in the epitaxial layer 20. As the thickness of the epitaxial layer 20 increases, the concentration of doped ions in the epitaxial layer 20 gradually decreases. The substrate 10 includes, from the center to the edge, a circular central region, an annular transition region, and an annular edge region.

[0030] In some embodiments, a 9-inch (300mm in diameter, 150mm in radius) wafer can be selected, the central region is an inner circle with a radius of 0mm to 37.5mm, the transition region is an annulus with a diameter of 37.5mm to 112.5mm, and the edge region is an annulus with a radius of 112.5mm to 150mm.

[0031] Step S2: Reference Figure 3 , Figure 3This is a schematic diagram of the semiconductor structure after the second step is executed for the first time in an embodiment of the present invention. A first flow rate of reactive gas is introduced into the process chamber to form a first sub-pillar layer 41 in the trench. The distribution ratio of the introduced reactive gas gradually increases from the center of the substrate to the edge of the substrate, so that the thickness of the first sub-pillar layer 41 gradually increases from the center of the substrate to the edge of the substrate.

[0032] from Figure 3 As can be seen from the cross-section of the semiconductor structure, the thickness of the first sub-pillar layer 41 gradually increases from the center of the substrate to the edge of the substrate, making the first sub-pillar layer 41 on the whole wafer have a "V" shape with a large opening.

[0033] In this embodiment, the reaction gases include: H2, SiH2Cl2 (DCS), HCl, and B2H6. H2 is the carrier gas; SiH2Cl2 (DCS) is the growth gas; HCl is the etching gas; and B2H6 is the doping gas. The initial flow rate of H2 is 10 L to 100 L; the initial flow rate of SiH2Cl2 (DCS) is 100 sccm to 5000 sccm; the initial flow rate of HCl is 100 sccm to 5000 sccm; and the initial flow rate of B2H6 is 10 sccm to 3000 sccm.

[0034] Step 3 (S3): Reference Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the first execution of the third step in this embodiment of the invention. A first sub-pillar layer 41 of a certain thickness in the trench is etched back, wherein the etching rate of the first sub-pillar layer 41 in the central region is less than the etching rate of the first sub-pillar layer 41 in the transition region, and the etching rate of the first sub-pillar layer 41 in the transition region is less than the etching rate of the first sub-pillar layer 41 in the edge region. Figure 4 As can be seen, the thickness of the first sub-pillar layer 41 in the edge region that is etched back is greater than the thickness of the first sub-pillar layer 41 in the transition region that is etched back, and the thickness of the first sub-pillar layer 41 in the transition region that is etched back is greater than the thickness of the first sub-pillar layer 41 in the center region that is etched back.

[0035] This application etches back a first sub-pillar layer 41 of a certain thickness in the trenches of different regions on the wafer, wherein the etching rate gradually increases from the center region to the edge region. This removes the thickest first sub-pillar layer 41 in the edge region, the thicker first sub-pillar layer 41 in the transition region, and the thinner first sub-pillar layer 41 in the center region, thereby making the upper surface of the first sub-pillar layer 41 in the edge region, the upper surface of the first sub-pillar layer 41 in the transition region, and the upper surface of the first sub-pillar layer 41 in the center region flush.

[0036] Preferably, in the third step, the process parameters for re-etching the first sub-pillar layer 41 include: a process chamber pressure of 10 Torr to 700 Torr; a process chamber temperature of 900°C to 1150°C; and the gas involved in the re-etching includes HCl, wherein the flow rate of HCl is 100 slm to 10000 slm, wherein, from the center of the substrate to the edge of the substrate, the flow rate of HCl in the edge region is greater than the flow rate of HCl in the transition region, and the flow rate of HCl in the transition region is greater than the flow rate of HCl in the center region, and / or the temperature of the edge region is greater than the temperature of the transition region, and the temperature of the transition region is greater than the temperature of the center region.

[0037] Fourth step S4: Continue to repeat the second to the third steps four times in sequence, that is, the second to the third steps are executed a total of five times, that is, forming the second sub-pillar layer 42; etching back the second sub-pillar layer 42 of a certain thickness; forming the third sub-pillar layer 43; etching back the third sub-pillar layer 43 of a certain thickness, ..., forming the fifth sub-pillar layer 45, until the upper surface of the fifth sub-pillar layer 45 in the edge region of the second step is flush with or higher than the upper surface of the epitaxial layer 20, wherein the flow rate of the reaction gas introduced in the later step is less than the flow rate of the reaction gas introduced in the previous step.

[0038] It is worth noting that the number of times (N-1) the second to the third steps are repeated is determined by the depth of the trench and the thickness of each sub-pillar layer. This application does not limit the number of times the second to the third steps are repeated.

[0039] In this embodiment, the fourth step S4 may specifically include: refer to Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the second step of the second embodiment of the present invention. A second flow rate of reactive gas is introduced into the process chamber to form a second sub-pillar layer 42 in the trench. The distribution ratio of the introduced reactive gas gradually increases from the center of the substrate to the edge of the substrate, so that the thickness of the second sub-pillar layer 42 gradually increases from the center of the substrate to the edge of the substrate, making the second sub-pillar layer 42 on the entire wafer have a "V" shape with a large opening. The reactive gas includes: H2, SiH2Cl2 (DCS), HCl and B2H6, wherein the second flow rate of H2 is 10L~100L; the second flow rate of SiH2Cl2 (DCS) is 100sccm~5000sccm; the second flow rate of HCl is 100sccm~5000sccm; and the second flow rate of B2H6 is 10sccm~3000sccm.

[0040] refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the second execution of the third step in this embodiment of the invention. A second sub-pillar layer 42 of a certain thickness in the trench is etched back, wherein the etching rate of the second sub-pillar layer 42 etched back in the central region is less than the etching rate of the second sub-pillar layer 42 etched back in the transition region, and the etching rate of the second sub-pillar layer 42 etched back in the transition region is less than the etching rate of the second sub-pillar layer 42 etched back in the edge region. Figure 4 As can be seen, the thickness of the second sub-pillar layer 42 etched back in the edge region is greater than the thickness of the second sub-pillar layer 42 etched back in the transition region, and the thickness of the second sub-pillar layer 42 etched back in the transition region is greater than the thickness of the second sub-pillar layer 42 etched back in the center region. This application etches back a certain thickness of the second sub-pillar layer 42 in the trenches of different regions on the wafer, wherein the etching rate gradually increases from the center region to the edge region. This removes the thickest second sub-pillar layer 42 in the edge region, the relatively thick second sub-pillar layer 42 in the transition region, and the relatively thin second sub-pillar layer 42 in the center region, thereby making the upper surface of the second sub-pillar layer 42 in the edge region, the upper surface of the second sub-pillar layer 42 in the transition region, and the upper surface of the second sub-pillar layer 42 in the center region flush. A third flow rate of reactive gas is introduced into the process chamber to form a third sub-pillar layer 43 in the trench. The proportion of the reactive gas gradually increases from the center of the substrate to the edge of the substrate, so that the thickness of the third sub-pillar layer 43 gradually increases from the center of the substrate to the edge of the substrate, making the third sub-pillar layer 43 on the entire wafer have a "V" shape with a large opening. The reactive gas includes H2, SiH2Cl2 (DCS), HCl and B2H6, wherein the third flow rate of H2 is 10L~100L; the third flow rate of SiH2Cl2 (DCS) is 100sccm~5000sccm; the third flow rate of HCl is 100sccm~5000sccm; and the third flow rate of B2H6 is 10sccm~3000sccm.

[0041] The third sub-pillar layer 43 of a certain thickness in the trench is etched back, wherein the etching rate of the third sub-pillar layer 43 in the central region is less than the etching rate of the third sub-pillar layer 43 in the transition region, and the etching rate of the third sub-pillar layer 43 in the transition region is less than the etching rate of the third sub-pillar layer 43 in the edge region. This application etches back the third sub-pillar layer 43 of a certain thickness in the trench in different regions of the wafer, wherein the etching rate gradually increases from the central region to the edge region. This removes the thickest third sub-pillar layer 43 in the edge region, the relatively thick third sub-pillar layer 43 in the transition region, and the relatively thin third sub-pillar layer 43 in the central region, thereby making the upper surface of the third sub-pillar layer 43 in the edge region, the upper surface of the third sub-pillar layer 43 in the transition region, and the upper surface of the third sub-pillar layer 43 in the central region flush. A fourth flow rate of reactive gas is introduced into the process chamber to form a fourth sub-pillar layer 44 in the trench. The proportion of the reactive gas gradually increases from the center of the substrate to the edge of the substrate, so that the thickness of the fourth sub-pillar layer 44 gradually increases from the center of the substrate to the edge of the substrate, making the fourth sub-pillar layer 44 on the entire wafer have a large opening "V" shape. The reactive gas includes H2, SiH2Cl2 (DCS), HCl and B2H6, wherein the fourth flow rate of H2 is 10L~100L; the fourth flow rate of SiH2Cl2 (DCS) is 100sccm~5000sccm; the fourth flow rate of HCl is 100sccm~5000sccm; and the fourth flow rate of B2H6 is 10sccm~3000sccm.

[0042] The fourth sub-pillar layer 44 of a certain thickness in the trench is etched back, wherein the etching rate of the fourth sub-pillar layer 44 in the central region is less than the etching rate of the fourth sub-pillar layer 44 in the transition region, and the etching rate of the fourth sub-pillar layer 44 in the transition region is less than the etching rate of the fourth sub-pillar layer 44 in the edge region. This application etches back fourth sub-pillar layers 44 of a certain thickness in different regions of the trench on the wafer, wherein the etching rate gradually increases from the central region to the edge region. This removes the thickest fourth sub-pillar layer 44 in the edge region, the relatively thick fourth sub-pillar layer 44 in the transition region, and the relatively thin fourth sub-pillar layer 44 in the central region, thereby making the upper surfaces of the fourth sub-pillar layers 44 in the edge region, the transition region, and the central region flush; and... A fifth flow rate of reactive gas is introduced into the process chamber to form a fifth sub-pillar layer 45 in the trench. The proportion of the reactive gas gradually increases from the center of the substrate towards the substrate edge, causing the thickness of the fifth sub-pillar layer 45 to gradually increase from the center to the edge, resulting in a "V" shape with a large opening on the entire wafer. At this time, the upper surface of the fifth sub-pillar layer 45 in the edge region is flush with or higher than the upper surface of the epitaxial layer 20. The reactive gas includes H2, SiH2Cl2 (DCS), HCl, and B2H6, with the fifth flow rate of H2 being 10L~100L; the fifth flow rate of SiH2Cl2 (DCS) being 100sccm~5000sccm; the fifth flow rate of HCl being 100sccm~5000sccm; and the fifth flow rate of B2H6 being 10sccm~3000sccm.

[0043] A fifth sub-pillar layer 45 of a certain thickness is etched back into the trench. The etching rate of the fifth sub-pillar layer 45 in the central region is lower than that in the transition region, and the etching rate of the fifth sub-pillar layer 45 in the transition region is lower than that in the edge region. This application etches back fifth sub-pillar layers 45 of a certain thickness into different regions of the trench on the wafer, with the etching rate gradually increasing from the central region to the edge region. This removes the thickest fifth sub-pillar layer 45 in the edge region, the relatively thick fifth sub-pillar layer 45 in the transition region, and the relatively thin fifth sub-pillar layer 45 in the central region, thereby making the upper surfaces of the fifth sub-pillar layers 45 in the edge region, the transition region, and the central region flush.

[0044] Because the upper surface of the fifth sub-pillar layer 45 in the edge region is flush with or higher than the upper surface of the epitaxial layer 20, the second to third steps are not repeated, and the fifth step S5 is executed next.

[0045] Preferably, the number of gas pipelines for introducing reaction gases into the process chamber is at least two.

[0046] In this embodiment, the gas pipelines for introducing the reactive gas within the process chamber are two-way: one gas pipeline is located above the edge region, and the other gas pipeline is located above the central region. In the second step, reactive gases at flow rates from first to sixth are sequentially introduced into the process chamber, forming a first sub-pillar layer, a second sub-pillar layer, and a sixth sub-pillar layer in the trench. The gas distribution ratio in the central region is less than that in the edge region, so that the growth rate of the i-th sub-pillar layer in the edge region is greater than that in the central region. The gas distribution ratio in the central region is 1 minus the gas distribution ratio in the edge region. Because the growth rate of the i-th sub-pillar layer in the edge region is greater than that in the central region, the thickness of the i-th sub-pillar layer gradually increases from the substrate center towards the substrate edge, resulting in a "V" shape with a large opening for the i-th sub-pillar layer across the entire wafer.

[0047] In other embodiments, the gas pipelines introducing the reactant gas within the process chamber are three-way: the first gas pipeline is located above the edge region, the second gas pipeline is located above the transition region, and the third gas pipeline is located above the central region. In the second step, reactant gases at first to sixth flow rates are sequentially introduced into the process chamber, forming a first sub-pillar layer, a second sub-pillar layer, and a sixth sub-pillar layer in the trench. The gas distribution ratio in the central region is less than that in the transition region, and the gas distribution ratio in the transition region is less than that in the edge region. This ensures that the growth rate of the i-th sub-pillar layer in the edge region is greater than that in the transition region, and the growth rate of the i-th sub-pillar layer in the transition region is greater than that in the central region. The gas distribution ratio in the central region = 1 - the gas distribution ratio in the edge region - the gas distribution ratio in the transition region. Because the growth rate of the i-th sub-pillar layer in the edge region is greater than that in the transition region, and the growth rate of the i-th sub-pillar layer in the transition region is greater than that in the center region, the thickness of the i-th sub-pillar layer gradually increases from the center of the substrate to the edge of the substrate, so that the i-th sub-pillar layer on the whole wafer has a "V" shape with a large opening.

[0048] In other embodiments, the transition region, from the inside out, sequentially includes a ring-shaped inner ring region and a ring-shaped outer ring region. Therefore, the gas pipelines introducing the reactant gas within the process chamber can be four: the first gas pipeline is located above the edge region, the second gas pipeline is located above the outer ring region, the third gas pipeline is located above the inner ring region, and the fourth gas pipeline is located above the central region. The gas distribution ratio gradually increases from the central region towards the edge region, and the sum of the gas distribution ratios in different regions is 1. In other embodiments, the gas pipelines introducing the reactant gas within the process chamber are three: the first gas pipeline is located above the edge region, the second gas pipeline is located above the transition region, and the third gas pipeline is located above the central region. In the second step, reaction gases at flow rates of first to sixth are sequentially introduced into the process chamber to form a first sub-pillar layer, a second sub-pillar layer, and a sixth sub-pillar layer in the trench. The gas distribution ratio in the central region is less than that in the transition region, and the gas distribution ratio in the transition region is less than that in the edge region. This ensures that the growth rate of the i-th sub-pillar layer in the edge region is greater than that in the transition region, and the growth rate of the i-th sub-pillar layer in the transition region is greater than that in the central region. The gas distribution ratio in the central region = 1 - the gas distribution ratio in the edge region - the gas distribution ratio in the transition region. Because the growth rate of the i-th sub-pillar layer in the edge region is greater than that in the transition region, and the growth rate of the i-th sub-pillar layer in the transition region is greater than that in the central region, the thickness of the i-th sub-pillar layer gradually increases from the center of the substrate towards the edge, resulting in a "V" shape with a large opening for the i-th sub-pillar layer across the entire wafer.

[0049] In other embodiments, the transition region, from the inside out, sequentially comprises a ring-shaped inner ring region and a ring-shaped outer ring region. Therefore, the gas pipelines introducing the reaction gas into the process chamber can be four: the first gas pipeline is located above the edge region, the second gas pipeline is located above the outer ring region, the third gas pipeline is located above the inner ring region, and the fourth gas pipeline is located above the central region. The gas distribution ratio gradually increases from the central region towards the edge region, and the sum of the gas distribution ratios in different regions is 1.

[0050] Step 5 (S5): Reference Figure 7 , Figure 7This is a schematic diagram of the semiconductor structure after the fifth execution of the third step and the continued execution of the fifth and sixth steps in an embodiment of the present invention. A sixth flow rate of reaction gas is introduced into the process chamber to form a sixth sub-pillar layer 46 in the trench.

[0051] In the above reaction gases, H2 is the carrier gas; SiH2Cl2 (DCS) is the growth gas; HCl is the etching gas; and B2H6 is the dopant gas. The flow rates of H2, SiH2Cl2 (DCS), and HCl in each reaction satisfy the following conditions: the sixth flow rate is less than the fifth flow rate, the fifth flow rate is less than the fourth flow rate, the fourth flow rate is less than the third flow rate, and so on, ..., the second flow rate is less than the first flow rate. The flow rates of H2, SiH2Cl2 (DCS), and HCl in each reaction also satisfy the following condition: the sixth flow rate = (equal to) the fifth flow rate = the fourth flow rate = the third flow rate = the second flow rate = the first flow rate.

[0052] Furthermore, the flow rates of the doping gas B₂H₆ must satisfy the following conditions: the sixth flow rate is less than the fifth flow rate, the fifth flow rate is less than the fourth flow rate, the fourth flow rate is less than the third flow rate, and so on, ..., the second flow rate is less than the first flow rate, so that the ion doping concentration in the pillar layers of each trench gradually decreases from bottom to top. Specifically, the ion doping concentration in the first sub-pillar layer 41 is greater than the ion doping concentration in the second sub-pillar layer 42, the ion doping concentration in the second sub-pillar layer 42 is greater than the ion doping concentration in the third sub-pillar layer 43, the ion doping concentration in the third sub-pillar layer 43 is greater than the ion doping concentration in the fourth sub-pillar layer 44, the ion doping concentration in the fourth sub-pillar layer 44 is greater than the ion doping concentration in the fifth sub-pillar layer 45, and the ion doping concentration in the fifth sub-pillar layer 45 is greater than the ion doping concentration in the sixth sub-pillar layer 46. It is worth noting that, from bottom to top, the ion doping concentration in the epitaxial layer 20 gradually decreases as the thickness increases, and similarly, the ion doping concentration in the combined pillar layers also gradually decreases as the thickness increases. In this embodiment, the ion doping concentration at different thicknesses in the combined pillar layer is matched with the ion doping concentration at different thicknesses in the epitaxial layer 20. This can also be understood as the ion doping concentration at different thicknesses in the combined pillar layer being adapted to the ion doping concentration at different thicknesses in the epitaxial layer 20.

[0053] In this embodiment, the reactant gases include: H2, SiH2Cl2 (DCS), HCl and B2H6, wherein the sixth flow rate of H2 is 10L~100L; the sixth flow rate of SiH2Cl2 (DCS) is 100sccm~5000sccm; the sixth flow rate of HCl is 100sccm~5000sccm; and the sixth flow rate of B2H6 is 10sccm~3000sccm.

[0054] Step S6: Continue to refer to Figure 7 The sixth sub-pillar layer 46, extending beyond the top of the trench 30 and the surface of the epitaxial layer 20, is removed by grinding.

[0055] After grinding removes the sixth sub-pillar layer 46 that extends beyond the top of the trench 30 and the surface of the epitaxial layer 20, the first sub-pillar layer 41, the second sub-pillar layer 42, the third sub-pillar layer 43, the fourth sub-pillar layer 44, the fifth sub-pillar layer 45, and the sixth sub-pillar layer 46 stacked in the trench form the final combined pillar layer.

[0056] This application obtains a first sub-pillar layer, a second sub-pillar layer, and an N+1th sub-pillar layer with progressively decreasing doping concentration from bottom to top by executing steps one through six. The first sub-pillar layer, the second sub-pillar layer, and the N+1th sub-pillar layer are combined to form a final combined pillar layer. This not only allows the ion doping concentration in the combined pillar layer in each trench to decrease layer by layer as the thickness of the combined pillar layer increases, thus matching the ion doping concentration at different thickness positions in the combined pillar layer with the ion doping concentration at different thickness positions in the epitaxial layer, but also simultaneously lowers the ion doping concentration of the pillar layer in different regions of the wafer surface. This avoids the situation in traditional deep trench filled superjunction products where the pillar layer concentration mismatch in different regions of the wafer surface leads to a low and discrete BV (breakdown voltage). This improves the imbalance of pillar layer concentration mismatch in different regions of the wafer surface, increases the overall BV (breakdown voltage) of the device, and balances the BV in different regions of the wafer surface.

[0057] Based on the same inventive concept, this application also provides a semiconductor device, see reference. Figure 7 The semiconductor device includes: A substrate 10 has an epitaxial layer 20 formed thereon, and a plurality of trenches 30 are formed in the epitaxial layer 20 in an array. As the thickness of the epitaxial layer 20 increases, the concentration of doped ions in the epitaxial layer 20 gradually decreases. The substrate 10 includes, from the center to the edge, a circular central region, an annular transition region, and an annular edge region. A composite pillar layer fills the trench. From bottom to top, the composite pillar layer includes stacked first sub-pillar layer 41, second sub-pillar layer 42 to N+1th sub-pillar layer. The ion doping concentration of the first sub-pillar layer 41 is greater than that of the second sub-pillar layer 42, the ion doping concentration of the second sub-pillar layer 42 is greater than that of the third sub-pillar layer 43, and so on, with the ion doping concentration of the Nth sub-pillar layer being greater than that of the N+1th sub-pillar layer.

[0058] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: First step: Provide a substrate on which an epitaxial layer is formed, and an array of trenches are formed in the epitaxial layer, wherein the concentration of doped ions in the epitaxial layer gradually decreases as the thickness of the epitaxial layer increases; the substrate, from the center to the edge, sequentially includes: a circular central region, an annular transition region, and an annular edge region; The second step is to introduce the reaction gas at a flow rate of i into the process chamber to form the i-th sub-pillar layer in the trench. The distribution ratio of the introduced reaction gas gradually increases from the center of the substrate to the edge of the substrate, so that the thickness of the i-th sub-pillar layer gradually increases from the center of the substrate to the edge of the substrate. The third step is to etch back a certain thickness of the i-th sub-pillar layer in the trench, wherein the etching rate of the i-th sub-pillar layer in the central region is less than the etching rate of the i-th sub-pillar layer in the transition region, and the etching rate of the i-th sub-pillar layer in the transition region is less than the etching rate of the i-th sub-pillar layer in the edge region. Fourth step: Repeat the second step to the third step for a total of N-1 times, with i increasing each time, until the upper surface of the Nth sub-pillar layer in the edge region of the second step is flush with or higher than the upper surface of the epitaxial layer, where N is an integer greater than or equal to 2, and the flow rate of the dopant gas in the reaction gas introduced in the later step is less than the flow rate of the dopant gas in the reaction gas introduced in the previous step. Fifth step: Introduce the reaction gas at a flow rate of N+1 into the process chamber to form the N+1 sub-pillar layer in the trench, wherein the flow rate of the doping gas in the reaction gas at the N+1 flow rate is less than the Nth flow rate, so that the ion doping concentration in each sub-pillar layer in each trench decreases layer by layer from bottom to top. Step 6: Grinding removes the N+1th sub-pillar layer that extends beyond the top of the trench and the surface of the epitaxial layer to obtain a combined pillar layer; Where i is the sequence number of the cyclic process, and its value is an integer from 1 to N.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The reacting gases include: H2, SiH2Cl2 (DCS), HCl and B2H6.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The number of gas pipelines that introduce the reaction gas into the process chamber is at least two.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The process chamber has two gas pipelines for introducing the reaction gas: one gas pipeline is located above the edge region, and the other gas pipeline is located above the center region.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, In the second step, a reaction gas with an i-th flow rate is introduced into the process chamber to form an i-th sub-pillar layer in the trench, wherein the gas distribution ratio in the central region is less than the gas distribution ratio in the edge region, so that the ion doping concentration in the i-th sub-pillar layer in the edge region is greater than the ion doping concentration in the i-th sub-pillar layer in the central region.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The gas distribution ratio of the central region = 1 - the gas distribution ratio of the edge region.

7. The method for fabricating a semiconductor device according to claim 3, characterized in that, The process chamber has three gas pipelines for introducing reaction gases. The first gas pipeline is located above the edge region, the second gas pipeline is located above the transition region, and the third gas pipeline is located above the central region.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, In the second step, a reaction gas with an i-th flow rate is introduced into the process chamber to form an i-th sub-pillar layer in the trench. The gas distribution ratio in the central region is less than that in the transition region, and the gas distribution ratio in the transition region is less than that in the edge region, so that the ion doping concentration in the i-th sub-pillar layer in the edge region is greater than that in the i-th sub-pillar layer in the transition region, and the ion doping concentration in the i-th sub-pillar layer in the transition region is greater than that in the i-th sub-pillar layer in the central region.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The gas distribution ratio of the central region = 1 - the gas distribution ratio of the edge region - the gas distribution ratio of the transition region.

10. The method for fabricating a semiconductor device according to claim 1, characterized in that, In the third step, the process parameters for re-etching the pillar layer include: process chamber pressure of 10 Torr~700 Torr; process chamber temperature of 900℃~1150℃; and the gas involved in the re-etching includes HCl, wherein the flow rate of HCl is 100 slm~10000 slm, wherein, from the center of the substrate to the edge of the substrate, the flow rate of HCl in the edge region is greater than the flow rate of HCl in the transition region, and the flow rate of HCl in the transition region is greater than the flow rate of HCl in the center region, and / or the temperature of the edge region is greater than the temperature of the transition region, and the temperature of the transition region is greater than the temperature of the center region.

11. A semiconductor device, fabricated using the method for fabricating a semiconductor device as described in any one of claims 1 to 10, characterized in that, include: A substrate on which an epitaxial layer is formed, wherein an array of trenches is formed in the epitaxial layer, wherein the concentration of doped ions in the epitaxial layer gradually decreases as the thickness of the epitaxial layer increases; the substrate, from the center to the edge, sequentially includes: a circular central region, an annular transition region, and an annular edge region. A composite pillar layer fills the trench. From bottom to top, the composite pillar layer includes stacked first sub-pillar layers, second sub-pillar layers to N+1th sub-pillar layers. The ion doping concentration of the first sub-pillar layer is greater than that of the second sub-pillar layer, the ion doping concentration of the second sub-pillar layer is greater than that of the third sub-pillar layer, and so on, with the ion doping concentration of the Nth sub-pillar layer being greater than that of the N+1th sub-pillar layer, where N is an integer greater than or equal to 2.

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