Method for manufacturing a semiconductor device

Abstract

Embodiments provide a method for manufacturing a semiconductor device capable of improving the processability of an indium-containing compound film. In the method for manufacturing a semiconductor device of an embodiment, an electrode layer (22) is formed on an indium-containing compound film (24X) formed over a substrate, a mask layer is formed over the electrode layer (22), after the mask layer is processed, the electrode layer (22) is etched until at least a part of the compound film (24X) is exposed, thereafter a spacer film (26) is formed so as to cover the upper surface of the mask layer, the side surface of the mask layer and the electrode layer (22), and the upper surface of the compound film (24X), the spacer film (26) located on the upper surface of the mask layer and the upper surface of the compound film (24X) is etched, the exposed compound film (24X) is subjected to reduction treatment using plasma of a reducing gas, and the compound film (24Y) subjected to the reduction treatment is etched using a chemical liquid.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-47602 (filed on March 23, 2022). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a method for manufacturing a semiconductor device. Background Technology

[0004] When dry etching or wet etching is performed on compound films such as indium (In) oxide films, problems may arise such as the generation of processing residues or the adhesion of non-volatile products into the chamber, or the film processing itself may become more difficult. Summary of the Invention

[0005] The present invention provides a method for manufacturing a semiconductor device that can improve the processability of indium-containing compound films.

[0006] In the semiconductor device manufacturing method of the embodiment, an electrode layer is formed on an indium-containing compound film formed on a substrate, a mask layer is formed on the electrode layer, the mask layer is processed, the electrode layer is etched until at least a portion of the compound film is exposed, a spacer film is then formed to cover the upper surface of the mask layer, the side surfaces of the mask layer and the electrode layer, and the upper surface of the compound film, the spacer film located on the upper surface of the mask layer and the upper surface of the compound film is etched, the exposed compound film is reduced using plasma of a reducing gas, and the reduced compound film is etched using a chemical solution. Attached Figure Description

[0007] Figures 1(A) to 1(C) This is a diagram showing the processing steps of the indium-containing compound film according to the first embodiment.

[0008] Figure 2 This is a cross-sectional view showing a semiconductor device manufactured using the manufacturing method of the second embodiment.

[0009] Figure 3 It is along Figure 2 A cross-sectional view along line AA.

[0010] Figures 4(A) and 4(B) are cross-sectional views showing the first example of the manufacturing steps of the semiconductor device according to the second embodiment.

[0011] Figures 5(A) and 5(B) are cross-sectional views showing the first example of the manufacturing steps of the semiconductor device according to the second embodiment.

[0012] Figure 6 These are cross-sectional views showing variations of the semiconductor devices shown in Figures 5(A) and 5(B).

[0013] Figures 7(A) and 7(B) are cross-sectional views showing a second example of the manufacturing steps of the semiconductor device according to the second embodiment.

[0014] Figures 8(A) and 8(B) are cross-sectional views showing a second example of the manufacturing steps of the semiconductor device according to the second embodiment.

[0015] Figure 9 This is a partial cross-sectional view of a variation of the semiconductor device according to the second embodiment.

[0016] Figures 10(A) to 10(D) This is a cross-sectional view showing a third example of the manufacturing steps of the semiconductor device according to the second embodiment. Detailed Implementation

[0017] Hereinafter, with reference to the accompanying drawings, the processing method of the compound film and the manufacturing method of the semiconductor device according to the embodiments will be described. Furthermore, in each embodiment, substantially identical components are given the same reference numerals, and sometimes partial descriptions are omitted. The accompanying drawings are for illustrative purposes, and the relationship between thickness and planar dimensions, as well as the thickness ratios of various parts, may sometimes differ from reality.

[0018] (First Embodiment)

[0019] Figures 1(A) to 1(C) This describes the processing steps for an indium (In) compound film. First, as shown in Figure 1(A), an indium-containing compound film 2 is formed on a substrate 1 using, for example, PVD (Physical Vapor Deposition). The substrate 1 is appropriately selected depending on the intended use of the indium-containing compound film 2; for example, a conductive substrate such as a semiconductor substrate or a metal substrate, or an insulating substrate such as a ceramic substrate, may be used. These substrates can be used directly as the substrate 1, or substrates with various functional layers such as conductive layers, insulating layers, and semiconductor layers can be used as the substrate 1, and the compound film 2 can be formed on these functional layers.

[0020] Examples of indium-containing compounds constituting compound film 2 include nonmetallic or semimetallic elements from Group 15, Group 16, and Group 17, such as oxygen (O), phosphorus (P), boron (B), carbon (C), nitrogen (N), silicon (Si), sulfur (S), selenium (Se), tellurium (Te), fluorine (F), chlorine (Cl), bromine (Br), or iodine (I), in combination with indium. Specific examples of such compounds include indium oxide (InO), indium phosphide (InP), indium nitride (InN), indium arsenide (InAs), and indium selenide (InSe), and the indium-containing compound may contain at least one of these compounds. However, the indium-containing compound may also contain metallic elements other than indium, such as tin (Sn), gallium (Ga), aluminum (Al), and zinc (Zn).

[0021] Indium-containing compounds, such as indium oxides or indium phosphides, sometimes function as semiconductors or conductors. Examples of indium oxides include indium tin oxide (ITO), indium gallium zinc oxide (In-Ga-Zn Oxide, IGZO), indium aluminum zinc oxide (In-Al-Zn Oxide, IAZO), and indium oxide (InO).

[0022] Indium-containing oxides with a high proportion of indium oxides such as ITO present the following challenges: they exhibit high resistance to acidic or alkaline solutions used in wet etching, and consequently, they are prone to producing processing residues or non-volatile substances when subjected to halogenated gases (such as HBr or Cl2) or organic gases (such as CH4, CH3OH, CF4, CHF3, etc.) used in dry etching. Therefore, it is difficult to achieve high-efficiency etching without producing processing residues with indium-containing oxides. Thus, processing methods such as the etching method described in the embodiments are necessary. Furthermore, since processing becomes more difficult when indium-containing oxides crystallize, the processing methods described in the embodiments are particularly effective when the indium-containing oxide or other compound being processed contains crystalline portions.

[0023] Next, the indium-containing compound film 2 is reduced using plasma with a reducing gas. Examples of reducing gases used in the plasma treatment include gases containing hydrogen atoms (H). Such reducing gases include at least one gas selected from the group consisting of H2 (hydrogen), NH3 (ammonia), H2S (hydrogen sulfide), and H2O (water vapor). As shown below, gases containing H2 (hydrogen), NH3 (ammonia), H2S (hydrogen sulfide), and H2O (water vapor) can all be used in the reduction treatment of the indium-containing compound film 2. In addition to these gases, HF (hydrogen fluoride), HCl (hydrogen HCl), HBr (hydrogen bromide), HI (hydrogen iodide), CH4 (methane), CHF3 (trifluoromethane), CH2F2 (difluoromethane), CH3F (fluoromethane), etc., can also be used.

[0024] In the process using plasma with reducing gas, a substrate 1 having an indium-containing compound film 2 is first placed in the chamber of a plasma processing apparatus. By introducing a reducing gas into this chamber and applying a high-frequency voltage to electrodes disposed within the chamber, a plasma of reducing gas is generated within the chamber. The indium-containing compound film 2 is then processed using this plasma. If the indium-containing compound film 2 is exposed to the plasma of reducing gas, as shown in Figure 1(B), the compound film 2, such as an oxide film, is reduced, generating nanoparticles (indium-containing metal nanoparticles) 3 containing indium, or indium and metals (such as Sn) coexisting with indium. This allows the indium-containing compound film 2 to be transformed into a metal film 4 deposited with the metal nanoparticles 3. This type of indium-containing metal film 4 exhibits superior processability compared to indium-containing oxide films or other compound films 2. Therefore, it is possible to process the indium-containing metal film 4 using etching solutions or similar solvents with high efficiency, and processing residues can be suppressed.

[0025] Next, the indium-containing metal film 4 is treated with a chemical solution. Examples of the chemical solutions used to treat the indium-containing metal film 4 include: an aqueous solution of hydrochloric acid (HCl) at a concentration of 0.5% to 40% by mass, an aqueous solution of hydrofluoric acid (HF) at a concentration of 0.01% to 50% by mass, a mixture of hydrochloric acid (HCl) at a concentration of 30% or more by mass and nitric acid (HNO3) at a concentration of 70% or less by mass, and a mixed solution prepared by diluting such a mixture with water (H2O) at a concentration of 10% by volume or more. By treating the indium-containing metal film 4 with the acid solution, the indium-containing metal film 4 can be etched away as shown in FIG1(C). At this time, since the compound film 2 containing crystallized indium oxides, etc., is etched along the grain boundaries, it is easy to generate particulate residues. In contrast, in the indium-containing metal film 4, since the metal nanoparticles 3 themselves are easily etched by the acid solution, the indium-containing metal film 4 can be etched away without generating processing residues. Furthermore, depending on the type of indium-containing metal film 4, alkaline solutions or the like can also be used as the treatment solution. The treatment solution used for the treatment shown in Figure 1(C) is appropriately selected according to the treatment content.

[0026] (Second Implementation)

[0027] Figure 2 This is a cross-sectional view of the semiconductor device according to the second embodiment. Figure 3 It is along Figure 2 The cross-sectional view of line AA. In Figures 4(A) and 4(B), the up and down direction is designated as the first direction, and the two directions orthogonal to the first direction are designated as the second and third directions.

[0028] Figure 2 and Figure 3 The semiconductor device 10 shown is a transistor with an oxide semiconductor as the channel layer. The transistor 10 is a so-called SGT (Surrounding Gate Transistor) arranged such that the gate electrode surrounds the channel layer, and it is a vertical transistor.

[0029] Transistor 10 includes a channel layer 11 comprising an oxide semiconductor, a gate electrode 12, a gate insulating layer 13, a source electrode 14, a drain electrode 15, a first interlayer insulating layer 16, a second interlayer insulating layer 17, and a third interlayer insulating layer 18. The channel layer 11 includes, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn); zinc (Zn); and oxygen (O). The channel layer 11 includes, for example, indium (In), gallium (Ga), and zinc (Zn). The channel layer 11 includes, for example, indium (In), aluminum (Al), and zinc (Zn). The source electrode 14 has a first electrode layer 19, a first barrier layer 20, and a first oxide conductor layer 21. The drain electrode 15 has a second electrode layer 22, a second barrier layer 23, and a second oxide conductor layer 24.

[0030] The electrode layers 19 and 22 of the source electrode 14 and drain electrode 15 are made of tungsten (W), W alloy, molybdenum (Mo), Mo alloy, etc. The barrier layers 20 and 23 are made of titanium nitride (TiN) or tantalum nitride (TaN), etc. An oxide conductor layer 21 is disposed between the channel layer 11 and the electrode layer 19, and an oxide conductor layer 24 is disposed between the channel layer 11 and the electrode layer 22. Furthermore, a barrier layer 20 is disposed between the oxide conductor layer 21 and the electrode layer 19, and a barrier layer 23 is disposed between the oxide conductor layer 24 and the electrode layer 22. The oxide conductor layers 21 and 24 are, for example, formed of the same material. The first oxide conductor layer 21 and the second oxide conductor layer 24 are, for example, oxide conductors containing indium (In), tin (Sn), and oxygen (O). The first oxide conductor layer 21 and the second oxide conductor layer 24 are, for example, indium tin oxide.

[0031] A channel layer 11 is disposed between the source electrode 14 and the drain electrode 5. A channel is formed in the channel layer 11, which becomes a current path when the transistor 10 is turned on. The channel layer 11 has a cylindrical shape extending in a first direction. The width of the channel layer 11 in a second direction is, for example, 20 nm to 50 nm. The gate length (width in the first direction) of the gate electrode 12 is, for example, 20 nm to 100 nm. The gate electrode 12 is disposed in a manner surrounding the channel layer 11. The gate electrode 12 is disposed around the channel layer 11 with a gate insulating layer 13 in between.

[0032] A gate insulating layer 13 is disposed between the channel layer 11 and the gate electrode 12. The gate insulating layer 13 is disposed in a manner that surrounds the channel layer 11. The gate insulating layer 13 may contain, for example, oxide or oxynitride. The gate insulating layer 14 may be, for example, silicon oxide, silicon nitride, or aluminum oxide. The thickness of the gate insulating layer 14 may be, for example, 2 nm or more and 10 nm or less.

[0033] Interlayer insulating layers 16, 17, and 18 are disposed, for example, between the source electrode 14 and the gate electrode 12, between the drain electrode 15 and the gate electrode 12, and around the gate electrode 12. Interlayer insulating layers 16, 17, and 18 provide electrical separation between the source electrode 14, the drain electrode 15, and the gate electrode 12. Interlayer insulating layers 16, 17, and 18 may contain oxides, for example, silicon oxide.

[0034] Referring to Figures 4(A), 4(B), 5(A), and 5(B), the manufacturing steps of the oxide semiconductor transistor 10 will be described. First, as shown in Figure 4(A), a structure 25 having a source electrode 14, a channel layer 11, a gate insulating layer 13, and a gate electrode 12 is formed based on a known manufacturing method for vertical transistors (SGT). On this structure 25, an ITO film 24X serving as a second oxide conductor layer 24, a TiN film 23X serving as a second barrier layer 23, and a W film 22X serving as a second electrode layer 22 are sequentially formed in connection with the channel layer 11.

[0035] Next, as shown in FIG4(B), the TiN film 23X and W film 22X are etched by dry etching such as reactive ion etching (RIE) to form a barrier layer 23 and an electrode layer 22. Then, using the barrier layer 23 and electrode layer 22 as masks, the portion of the ITO film 24X exposed from these masks is exposed to a plasma containing at least one reducing gas, such as H2, NH3, H2S, or H2O, similar to the steps shown in FIG1(B). As a result, as shown in FIG5(A), the portion of the ITO film 24X exposed from the masks is modified into a modified film 24Y deposited with In-Sn nanoparticles.

[0036] Next, the portion of the ITO film 24X that has deteriorated into a deteriorated film 24Y is treated using an acidic solution such as a 20% HCl aqueous solution, and the deteriorated film 24Y is etched away as shown in FIG. 5(B). This forms a second oxide conductive layer 24 that not only has the desired shape but is also connected to the channel layer 11. By applying a combination of reduction treatment based on plasma such as H2 and wet etching to the ITO film 24X, the ITO film 24X can be etched without generating processing residue. Therefore, the transistor 10 can be processed into the desired shape. Furthermore, when the ITO film 24X is treated only by dry etching, problems such as mask end depression or indium dust adhering to the chamber of the processing device occur because the RIE for etching ITO requires high energy. The ITO treatment of this embodiment can suppress these problems. Furthermore, the etching shown in FIG. 5(B), as... Figure 6As shown, the cross-sectional area of ​​the second oxide conductor layer 24 can also be smaller than the cross-sectional area of ​​the second barrier layer 23 or the second electrode layer 22.

[0037] When applying the combined process of reduction treatment using plasma based on reducing gas and wet etching, side etching of the ITO film 24X sometimes occurs. Here, side etching of the ITO film 24X refers to a situation where the length of the ITO film 24X in the second or third direction is shorter than the lengths of the TiN film 23X and the W film 22X in the second or third direction. To address this, it is more effective to form a spacer film 26 on the side of the stacked film of the second barrier layer 23 and the second electrode layer 22, as shown in Figures 7(A) and 7(B). This ensures a margin for side etching equivalent to the thickness of the spacer film 26, thus suppressing side etching of the ITO film 24X.

[0038] First, as shown in FIG7(A), a spacer film 26 is formed such that it covers the side and top surfaces of the stacked film of the second barrier layer 23 and the second electrode layer 22, as well as the surface of the ITO film 24X exposed from the stacked film. The spacer film 26 is, for example, made of silicon oxide or silicon nitride, or an organic material. The thickness of the spacer film 26 is preferably set to be greater than or equal to the thickness of the ITO film 24X. Next, as shown in FIG7(B), the spacer film 26 located on the second electrode layer 22 and the ITO film 24X is etched away such that the spacer film 26 present on the side surfaces of the stacked film of the second barrier layer 23 and the second electrode layer 22 is retained.

[0039] Next, similar to the steps shown in FIG5(B), the exposed portion of the ITO film 24X is exposed to a plasma containing at least one reducing gas, such as H2, NH3, H2S, or H2O, thereby transforming the exposed portion of the ITO film 24X from the mask into a modified film 24Y deposited with In-Sn nanoparticles, as shown in FIG8(A). Next, the portion of the ITO film 24X transformed into the modified film 24Y is treated with an acid solution such as a 20% aqueous HCl solution, thereby etching away the modified film 24Y, as shown in FIG8(B). Thus, an oxide conductive layer 24 with the desired shape is formed. In the plasma treatment step shown in FIG8(A) and the etching step shown in FIG8(B), a thickness margin equivalent to the spacer film 26 can be ensured, thus suppressing side etching of the ITO film 24X.

[0040] In the transistor 10 employing the manufacturing steps shown in Figures 7(A), 7(B), 8(A), and 8(B), the spacer film 26 existing on the sides of the stacked film between the second barrier layer 23 and the second electrode layer 22 can be used as a sidewall. At this time, as shown in Figures 7(A) and 7(B), the sidewalls relative to the sides of the stacked film between the second barrier layer 23 and the second electrode layer 22 can also be formed after exposing the ITO film 24X to a plasma of reducing gas, instead of forming the sidewalls before exposing the ITO film 24X to the plasma of reducing gas. If NH3 plasma is used in the plasma treatment of the ITO film 24X, then in addition to remodeling the ITO film 24X into a modified film 24Y, the sides of the stacked film between the second barrier layer 23 and the second electrode layer 22 can be exposed to NH3 plasma for surface treatment.

[0041] By treating the sidewalls of the second electrode layer 22, which includes a W film, with NH3 plasma, a W nitride (WN) is formed on the sidewalls of the W film. When silicon nitride (SiN) is used as the sidewall, the adhesion between the WN and SiN formed on the sidewalls of the W film is improved. Therefore, the adhesion of the sidewalls formed on the sidewalls of the second electrode layer 22 can be improved, thereby enhancing the quality of the transistor 10.

[0042] In addition, such as Figure 9 As shown, the junction surface between the second oxide conductor layer 24 and the channel layer 11 can be made larger than the junction surface between the second oxide conductor layer 24 and the second barrier layer 23 by tilting the end of the second oxide conductor layer 24. In other words, the lower surface of the second oxide conductor layer 24 can also be larger than the upper surface of the second oxide conductor layer 24. By forming this shape, it is easier to electrically connect the drain electrode 15 to the channel layer 11. Ideally, the lower surface of the second oxide conductor layer 24 should be larger than the upper surface of the channel layer 11. Alternatively, the cross-sectional shape of the second oxide conductor layer 24 can be formed such that the width of the lower end is greater than the width of the upper end (a two-segment shape), instead of tilting the end of the second oxide conductor layer 24. When a second oxide conductor layer 24 with this shape is formed, the combined treatment of reduction processing based on reducing gas plasma and wet etching can still be effectively applied to the second oxide conductor layer 24.

[0043] Reference Figures 10(A) to 10(D) The steps for forming the oxide semiconductor layer 24, which has two segments, are described below. Figures 10(A) to 10(D)This indicates the processing state of the oxide conductor layer 24 (ITO film 24X) existing between adjacent channel layers 11A, 11B and electrode layers 22A, 22B. First, as shown in FIG10(A), the exposed portion of the ITO film 24X is processed by using plasma containing at least one reducing gas, such as H2, NH3, H2S, H2O, etc., thereby transforming the portion of the ITO film 24X exposed from the mask into a modified film 24Y. At this time, by adjusting the processing conditions of the plasma based on the reducing gas, the modified region of the modified film 24Y is made shallower than the thickness of the ITO film 24X, that is, the modified region of the modified film 24Y is set to be a portion in the surface to thickness direction.

[0044] Next, as shown in Figure 10(B), the modified region of the modified film 24Y is etched by treating it with an acid solution such as a 20% HCl aqueous solution. At this point, since the modified region of the modified film 24Y is set to be shallower than the thickness of the ITO film 24X, only a portion of the ITO film 24X is etched in the thickness direction, thus forming a shallower recess H. Next, as shown in Figure 10(C), the portion of the ITO film 24X remaining after the etching step shown in Figure 10(B) is treated with a plasma of reducing gas, thereby modifying a portion of the remaining portion of the ITO film 24X into the modified film 24Y. Although not shown in Figure 10(C), by setting a mask or the like, the width of the modified region (the region where the modified film 24Y is formed) formed by the plasma is made narrower than the width between the adjacent channel layers 11A and 11B.

[0045] Subsequently, as shown in FIG10(D), the modified region (the region where the modified film 24Y is formed) formed by plasma is etched by treating it with an acid solution such as a 20% HCl aqueous solution. By performing this two-stage plasma treatment and etching process, a second oxide conductor layer 24 with a cross-sectional shape in which the width at the lower end is wider than the width at the upper end (two-section shape) can be obtained. Therefore, even if a positional shift occurs, the channel layer 11 and the second oxide conductor layer 24 can still be easily electrically connected. In addition, a spacer film 26 can be formed before FIG10(A) or before the plasma treatment in FIG10(C).

[0046] Furthermore, the configurations of the various embodiments can be combined and applied separately, or a portion of them can be replaced. Several embodiments of the present invention have been described here, but these embodiments are merely examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0047] [Symbol Explanation]

[0048] 1 Substrate

[0049] 2 Indium-containing compound films

[0050] 3 Metal nanoparticles

[0051] 10 transistors

[0052] 11-channel layer

[0053] 12 gate electrodes

[0054] 13 gate insulating layer

[0055] 14 source electrodes

[0056] 15 Drain electrode

[0057] 19,22 electrode layers

[0058] 22XW membrane

[0059] 20,23 barrier layers

[0060] 23XTiN film

[0061] 21,24 oxide conductor layer

[0062] 24XI TO membrane

[0063] 24Y deteriorated membrane.

Claims

1. A method for manufacturing a semiconductor device, An electrode layer is formed on an indium-containing compound film formed on a substrate. A mask layer is formed on top of the electrode layer. After processing the mask layer, the electrode layer is etched until at least a portion of the compound film is exposed. A spacer film is formed in such a manner that it covers the upper surface of the mask layer, the sides of the mask layer and the electrode layer, and the upper surface of the compound film. The spacer film located on the upper surface of the mask layer and the upper surface of the compound film is etched. The exposed compound film was subjected to reduction treatment using plasma with a reducing gas. The compound film that has undergone the reduction treatment is etched using a chemical solution.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the reducing gas comprises at least one selected from the group consisting of H2, NH3, H2S, and H2O.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the compound film comprises an oxide conductor.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the compound film contains a compound of indium and at least one element selected from the group consisting of nonmetallic and semimetallic elements selected from Group 15, Group 16 and Group 17.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the compound contains at least one selected from the group consisting of oxygen, phosphorus, boron, carbon, nitrogen, silicon, sulfur, selenium, tellurium, fluorine, chlorine, bromine, and iodine.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the compound film contains at least one selected from the group consisting of indium tin oxide, indium gallium zinc oxide, indium oxide, and indium aluminum zinc oxide.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the compound film has a crystallized portion.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the solution is acidic.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the compound film is degraded by the reduction treatment.

10. The method of manufacturing a semiconductor device according to claim 1, wherein the lower surface of the compound film after etching with the solution is larger than the upper surface of the compound film.

11. A method for manufacturing a semiconductor device, An electrode layer is formed on an indium-containing compound film formed on a substrate. A mask layer is formed on top of the electrode layer. After processing the mask layer, the electrode layer is etched until at least a portion of the compound film is exposed. The compound film and the electrode layer are subjected to reduction treatment using plasma with a reducing gas. A spacer film is formed in such a manner that it covers the upper surface of the mask layer, the sides of the mask layer and the electrode layer, and the upper surface of the compound film. The spacer film located on the upper surface of the mask layer and the upper surface of the compound film is etched. The compound film that has undergone the reduction treatment is etched using a chemical solution.

12. The method of manufacturing a semiconductor device according to claim 11, wherein the compound film is degraded by the reduction treatment to form a nitride on the side surface of the electrode layer. The spacer film is formed on the nitride.

13. The method of manufacturing a semiconductor device according to claim 12, wherein the electrode layer comprises tungsten, and tungsten nitride is formed on the side of the electrode layer by the reduction treatment.

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