A method of manufacturing a semiconductor device and a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. A first field effect transistor is formed on a substrate, a first isolation layer is formed on the first field effect transistor, a first through hole is formed in the first isolation layer, and a metal layer is deposited in the first through hole. The metal layer can be used as a power distribution supply network, and the metal layer is electrically connected with the first field effect transistor. Thus, the metal layer can supply power to the first field effect transistor. Then, a second isolation layer is formed on the first isolation layer and the metal layer, and a second field effect transistor is formed on the second isolation layer. The second field effect transistor and the second isolation layer have a second through hole penetrating therethrough. The second through hole is filled with a metal material to form a first contact plug. The first contact plug is electrically connected with the metal layer, and the metal layer can supply power to the second field effect transistor. The device size is reduced, the integration density of the semiconductor device is improved, the process flow steps are reduced, and the process difficulty is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] With the continuous development of integrated circuit manufacturing process nodes and key technologies, nanosheet gate-all-around field-effect transistors (NS GAAFETs) will replace existing fin field-effect transistors (FinFETs) at 3nm and below. Furthermore, the next generation of three-dimensional stacked field-effect transistors (3DSFETs) will become the main technology route after the 1nm node.

[0003] Currently, there are two main types of process methods for realizing 3DS FETs: sequential integration and self-aligned simultaneous integration. The former is simple and offers flexibility in material and process selection, but is limited by performance and cost. The latter offers high integration density and superior performance, but its integration method is complex and faces various process technology challenges.

[0004] Furthermore, the development of Backside Power Distribution Network (BS-PDN) technology, which involves moving the traditional backend-of-line (BEOL) power distribution network to the back side of the wafer using appropriate processes, is gaining increasing attention. Compared to frontside power distribution network (FS-PDN), semiconductor devices manufactured using BS-PDN technology exhibit higher integration density and lower interconnect voltage drop losses. How to combine the fabrication of 3DS FET devices and PDN to create novel semiconductor devices that improve integration density has become an urgent problem to be solved. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a method for manufacturing a semiconductor device and a semiconductor device in general, which improves the integration density of the semiconductor device, reduces the number of process steps, and lowers the process difficulty. The specific solution is as follows:

[0006] In a first aspect, this application provides a method for manufacturing a semiconductor device, comprising:

[0007] A first field-effect transistor and a first isolation layer are formed sequentially on the substrate;

[0008] A first via is formed in the first isolation layer, and a metal layer is deposited in the first via; the metal layer is electrically connected to the first field-effect transistor;

[0009] A second isolation layer is formed on the first isolation layer and the metal layer;

[0010] A second field-effect transistor is formed on the second isolation layer; the second field-effect transistor and the second isolation layer have a second through hole, and the second through hole is filled with a metal material to form a first contact plug, and the first contact plug is electrically connected to the metal layer.

[0011] Specifically, the step of forming a first field-effect transistor and a first isolation layer sequentially stacked on the substrate includes:

[0012] A stacked layer of alternating first and second semiconductor layers is formed on the substrate;

[0013] The stacked layers and a portion of the substrate are etched to form fins, and a dummy gate, a first sidewall, and a mask layer are formed on the fins;

[0014] Using the first sidewall as a shield, the stacked layer is etched, and the first semiconductor layer is etched from the outside to the inside, forming a second sidewall at both ends of the first semiconductor layer;

[0015] A source / drain region is formed around the stacked layer, and a third isolation layer is formed on the source / drain region;

[0016] Remove the dummy gate and the first semiconductor layer, and use the second semiconductor layer as a channel to form a gate surrounding the channel;

[0017] A third through-hole is formed in the third isolation layer, and a metal material is deposited in the third through-hole to form a second contact plug; the second contact plug is electrically connected to the metal layer.

[0018] Specifically, before forming the second isolation layer on the first isolation layer and the metal layer, the method further includes:

[0019] The metal layer is planarized until it is flush with the surface of the first insulating layer.

[0020] Specifically, the material of the metal layer includes at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag.

[0021] Specifically, the thickness or width of the metal layer is greater than or equal to 1 nm and less than or equal to 10,000 nm.

[0022] Specifically, the metal layer is a single-layer or multi-layer structure.

[0023] Specifically, the first field-effect transistor and the second field-effect transistor are nanosheet ring gate field-effect transistors.

[0024] Secondly, embodiments of this application also provide a semiconductor device, including:

[0025] A first field-effect transistor, a first isolation layer, a second isolation layer, and a second field-effect transistor are sequentially stacked on a substrate; the first isolation layer has a metal layer, which is electrically connected to the first field-effect transistor; the second field-effect transistor includes a first contact plug, which is electrically connected to the metal layer.

[0026] Specifically, the material of the metal layer includes at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag.

[0027] Specifically, the thickness or width of the metal layer is greater than or equal to 1 nm and less than or equal to 10,000 nm.

[0028] This application provides a method for manufacturing a semiconductor device and the semiconductor device itself. A first field-effect transistor (FET) is formed on a substrate, and a first isolation layer is formed on the FET. A first via is formed in the first isolation layer, and a metal layer is deposited in the first via. The metal layer can serve as a power distribution network (PDN) for supplying power to the FET. The metal layer is electrically connected to the FET, thus enabling the metal layer to supply power to the FET. Since the FET and the power distribution network are located on the same side of the substrate, an FS-PDN structure for the FET can be formed. Then, a semiconductor device is formed on the first isolation layer and the metal layer. A second isolation layer is formed, and a second field-effect transistor is formed on the second isolation layer. The second field-effect transistor and the second isolation layer have a through-hole. The through-hole is filled with metal material to form a first contact plug. The first contact plug is electrically connected to the metal layer. In this way, the metal layer can supply power to the second field-effect transistor, which can form a BS-PDN structure of the second field-effect transistor. The BS-PDN structure occupies less space and can reduce the device size. In addition, the first field-effect transistor and the second field-effect transistor can share the same metal layer for power supply, which improves the integration density of semiconductor devices, eliminates the need to thin the substrate, reduces process steps, and lowers the process difficulty. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0032] Figure 3 A schematic diagram of the overall structure of a first field-effect transistor provided in an embodiment of this application;

[0033] Figure 4 A cross-sectional view of a semiconductor device in the XX direction provided for an embodiment of this application;

[0034] Figure 5 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0035] Figure 6 A cross-sectional view of a semiconductor device in the YY direction provided for an embodiment of this application;

[0036] Figure 7 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0037] Figure 8 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0038] Figure 9 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0039] Figure 10 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0040] Figure 11 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0041] Figure 12 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0042] Figure 13A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0043] Figure 14 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0044] Figure 15 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0045] Figure 16 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0046] Figure 17 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0047] Figure 18 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0048] Figure 19 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0049] Figure 20 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0050] Figure 21 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0051] Figure 22 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0052] Figure 23 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0053] Figure 24 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0054] Figure 25 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0055] Figure 26 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0056] Figure 27 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0057] Figure 28 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction;

[0058] Figure 29 A cross-sectional view of another semiconductor device provided in the embodiment of this application in the YY direction;

[0059] Figure 30 This is a cross-sectional view of another semiconductor device provided in the embodiment of this application in the XX direction. Detailed Implementation

[0060] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0061] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0062] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0063] For ease of understanding, the following detailed description, in conjunction with the accompanying drawings, provides a method for manufacturing a semiconductor device and the semiconductor device itself, according to embodiments of this application.

[0064] refer to Figure 1 The diagram shown is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. The method includes the following steps.

[0065] S101, a first field-effect transistor and a first isolation layer are formed sequentially on a substrate.

[0066] In the embodiments of this application, a substrate can be provided, which can be Si or SiGe. A bulk silicon Si substrate can be used and then doped. Specifically, a highly doped well region is formed in the bulk silicon substrate by implanting impurities, diffusion, and annealing to achieve the required well depth. For a P-type FET, the highly doped well region is an N-well, and the implanted impurity is an n-type impurity ion, such as phosphorus (P) ions. For an N-type FET, the highly doped well region is a p-well, and the implanted impurity is a p-type impurity ion, such as boron (B) ions.

[0067] For ease of explanation, the direction from the substrate to the first field-effect transistor can be called "up" and the direction from the first field-effect transistor to the substrate can be called "down". However, this labeling is for convenience and is unrelated to the direction of gravity.

[0068] Specifically, a first field-effect transistor can be formed on the substrate. The first field-effect transistor can be a nanosheet-ring field-effect transistor or other types of field-effect transistors, without specific limitations. Next, a first isolation layer can be formed on the surface of the first field-effect transistor to isolate the first field-effect transistor from the second field-effect transistor.

[0069] Specifically, the semiconductor device provided in this application can be a three-dimensional stacked field-effect transistor (3DS FET) or a vertical field-effect transistor (VFET). The 3DS FET can specifically be a complementary field-effect transistor (CFET), or of course, other types of field-effect transistors. (Reference) Figure 2 The diagram shown is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application, which has a first field-effect transistor 10 and a first isolation layer 20 on a substrate 100.

[0070] S102, a first through-hole is formed in the first isolation layer, and a metal layer is deposited in the first through-hole.

[0071] In this embodiment, a via can be formed in the first isolation layer 20, referred to as the first via. The first via can penetrate the first isolation layer 20. The shape of the first via is not specifically limited here. For example, the first via may include a first part and a second part. The first part may be located on the surface of the first isolation layer 20, and the second part may penetrate the first isolation layer 20. The lateral dimension of the first part may be larger than the lateral dimension of the second part. The first part and the second part are connected. The first part can be used to form a power distribution supply network, and the second part can be used to connect the first part to the first field-effect transistor.

[0072] Specifically, a metal layer 30 can be deposited in the first via. The metal layer 30 can serve as a power distribution network and can be electrically connected to the first field-effect transistor 10, so that the power distribution network can supply power to the first field-effect transistor 10. The first field-effect transistor 10 and the power distribution network are both located on the same side of the substrate 100, which can form an FS-PDN structure of the first field-effect transistor.

[0073] In one possible implementation, the material of the metal layer 30 may include at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag, which enables the metal layer to withstand high temperatures and has low resistivity, making it suitable for large currents to pass through.

[0074] In one possible implementation, the thickness of the metal layer 30 can be greater than or equal to 1 nm and less than or equal to 10,000 nm, and the width of the metal layer 30 can also be greater than or equal to 1 nm and less than or equal to 10,000 nm. Those skilled in the art can choose according to the actual situation.

[0075] In one possible implementation, depending on the specific circuit design, the metal layer 30 can be a single-layer or multi-layer structure. When the metal layer 30 is a multi-layer structure, the interconnection between the multi-layers can be selected according to the actual situation.

[0076] S103, a second isolation layer is formed on the first isolation layer and the metal layer.

[0077] In this embodiment, a second isolation layer 40 can be formed on the first isolation layer 20 and the metal layer 30. The material of the second isolation layer 40 can be the same as or different from the material of the first isolation layer 20. The second isolation layer 40 can isolate the metal layer 30 and the second field-effect transistor 60. After the second isolation layer 40 is formed, chemical-mechanical planarization (CMP) can be performed to make the second isolation layer 40 flatter.

[0078] In one possible implementation, before forming the second isolation layer 40 on the first isolation layer 20 and the metal layer 30, the metal layer 30 can be planarized until the metal layer 30 is flush with the surface of the first isolation layer 20, thereby improving device performance.

[0079] S104 forms the second field-effect transistor on the second isolation layer.

[0080] In this embodiment, a second field-effect transistor 60 can be formed on the second isolation layer 40. The fabrication process of the second field-effect transistor 60 can refer to the fabrication process of the first field-effect transistor 10. The channel material of the second field-effect transistor 60 can be the same as or different from the channel material of the first field-effect transistor 10. The second field-effect transistor 60 can also be a gate-all-around field-effect transistor or other types of field-effect transistors.

[0081] Specifically, a via, referred to as the second via, can be formed in the second field-effect transistor 60 and the second isolation layer 40. The second via can be filled with metal material to form a first contact plug 50. The first contact plug 50 can be electrically connected to the metal layer 30. In this way, the metal layer 30 can also supply power to the second field-effect transistor 60, forming a BS-PDN structure for the second field-effect transistor. The BS-PDN structure occupies less space, which can reduce the device size and improve the integration density of the semiconductor device. In addition, the first field-effect transistor 10 and the second field-effect transistor 60 can share the same metal layer 30 for power supply, eliminating the need to set a separate metal layer 30 for power supply for each field-effect transistor, reducing the number of metal layers and improving the integration density of the semiconductor device.

[0082] This application uses a sequential integration method to fabricate semiconductor devices, which allows for more flexible material and process selection. Furthermore, in the traditional BS-PDN structure fabrication process, due to the relatively thick wafer thickness of several hundred micrometers, it is necessary to thin the wafer (to about one or two dozen micrometers) to fabricate the BS-PDN structure. However, in this application, a buried metal layer 30 is formed in the isolation layer between the upper and lower field-effect transistors to form a power distribution supply network. The combined thickness of the first isolation layer 20 and the second isolation layer 40 is relatively small, at several micrometers or nanometers, eliminating the need for thinning operations, reducing process steps, and lowering the process difficulty.

[0083] In the embodiments of this application, the formation of the first field-effect transistor 10 and the first isolation layer 20 stacked sequentially on the substrate 100 can be briefly described using the first field-effect transistor 10 as an example of a nanosheet ring gate field-effect transistor.

[0084] refer to Figure 3 This is a schematic diagram of the overall structure of a first field-effect transistor provided in an embodiment of this application, in which two directions are defined and two dashed lines, XX and YY, are set. The following figures are all cross-sectional schematic diagrams with the two lines XX and YY.

[0085] Specifically, a stacked layer of alternating first and second semiconductor layers can be epitaxially grown on a substrate, as shown in the reference. Figure 4 The image shown is a cross-sectional view of a semiconductor device provided in an embodiment of this application in the XX direction. At this time, the cross-sectional view in the YY direction is the same as the cross-sectional view in the XX direction.

[0086] Specifically, the materials of the first semiconductor layer 101 and the second semiconductor layer 102 can be set according to actual needs. The first semiconductor layer 101 can be a germanium-based film layer, which can include an epitaxial germanium layer, an epitaxial silicon-germanium layer, or a combination thereof. The second semiconductor layer 102 can be an epitaxial silicon layer. For example, the first semiconductor layer / second semiconductor layer stack is SiGe / Si, and SiGe / Si periodic superlattice epitaxial growth is performed. The epitaxial process can be vacuum epitaxy or molecular beam epitaxy, etc.

[0087] Next, fins can be formed by etching the stacked layers and a portion of the substrate. In the actual process, this can be referenced... Figure 5 and Figure 6 As shown, Figure 5 This is a cross-sectional view of another semiconductor device provided in an embodiment of this application in the XX direction. The cross-sectional view in the YY direction is as follows: Figure 6 As shown, a sacrificial layer 103 is deposited on the stacked layers. The sacrificial layer 103 can be polycrystalline silicon (p-si) or amorphous silicon (a-si). Part of the sacrificial layer is etched away, and the third sidewall 104 is deposited. The material can be silicon nitride (SiN). x ) or silicon dioxide.

[0088] Anisotropic etching is then used to etch away the remaining sacrificial layer 103, leaving only the third sidewall 104 on the stacked layer. The third sidewall 104 acts as a hard mask in photolithography. Then, using the third sidewall 104 as a mask, etching is performed to form a fin from the epitaxially grown stacked layer, creating a fin with a stacked layer structure. Finally, the third sidewall 104 is removed, forming a fin like... Figure 7 and Figure 8 The fin shown is a conductive channel region formed by stacked layers at the top and a substrate 100 at the bottom. This means the fin includes not only the stacked layer structures 101 / 102 but also a single-crystal silicon structure extending into the substrate. The etching process can be dry or wet etching, such as reactive ion etching (RIE). The fin will be used to form horizontal nanosheets for n-type and / or p-type field-effect transistors.

[0089] In this embodiment, a shallow trench isolation (STI) region 105 can be formed around the fin to separate adjacent transistors. A cross-sectional view in the YY direction is shown below. Figure 9 As shown, the cross-sectional view in the XX direction is as follows. Figure 7As shown, first, a dielectric insulating material is deposited, then planarized, for example using a CMP process, followed by selective etching back of the dielectric insulating material to expose a three-dimensional fin structure, forming a shallow trench isolation region 105. The upper surface of the shallow trench isolation region 105 is generally flush with the interface between the stacked layer structure in the fin and the substrate monocrystalline silicon, but may be higher or lower than this interface level. The shallow trench isolation region 105 can be formed of a suitable dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SiN). x )wait.

[0090] In this embodiment, a dummy gate 107, a first sidewall 109, and a mask layer 108 can be formed on the fin, as shown in the reference. Figure 10 and Figure 11 As shown. Specifically, the dummy gate 107 can span the stacked layers above the fin, and the material used for the dummy gate 107 can be polysilicon (p-si) or amorphous silicon (a-si). A mask layer 108 can be formed above the dummy gate 107, and first sidewalls 109 can be formed on both sides of the dummy gate 107. The first sidewalls 109 can be silicon nitride (SiN). x The thickness of the first sidewall 109 on both sides can be the same, and the height of the first sidewall 109 can be greater than the height of the dummy gate 107 to avoid excessive etching. It is understood that before forming the dummy gate 107, a gate dielectric layer 106 spanning the fin can be formed. The material of the gate dielectric layer 106 can be the same as or different from the material of the shallow trench isolation region 105.

[0091] In this embodiment, the stacked layers can be etched from the outside in using the first sidewall 109 as a mask, retaining only the dummy gate 107 and the stacked layers below the first sidewall 109. Next, partial areas at both ends of the first semiconductor layer 101 are etched from the outside in, forming second sidewalls 116 at both ends of the first semiconductor layer 101. A cross-sectional view in the XX direction is referenced. Figure 12 As shown, the cross-sectional view in the YY direction is as follows. Figure 11 As shown. Specifically, pull-back etching can be performed to etch away a portion of the first semiconductor layer 101 from the outside to the center, so that a second sidewall 116 can be formed in the area of ​​the etched first semiconductor layer 101. The second sidewall 116 can be silicon nitride, etc.

[0092] When depositing the second sidewall 116 on the outer periphery of the fin, the second sidewall 116 can be etched until it is flush with the second semiconductor layer 102 in the vertical direction, that is, the second sidewall 116 is formed at both ends of the first semiconductor layer 101.

[0093] In this embodiment, source / drain regions can be epitaxially formed and doped. For PMOS, the source / drain region material is boron (B)-doped SiGe (SiGe:B), and for NMOS, the source / drain region material is phosphorus (P)-doped silicon (Si) (Si:P), ultimately forming the first source / drain region 110. A cross-sectional view in the XX direction is shown below. Figure 13 As shown, the cross-sectional view in the YY direction is as follows. Figure 11 As shown.

[0094] Next, a third isolation layer (ILD) 111 is deposited on the upper surface of the first source / drain region 110, as shown in Figure 14. Figure 15 As shown, to prevent short circuits between the dummy gate layer 107 and the first source / drain region 110 in subsequent steps, the third isolation layer 111 is chemically and mechanically polished to planarize it.

[0095] Then, as Figure 16 and Figure 17 As shown, by selective etching or etching processes, the dummy gate layer 107 formed of polysilicon (p-si) or amorphous silicon (a-si) and the gate dielectric layer 106 formed of the dummy gate dielectric are etched or etched away, that is, the dummy gate 107 and the gate dielectric layer 106 are removed. Then, the nanosheet channel is released, that is, the first semiconductor layer 101 is removed and the second semiconductor layer 102 is released, and the second semiconductor layer 102 is used as the channel.

[0096] Next, a first gate 113 is formed to surround the channel, as referenced. Figure 18 and 19 As shown, specifically, a first interface oxide layer (IL) 112, a high-k dielectric layer and a first gate 113 can be formed. The function of the first interface oxide layer is to improve the interface characteristics between the high-k dielectric layer and the channel.

[0097] refer to Figure 20 and Figure 21 As shown, a fourth isolation layer 115 can be deposited, covering the third isolation layer 111 and the first gate 113. Next, a third via can be formed in the third isolation layer 111 and the fourth isolation layer 115. Then, metal material is deposited in the third via to form a second contact plug 114. One end of the second contact plug 114 can be connected to the first source / drain region 110, and the other end can be electrically connected to the metal layer 30, thereby achieving the connection between the metal layer 30 and the first source / drain region. In this way, the fabrication of the first field-effect transistor 10 can be completed.

[0098] In this embodiment, a first isolation layer 20 can be deposited and formed above the nanosheet ring gate field-effect transistor, as referenced. Figure 22 and Figure 23As shown, next, a hole can be drilled in the first isolation layer 20 to obtain a first through hole, and then a metal layer 30 can be formed in the first through hole, as shown in the reference. Figure 24 and Figure 25 As shown. Metal layer 30 serves as the PDN structure. The first field-effect transistor is interconnected with the PDN via a BEOL via, allowing power to be supplied to the underlying first field-effect transistor 10. Next, a second isolation layer 40 can be deposited to form. (Refer to...) Figure 26 and Figure 27 The material of the second isolation layer 40 can be the same as that of the first isolation layer 20. Then, another nanosheet ring gate field-effect transistor is formed above the second isolation layer 40 as the second field-effect transistor 60. (Refer to...) Figure 28 and Figure 29 As shown.

[0099] Specifically, the second field-effect transistor 60 may include a third semiconductor layer 602 as a channel, a fourth sidewall 609, a fifth sidewall 616, a second source / drain region 610, a second interface layer 612, a second gate 613, a fifth isolation layer 611, a sixth isolation layer 615, and a third contact plug 614. After forming these structures, the sixth isolation layer 615 and the fifth isolation layer 611 can be etched to form vias to connect the second source / drain region 610. Simultaneously, the sixth isolation layer 615, the fifth isolation layer 611, the second source / drain region 610, and the second isolation layer 40 can be etched to form through-silicon vias (TSVs). Metal material is deposited in the TSVs to form the first contact plug 50. In other words, the second field-effect transistor 60 and the PDN are interconnected via TSVs. The cross-sectional view of the formed structure in the XX direction is shown below. Figure 30 As shown, the cross-sectional view in the YY direction is as follows: Figure 29 As shown, this allows for the extraction of either the source or drain electrode, and also enables the metal layer 30 to supply power to the second field-effect transistor 60, improving device integration and reducing process steps. Through-silicon vias (TSVs) can be formed using laser etching or deep reactive ion etching, and these TSVs can be filled with polysilicon, copper, tungsten, or polymer conductors. Metal materials can be filled using methods such as electroplating, chemical vapor deposition, or polymer coating.

[0100] This application provides a method for manufacturing a semiconductor device. A first field-effect transistor (FET) is formed on a substrate, and a first isolation layer is formed on the first FET. A first via is formed in the first isolation layer, and a metal layer is deposited in the first via. The metal layer can serve as a power distribution network (PDN) for supplying power to the FET. The metal layer is electrically connected to the first FET, thus enabling the metal layer to supply power to the first FET. Since the first FET and the power distribution network are located on the same side of the substrate, an FS-PDN structure for the first FET can be formed. Then, a second... An isolation layer is formed on which a second field-effect transistor (FET) is formed. The second FET and the second isolation layer have a through-hole. The through-hole is filled with a metal material to form a first contact plug. The first contact plug is electrically connected to the metal layer. In this way, the metal layer can supply power to the second FET, which can form a BS-PDN structure for the second FET. The BS-PDN structure occupies less space, which can reduce the device size. In addition, the first FET and the second FET can share the same metal layer for power supply, which can improve the integration density of semiconductor devices, eliminate the need to thin the substrate, reduce process steps, and reduce process difficulty.

[0101] Based on the semiconductor device manufacturing method provided in the above embodiments, this application also provides a semiconductor device, see reference. Figure 2 As shown.

[0102] In this embodiment of the application, the semiconductor device may include a first field-effect transistor 10, a first isolation layer 20, a second isolation layer 40 and a second field-effect transistor 60 stacked sequentially on a substrate 100. The first isolation layer 20 has a metal layer 30, which is electrically connected to the first field-effect transistor 10. The second field-effect transistor 60 includes a first contact plug 50, which is electrically connected to the metal layer 30.

[0103] Specifically, the first field-effect transistor 10 and the second field-effect transistor 60 can be nanosheet-ring gate field-effect transistors, such as... Figure 30 As shown, other types of transistors can also be used, and no specific limitation is made here.

[0104] Specifically, the material of the metal layer includes at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag.

[0105] Specifically, the thickness or width of the metal layer is greater than or equal to 1 nm and less than or equal to 10,000 nm.

[0106] This application provides a semiconductor device including a first field-effect transistor (FET), a first isolation layer, a second isolation layer, and a second FET stacked sequentially on a substrate. The first isolation layer has a metal layer electrically connected to the first FET. The second FET includes a first contact plug electrically connected to the metal layer. The metal layer can serve as a power distribution network for supplying power to the FET. Since the first FET and the power distribution network are located on the same side of the substrate, an FS-PDN structure for the first FET can be formed. The metal layer can also supply power to the second FET, forming a BS-PDN structure. The BS-PDN structure occupies less space, reducing device size. Furthermore, the first and second FETs can share the same metal layer for power supply, increasing the integration density of the semiconductor device, eliminating the need for substrate thinning, reducing process steps, and lowering process complexity.

[0107] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0108] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A first field-effect transistor and a first isolation layer are formed sequentially on a substrate; A first via is formed in the first isolation layer, and a metal layer is deposited in the first via; the metal layer is electrically connected to the first field-effect transistor; the first via includes a first part and a second part connected together, the first part is located on the surface of the first isolation layer, the second part penetrates the first isolation layer, the lateral dimension of the first part is larger than the lateral dimension of the second part, the first part is used to form a power distribution supply network, and the second part is used to connect the first part to the first field-effect transistor. A second isolation layer is formed on the first isolation layer and the metal layer; A second field-effect transistor is formed on the second isolation layer; the second field-effect transistor includes a second source / drain region, a fifth isolation layer, and a sixth isolation layer; after forming the second field-effect transistor, the sixth isolation layer, the fifth isolation layer, the second source / drain region, and the second isolation layer are etched to form a second via; the second via is filled with a metal material to form a first contact plug, and the first contact plug is electrically connected to the metal layer.

2. The method according to claim 1, characterized in that, The formation of a first field-effect transistor and a first isolation layer sequentially stacked on the substrate includes: A stacked layer of alternating first and second semiconductor layers is formed on the substrate; The stacked layers and a portion of the substrate are etched to form fins, and a dummy gate, a first sidewall, and a mask layer are formed on the fins; Using the first sidewall as a shield, the stacked layer is etched, and the first semiconductor layer is etched from the outside to the inside, forming a second sidewall at both ends of the first semiconductor layer; A source / drain region is formed around the stacked layer, and a third isolation layer is formed on the source / drain region; Remove the dummy gate and the first semiconductor layer, and use the second semiconductor layer as a channel to form a gate surrounding the channel; A third through-hole is formed in the third isolation layer, and a metal material is deposited in the third through-hole to form a second contact plug; the second contact plug is electrically connected to the metal layer.

3. The method according to claim 1, characterized in that, Before forming a second isolation layer on the first isolation layer and the metal layer, the method further includes: The metal layer is planarized until it is flush with the surface of the first insulating layer.

4. The method according to any one of claims 1-3, characterized in that, The material of the metal layer includes at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag.

5. The method according to any one of claims 1-3, characterized in that, The thickness or width of the metal layer is greater than or equal to 1 nm and less than or equal to 10,000 nm.

6. The method according to any one of claims 1-3, characterized in that, The metal layer can be a single layer or multiple layers.

7. The method according to any one of claims 1-3, characterized in that, The first field-effect transistor and the second field-effect transistor are nanosheet ring gate field-effect transistors.

8. A semiconductor device, characterized in that, include: A first field-effect transistor, a first isolation layer, a second isolation layer, and a second field-effect transistor are sequentially stacked on a substrate; a first via includes a first portion and a second portion connected together, the first portion being located on the surface of the first isolation layer, the second portion penetrating the first isolation layer, the lateral dimension of the first portion being larger than the lateral dimension of the second portion, the first portion being used to form a power distribution supply network, and the second portion being used to connect the first portion to the first field-effect transistor. The second field-effect transistor includes a second source / drain region, a fifth isolation layer, and a sixth isolation layer; the second via is formed by etching the sixth isolation layer, the fifth isolation layer, the second source / drain region, and the second isolation layer after the second field-effect transistor is formed. The first isolation layer has a metal layer that is electrically connected to the first field-effect transistor, and the second field-effect transistor includes a first contact plug that is electrically connected to the metal layer.

9. The semiconductor device according to claim 8, characterized in that, The material of the metal layer includes at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag.

10. The semiconductor device according to claim 8, characterized in that, The thickness or width of the metal layer is greater than or equal to 1 nm and less than or equal to 10,000 nm.

Images