Package structure based on active silicon interposer and manufacturing method thereof

Abstract

The application provides a packaging structure based on an active silicon interposer and a manufacturing method thereof, and is applied to the technical field of packaging structures based on active silicon interlayers. The packaging structure based on the active silicon interlayer comprises: a packaging carrier comprising a first pad array; an active silicon interlayer located above the packaging carrier, and the active silicon interlayer comprising a second pad array and a third pad array; a first metal lead line for connecting the second pad array and the first pad array; and a chip module located above the active silicon interlayer, the chip module comprising at least one chip, the chip comprising a fourth pad array, pads in the fourth pad array and pads in the third pad array being arranged according to the same pad layout, and the fourth pad array and the third pad array being connected through first bumps. The TSV process is avoided, process defects are reduced, manufacturing difficulty and cost are reduced, and packaging yield is improved. The reuse of the active silicon interlayer is realized, and the cost of the active silicon interlayer is further reduced.

Description

Technical Field

[0001] This invention relates to the field of packaging structure technology based on active silicon interposers, and more particularly to a packaging structure based on active silicon interposers and its fabrication method. Background Technology

[0002] In the field of active silicon interposer (OSI) based packaging technology, an OSI layer can be placed between the packaging substrate and the die. The OSI layer is used to connect the die's external signals to the packaging substrate. In traditional OSI-based packaging systems, the die's external signals are connected to the packaging substrate via through-silicon vias (TSVs) on the OSI layer, and then connected to an external interface via the packaging substrate. However, TSVs are difficult and costly to manufacture. Furthermore, TSV manufacturing may introduce process defects, which increases the failure risk of OSI-based packaging systems and reduces their reliability. Summary of the Invention

[0003] In view of the above, it is necessary to provide a packaging structure based on an active silicon interposer and its fabrication method to solve the above problems.

[0004] In a first aspect, this application provides a packaging structure based on an active silicon interposer, comprising: a packaging carrier including a first pad array; an active silicon interposer located above the packaging carrier, and the active silicon interposer including a second pad array and a third pad array; a first metal lead for connecting the second pad array and the first pad array; and a chip module located above the active silicon interposer, the chip module including at least one chip, the chip including a fourth pad array, the pads in the fourth pad array and the third pad array being arranged according to the same pad layout plan, and the fourth pad array and the third pad array being connected by a first bump.

[0005] In a preferred embodiment, the active silicon interposer includes a first surface and a second surface opposite to each other, the first surface corresponding to the chip module and the second surface corresponding to the packaging carrier; a second pad array and a third pad array are located on the first surface, with the second pad array located around the first surface and the third pad array being enclosed within the second pad array.

[0006] In a preferred embodiment, the third pad array includes at least one standard pad array configured according to a pad layout plan, and the fourth pad array includes at least one standard pad array configured according to a pad layout plan. The standard pad array includes pads in a first functional area and pads in a second functional area. The pads in the first functional area include one or more of the following: a first power pad, a first ground pad, a system clock pad, a system reset pad, and a programmable direct-connect pad. The pads in the second functional area include one or more of the following: a data strobe pad, a channel reset pad, a data transmission pad, a second power pad, and a second ground pad.

[0007] In a preferred embodiment, when the number of standard pad arrays in the third pad array is greater than or equal to 2, the third pad array has at least one pair of rotationally symmetric standard pad arrays.

[0008] In a preferred embodiment, when the number of standard pad arrays in the third pad array is greater than or equal to 2, the third pad array further includes a fifth pad array arranged among the standard pad arrays, the fifth pad array including a first power pad and a first ground pad.

[0009] In a preferred embodiment, the first metal lead is a bonding lead, and the first bump is a microbump, which is integrally formed with the pads in the fourth pad array. The first bump includes, but is not limited to, microbumps, copper bumps (consisting of a copper pillar with a solder cap), and bumpless Cu-Cu hybrid bonding, wherein the bumpless hybrid bonding uses copper-copper direct bonding technology that does not require microbumps.

[0010] In a preferred embodiment, there is a preset interval between the pads in the second pad array and the pads in the third pad array.

[0011] In a preferred embodiment, the spacing between the pads in the third pad array is the same as the spacing between the pads in the fourth pad array, and the functionally corresponding pads in the third and fourth pad arrays are connected by a first bump.

[0012] In a preferred embodiment, the packaging carrier includes any one of a packaging substrate, a packaging shell, or a printed circuit board.

[0013] In a preferred embodiment, the encapsulation carrier may be a passive interposer or an active interposer.

[0014] Secondly, this application provides a method for fabricating a package structure based on an active silicon interposer. The method includes: providing a package carrier and forming a first pad array on the package carrier; providing an active silicon interposer and forming a second pad array on a first surface of the active silicon interposer, and forming a third pad array on the first surface according to a pad layout plan; providing a chip module, the chip module including at least one chip, and forming a fourth pad array on the chip according to a pad layout plan; connecting the fourth pad array and the third pad array through a first bump; placing a second surface of the active silicon interposer on the package carrier and connecting the second pad array and the first pad array through a first metal lead, wherein the second surface is opposite to the first surface.

[0015] The packaging structure and manufacturing method based on an active silicon interposer provided in this application embodiment connect the active silicon interposer and the chip via a first bump to provide higher communication bandwidth, reduce communication latency, and ensure high-performance interconnection between chips. The active silicon interposer and the packaging carrier are connected via a first metal lead, avoiding the use of TSV (Through Silicon Via) technology. This avoids process defects introduced by the through-silicon via (TSV) manufacturing process, reduces the failure risk of the active silicon interposer-based packaging structure, improves its reliability, reduces the manufacturing difficulty and cost of the active silicon interposer, and increases packaging yield. Furthermore, the pads of both the active silicon interposer and the chip can be planned and set according to the same pad layout, allowing the active silicon interposer to support electrical interconnection for various different chips, enabling reuse of the active silicon interposer and avoiding the need for dedicated active silicon interposers for different chip designs, thus reducing the cost of the active silicon interposer. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the packaging structure based on an active silicon interposer provided in an embodiment of this application.

[0017] Figure 2A for Figure 1 The packaging carrier in the packaging structure is the packaging substrate.

[0018] Figure 2B for Figure 1 The encapsulation carrier in the encapsulation structure is a structural diagram of the encapsulation tube shell.

[0019] Figure 3 This is a schematic diagram of the pad layout of a standard pad array provided in an embodiment of this application.

[0020] Figure 4 This is a schematic diagram illustrating the interface function between the chip and the active silicon interposer provided in an embodiment of this application.

[0021] Figure 5 This is a schematic diagram of the pad layout of the chip provided in an embodiment of this application.

[0022] Figure 6 This is a schematic diagram of the pad layout of the active silicon interposer provided in an embodiment of this application.

[0023] Figure 7 This is a schematic diagram of another pad layout for the active silicon interposer provided in an embodiment of this application.

[0024] Figure 8 for Figure 7 The diagram shows the connection between the active silicon interposer and the chip.

[0025] Figure 9 for Figure 7 Another schematic diagram showing the connection between the active silicon interposer and the chip.

[0026] Figure 10 This is a schematic diagram of the process for fabricating a packaging structure based on an active silicon interposer, as provided in an embodiment of this application.

[0027] Explanation of main component symbols

[0028] Packaging structure based on active silicon interposer 100

[0029] Packaging carrier 10

[0030] Active silicon interposer 20

[0031] Chip Module 30

[0032] Chip 1, 2

[0033] First metal lead 40

[0034] First pad array 1

[0035] upper surface 12

[0036] lower surface 13

[0037] First surface 201

[0038] Second surface 202

[0039] Second pad array 21

[0040] Third pad array 22

[0041] The fourth pad array consists of pads 31, 31a, 31b, 801, 802, 803, 804, 901, and 902.

[0042] Wire bonding pads 111, 211

[0043] Bump pads 221, 311, 311a, 311b

[0044] First protrusion 32

[0045] Packaging substrate 101

[0046] C4 bump array 14

[0047] C4 bump 141

[0048] Encapsulation housing 102

[0049] Cover plate 103

[0050] Functional areas 310, 320a, 320b

[0051] Second functional areas 320, 310a, 310b

[0052] First data path area 301

[0053] Second data path area 302

[0054] Third data path area 303

[0055] Fourth data path area 304

[0056] Data transmission microbump pads 401a, 401b

[0057] First power supply microbump pads 402a, 402b

[0058] First grounding microbump pads 403a, 403b

[0059] System clock microbump pads 404a, 404b

[0060] System reset microbump pads 405a, 405b

[0061] Surface 1a of the active silicon interposer corresponding to the chip

[0062] Standard pad arrays 300, 601, 602, 603, 604, 701, 702, 703, 704.

[0063] Fifth pad array 605, 705

[0064] Socket 23

[0065] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0066] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0067] Based on the embodiments described in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0068] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0069] Based on the embodiments described in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0070] In the field of chip packaging technology, a silicon interposer can be used to connect a packaging substrate and a bare die (or chip). A silicon interposer is a type of chip based on silicon technology. The silicon interposer is used to connect the external signals of the bare die to the packaging substrate. When two or more bare dies are placed on a silicon interposer, the silicon interposer is also used to realize the electrical interconnection between the two or more bare dies, enabling data transmission between the two or more bare dies.

[0071] Silicon interposers include active silicon interposers and passive silicon interposers. Passive silicon interposers achieve electrical interconnection between dies via interconnects. As a passive structure, passive silicon interposers lack control functions and therefore cannot autonomously handle faults; their reliability depends on the reliability of the package substrate and the dies. Active silicon interposers include active devices such as transistors, voltage regulators, and networks. Therefore, active silicon interposers can autonomously handle faults and have higher reliability. In addition to achieving electrical interconnection between dies via interconnects, active silicon interposers can also achieve high-performance interconnection (i.e., high-bandwidth and low-latency data transmission) with dies through their internal networks. Active silicon interposers can implement common circuit functions of system-on-a-chip (SoC), such as power supply, data interconnect networks, and system input / output functions. Therefore, active silicon interposers are commonly used to achieve high-performance interconnection between dies.

[0072] Silicon interposer technology typically employs Through Silicon Via (TSV) technology, a packaging technique used to package different chips together. It involves creating through-holes that penetrate the substrate and are filled with conductive material, then stacking multiple chips or wafers together to achieve electrical interconnection between them. TSVs allow for maximum chip density in three dimensions, minimize overall size, and significantly improve chip speed and low-power performance. Specifically, a TSV is a vertical via created on a chip (such as a silicon interposer) using etching, laser, or other techniques. The via is then filled with conductive materials such as copper, tungsten, or polysilicon to achieve vertical electrical interconnection, thereby enabling electrical interconnection between the die and the packaging substrate.

[0073] In a silicon interposer packaging system, dies are flip-chip packaged onto a silicon interposer, which is then soldered to a package substrate via C4 bumps (Controlled Collapse Chip Connection bumps) on its back side. Electrical interconnections between dies are achieved through interconnects or active devices on the silicon interposer. External signals from the dies are connected to the package substrate via vias and C4 bumps on the silicon interposer, and then connected to external interfaces via the package substrate.

[0074] When using active silicon interposers (TSVs) for chip packaging, the cost of TSVs is relatively high, and multiple dedicated TSVs are often required for different dies, increasing the overall cost of the packaging system. Traditional active silicon interposers require through-silicon vias (TSVs) to achieve vertical connections between upper and lower layers (such as the die and the packaging substrate). However, TSVs are difficult and expensive to manufacture. Furthermore, TSV manufacturing may introduce process defects, increasing the failure risk of the packaging system and reducing its reliability. The manufacturing process of TSVs can also introduce stress into the active silicon region near the via opening, interfering with normal circuit operation. Therefore, the area surrounding the TSV is designated as a "keep-out zone" (KOZ), where active circuits cannot be inserted. The area of ​​the keep-out zone is significant, and when multiple TSVs are placed on the chip, it creates a large number of discontinuous unusable areas, severely impacting chip layout utilization and causing difficulties in chip placement and routing design.

[0075] In view of this, this application provides a packaging structure based on an active silicon interposer and its fabrication method. This packaging structure supports high-speed internal operation and low-speed external operation; that is, it uses high-speed interfaces for electrical interconnection between chips and low-speed interfaces for electrical interconnection between chips and external components. Specifically, the active silicon interposer is connected to the chip via a first bump to provide higher communication bandwidth, reduce communication latency, and ensure high-performance interconnection between chips. The active silicon interposer is connected to the packaging carrier via a first metal lead, avoiding the use of TSV (Through Silicon Via) technology. This avoids process defects introduced by the through-silicon via (TSV) manufacturing process, reduces the failure risk of the chip packaging structure, improves the reliability of the chip packaging structure, reduces the manufacturing difficulty and cost of the active silicon interposer, and improves the packaging yield. It also avoids the chip layout utilization problem caused by the "forbidden area" of the TSV occupying the active area of ​​the active interposer. Furthermore, since both the active silicon interposer and the chip's pads can be configured according to the same pad layout plan, the active silicon interposer can support electrical interconnection for multiple different chips, as well as electrical interconnection for multiple chips of the same type. This enables the reuse of the active silicon interposer, avoiding the need for dedicated active silicon interposers for different chip designs and reducing the cost of the active silicon interposer.

[0076] Figure 1 This application provides an exemplary embodiment of the packaging structure based on an active silicon interposer.

[0077] like Figure 1 As shown, the packaging structure 100 based on an active silicon interposer (EPS) includes a packaging carrier 10, an active EPS 20, and a chip module 30. The active EPS 20 is located above the packaging carrier 10, and the chip module 30 is located above the active EPS 20. That is, the active EPS 20 is located between the packaging carrier 10 and the chip module 30, connecting the packaging carrier 10 and the chip module 30 through the active EPS 20, thus achieving electrical connection between the packaging carrier 10 and the chip module 30. It also allows for the integration of chips (such as...) within the chip module 30. Figure 1 The electrical connection of chip 1 and chip 2 shown.

[0078] The packaging carrier 10 includes a first pad array 11 for connection to the active silicon interposer 20. The first pad array 11 includes wire bonding pads 111. The wire bonding pads 111 are made of metal. In some embodiments, the wire bonding pads 111 may be made of multiple layers of metal, such as five layers of electroplated Au, Ni, Cu, Ni, and Au stacked sequentially at the bottom. This application does not specifically limit this embodiment.

[0079] Specifically, the first pad array 11 is disposed on the upper surface 12 of the packaging carrier 10, and the upper surface 12 corresponds to the active silicon interposer 20, that is, the active silicon interposer 20 is placed on the upper surface 12.

[0080] In some embodiments, such as Figure 2A As shown, the packaging carrier 10 may further include a C4 bump array 14, which includes C4 bumps 141. The C4 bump array 14 is disposed on the lower surface 13 opposite to the upper surface 12, and is used for connection to an external interface.

[0081] In some embodiments, such as Figure 2B As shown, the packaging structure 100 based on the active silicon interposer may also include a cover plate 103, which enables molding packaging and protects the packaging structure 100 based on the active silicon interposer, such as protecting the active silicon interposer 20, the chip module 30, and the first metal lead 40.

[0082] The packaging carrier 10 can be implemented as a packaging substrate, packaging shell, printed circuit board (PCB), etc., and this application does not make specific limitations in this regard.

[0083] The following example description Figure 1 The encapsulation carriers 10 in the text represent different application scenarios for each carrier.

[0084] Figure 2A and Figure 1 The difference is that, Figure 2A China and Israel Figure 1 Taking the packaging carrier 10 as an example, which is implemented as a packaging substrate 101, a C4 bump array 14 is provided on the lower surface 13 of the packaging substrate 101, and a first pad array 11 is provided on the upper surface 12 of the packaging substrate 101. The C4 bumps 141 in the C4 bump array 14 are connected to the wire bonding pads 111 in the first pad array 11. Figure 2B and Figure 1 The difference is that, Figure 2B Taking the packaging carrier 10 as an example, the packaging shell 102 is provided around the packaging shell 102. The active silicon interposer 20, the chip module 30 and the first metal lead 40 are all placed in the cavity of the packaging shell 102. The cover plate 103 is hermetically connected to the packaging shell 102 to protect the active silicon interposer, the chip module 30 and the first metal lead 40.

[0085] When the packaging carrier 10 is a circuit board or a packaging shell 102, the first pad array 11 located on the circuit board or packaging shell 102 is directly connected to the external interface, and the C4 bump array 14 does not need to be deployed on the circuit board or packaging shell 102.

[0086] The active silicon interposer 20 includes a first surface 201 and a second surface 202. The second surface 202 corresponds to the packaging carrier 10, that is, the second surface 202 is adhered to the packaging carrier 10 and is in contact with the upper surface 12 of the packaging carrier 10. The first surface 201 corresponds to the chip module 30, that is, the chip module 30 is adhered to the first surface 201.

[0087] The active silicon interposer 20 includes a second pad array 21 and a third pad array 22. The second pad array 21 and the third pad array 22 are disposed on a first surface 201. The second pad array 21 is used for connection to the package carrier 10 and includes wire bonding pads 211. The third pad array 22 is used for connection to the chip module 30 and includes bump pads 221.

[0088] The details of the wire bonding pad 211 in the second pad array 21 can be found in the wire bonding pad 111 mentioned above. The wire bonding pad 211 and the wire bonding pad 111 are used to achieve wire bonding. The only difference is that the pads are set on different carriers, which will not be elaborated here.

[0089] The bump pad 221 is used to connect bumps, which can be any of the following: C4 bumps (Controlled Collapse Chip Connection), C2 bumps (Chip Connection), and bumpless Cu-Cu hybrid bonding. C4 bumps are a controlled collapse chip connection process; a typical example of a C4 bump is a solder ball bump, with a pitch ranging from 50 μm to 150 μm. C2 bumps can also be called microbumps. A typical example of a C2 bump is a copper pillar bump, with a structure of a micro-copper pillar + solder cap (cu-pillar + solder cap). The pitch of the copper pillar bumps can be 50 μm, with a minimum of 25 μm. Bumpless Cu-Cu hybrid bonding, also known as hybrid bonding, has a pitch range of 1–10 μm.

[0090] Based on the diameter of the bumps connected to the bump pads, the bump pads 221 can be divided into: C4 bump pads, C2 bump pads, and hybrid bonding pads. Among them, C4 bump pads connect to C4 bumps, C2 bump pads connect to C2 bumps, and hybrid bonding pads use hybrid bonding.

[0091] This application does not impose specific limitations on the spacing, material, or implementation process of the bumps connected to the bump pads.

[0092] The package structure 100 based on an active silicon interposer also includes a first metal lead 40, which is used to connect the first pad array 11 and the second pad array 21. The first metal lead 40 is a metal lead used to achieve wire bonding. Specifically, the wire bonding pads 211 in the second pad array 21 and the wire bonding pads 111 in the first pad array 11 are electrically connected through the first metal lead 40, that is, the electrical connection is achieved through wire bonding. Wire bonding is a method that uses metal leads and utilizes heat, pressure, and ultrasonic energy to tightly bond the metal leads to the wire bonding pads.

[0093] Chip module 30 includes at least one chip. Each chip includes a fourth pad array 31, which includes bump pads 311. Details regarding bump pads 311 in the fourth pad array 31 can be found in the description of bump pads 221 above. The only difference between bump pads 311 and bump pads 221 is that the pads are mounted on different carriers; this will not be elaborated upon further here. When chip module 30 includes two or more chips, each chip includes its corresponding fourth pad array. For example... Figure 1 As shown in Figure 2, taking the chip module 30 as an example, which includes two chips, chip 1 includes its corresponding fourth pad array 31a, which includes bump pads 311a, and chip 2 includes its corresponding fourth pad array 31b, which includes bump pads 311b.

[0094] In some embodiments, the chips in chip module 30 can be of different types, each capable of performing different functions. These different types of chips include, but are not limited to, logic chips, memory chips, and dummy dies. The multiple chips in chip module 30 can have different sizes, different bandwidth requirements, different power pin counts, etc. Figure 1 Chips 1 and 2 in Figure 2 are logic chips with different functions, or one is a logic chip and the other is a memory chip. When the sizes of chip 1 and chip 2 are different, the sizes or the number of pads of the fourth pad array 31a and the fourth pad array 31b can be different accordingly.

[0095] It should be noted that, Figure 1 The number of chips shown in Figure 2 is merely an example. This application does not limit the number of chips in the chip module 30, nor does it limit the type of chips.

[0096] The bump pads 311 in the fourth pad array 31 have the same bump size as the bump pads 221 in the third pad array 22. The bump pads 311 in the fourth pad array 31 are micro-bump pads, and correspondingly, the bump pads 221 in the third pad array 22 connected to the fourth pad array 31 are also micro-bump pads. The spacing of the bump pads 311 in the fourth pad array 31 is the same as the spacing of the bump pads 221 in the third pad array 22. For example, if the spacing of the micro-bump pads in the fourth pad array 31 is 50 μm, the spacing of the micro-bump pads in the third pad array 22 connected to the fourth pad array 31 is also 50 μm.

[0097] In this embodiment, the package structure 100 based on the active silicon interposer further includes a first bump 32, which connects the bump pads 221 of the third pad array 22 and the bump pads 311 of the fourth pad array 31. Specifically, one first bump 32 connects one bump pad 221 in the third pad array 22 to one bump pad 311 in the fourth pad array 31, thereby achieving an electrical connection between the third pad array 22 and the fourth pad array 31. More specifically, one first bump 32 connects the functionally identical bump pads in the third pad array 22 and the fourth pad array 31, that is, achieving a one-to-one correspondence between the pins of the third pad array 22 and the fourth pad array 31. In other words, the two bump pads connected by the first bump 32 are used to achieve the same function, such as data transmission. The functions and deployments of each pad in the third pad array 22 and the fourth pad array 31 will be described in detail below. This embodiment does not specifically limit the number of first bumps 32. For details regarding the first protrusion 32, please refer to the above-mentioned protrusions; they will not be repeated here.

[0098] Preferably, if the first bump 32 is a microbump, then the bump pads 221 in the third pad array 22 and the bump pads 311 in the fourth pad array 31 are both microbump pads. Microbumps can be fabricated on a large scale on an entire wafer using photolithography and electroplating, which greatly improves production efficiency and thus reduces the cost of mass packaging.

[0099] In the embodiments of this application, the microbump can be any of the following types of bumps: solder bump, copper pillar bump (or micro copper pillar), and bonding copper bump.

[0100] In some embodiments, the first bump 32 is integrally formed with the bump pad 311 in the fourth pad array 31. In other embodiments, the first bump 32 may also be integrally formed with the bump pad 221 in the third pad array 22. To ensure high-quality interconnection between chips, different bump structures, different bump fabrication methods, and corresponding interconnection methods need to be selected for bumps of different sizes. This application does not impose specific limitations on these aspects.

[0101] The packaging structure 100 based on an active silicon interposer provided in this application embodiment has at least the following technical effects:

[0102] In this embodiment, the fourth pad array 31 on the chip is connected to the third pad array 22 on the active silicon interposer 20 via the first bump 32. This achieves high-performance interconnection between the chips in the chip module 30, as well as between the chips in the chip module 30 and the active silicon interposer 20. The high-performance interconnection between the chips in the chip module 30 is mainly achieved through metal lines and interconnect circuits on the active silicon interposer 20. The second pad array 21 on the active silicon interposer 20 is connected to the first pad array 11 on the package carrier 10 via the first metal lead 40. The chip's external signals are connected from the active silicon interposer 20 to the package carrier 10 via the first metal lead 40, and then the package carrier 10 connects the chip's external signals to an external interface, such as through the C4 bump array 14 of the package carrier 10. In other words, the pins of the wire bond are the external connections of the chip; wire bonding connects the chip to the outside world, achieving stacked chip packaging and low-insertion-loss inter-chip interconnection. Therefore, in the active silicon interposer-based packaging structure 100, the chip's external communication does not necessarily require high-performance packaging methods such as flip-chip arrays. This eliminates the need for contacts on both the top and bottom surfaces of the active silicon interposer 20; that is, neither the first surface 201 nor the second surface 202 of the active silicon interposer 20 needs to have bump pads. This avoids the need for TSV (Through Silicon Via) technology to connect the chip's external signals to the packaging carrier 10, thus avoiding process defects introduced by the through-silicon via (TSV) manufacturing process. This reduces the failure risk of the active silicon interposer-based packaging structure 100, improves its reliability, reduces the manufacturing difficulty and cost of the active silicon interposer 20, and increases packaging yield. Furthermore, since both the active silicon interposer 20 and the chip are made of silicon, they have the same coefficient of thermal expansion, which helps reduce stress.

[0103] In particular, in IoT and intelligent sensing applications, the input data bandwidth is low, and a large number of intermediate values ​​are generated during processing and sensing calculations. Therefore, the communication bandwidth requirement between modules within the packaged system (structure) is large, while the data volume of the final recognition result is very small, usually only a few bits. Advanced packaging technology can increase the storage capacity within the packaged system. In summary, the bandwidth requirement for external interconnection is small. Therefore, in the packaged structure 100 based on active silicon interposer provided in this application embodiment, the packaged system chip can be packaged externally using wire bonding, which can also meet the external interconnection bandwidth requirements; internally, high-bandwidth interconnection is achieved using active interposer.

[0104] Specifically, the packaging structure 100 based on an active silicon interposer provided in this application supports high-speed internal operation and low-speed external operation, meeting the needs of products such as intelligent sensing systems and possessing high market value. High-performance interconnection between chips is achieved through the first bump 32, and external signals from the chip are connected to the packaging carrier 10 through the first metal lead 40. For intelligent sensing systems, the bandwidth requirements for external sensor signal interfaces are not high. After the sensing function analyzes the data, the extracted features, recognition results, and other information are generally compressed significantly. Therefore, the first metal lead 40 is used to transmit external signals to meet the low bandwidth requirements. However, more complex artificial intelligence algorithms within the system often require higher internal communication bandwidth. Therefore, the first bump 32 connects the chip to the active silicon interposer 20, and the network within the first bump 32 and the active silicon interposer 20 achieves high-performance interconnection to meet the high bandwidth requirements for signal transmission within the chip.

[0105] The following section will describe in detail the setup of the third pad array 22 and the fourth pad array 31.

[0106] In this embodiment, the pads in the third pad array 22 and the fourth pad array 31 are configured according to the same pad layout plan. This pad layout plan indicates that the pad array includes at least one standard pad array. The standard pad array includes two functional areas. The first functional area can also be called the system common line. The pads in the first functional area are used to implement system functions to meet the necessary system function requirements. The second functional area can also be called the data line. The pads in the second functional area are used to implement data transmission. The network built into the active silicon interposer 20 realizes high-speed data interconnection between chips through the interface of the data line area (i.e., the pads in the second functional area).

[0107] In this embodiment, the pads in the first functional area include one or more of the following pads: a first power pad, a first ground pad, a system clock pad, a system reset pad, and a programmable feedthrough pad. The first power pad is used to provide power (VDD) to the chip via the active silicon interposer 20. The first ground pad is used to provide a common ground signal (VSS) to the chip via the active silicon interposer 20. The system clock pad is used to provide a system clock signal (sys_clk) to the chip via the active silicon interposer 20. The system reset pad is used to provide a system reset signal (sys_rstn) to the chip via the active silicon interposer 20. The programmable direct-connect pad is used to enable direct external connection of the chip. The programmable direct-connect pad is directly connected to the wire bonding pad of the active silicon interposer 20. The programmable direct-connect pad has a configurable signal, `reconfig`, which can be configured as: a direct connection signal between the chip and an external interface via the active silicon interposer 20, a power management control signal sent from the active silicon interposer 20 to the chip, or a probe signal between the active silicon interposer 20 and the chip, etc. Specifically, the internal control circuit of the active silicon interposer outputs the configurable signal `reconfig`, which is output to the configuration terminal of the programmable direct-connect pad to configure the signal direction of the programmable direct-connect pad (e.g., configuring the signal direction of the programmable direct-connect pad as input or output), and the internal connection (e.g., the direct connection signal between the active silicon interposer 20 and the external interface).

[0108] The pads in the second functional area include one or more of the following: a data strobe pad, a channel reset pad, a data transmission pad, a second power pad, and a second ground pad. The data strobe pad is used to transmit the data strobe signal `line_strb` in the data path. The channel reset pad is used to transmit the channel reset signal `line_rstn` in the data path. The data transmission pad is used to transmit the data transmission signal `line_data` in the data path. The second power pad is used to implement the interface voltage VDDIO provided by the active silicon interposer 20 to the chip. The second ground pad is used to implement the interface common ground signal VSSIO provided by the active silicon interposer 20 to the chip.

[0109] Preferably, the pads in the second functional area include at least a data strobe pad, a channel reset pad, and a data transmission pad.

[0110] Please see Figure 3 , Figure 3 This is a schematic diagram of the pad layout of a standard pad array provided in an embodiment of this application.

[0111] Taking the standard pad array 300 disposed on the active silicon interposer layer 20 as an example, the standard pad array 300 disposed on the active silicon interposer layer 20 is part or all of the third pad array 22, and the bump pads in the third pad array 22 are micro bump pads. Taking the standard pad array 300 as 7 rows and 11 columns as an example, the standard pad array 300 on the third pad array 22 includes a first functional area 310 and a second functional area 320.

[0112] In some embodiments, taking the first functional area 310 as having 3 columns and each data path in the second functional area 320 as having 2 columns as an example, the standard pad array can be 3+2N columns, where N is an integer greater than or equal to 1.

[0113] The first functional area 310 mainly provides chip power, system clock, and system reset signals to the chip. Specifically, the first functional area 310 includes a first power microbump pad, a first ground microbump pad, a system clock microbump pad, a system reset microbump pad, and a programmable direct-connect microbump pad. The first power microbump pad is used to transmit the system power signal VDD to the chip, the first ground microbump pad is used to transmit the common ground signal VSS to the chip, the system clock microbump pad is used to transmit the system clock signal sys_clk to the chip, the system reset microbump pad is used to transmit the system reset signal sys_rstn to the chip, and the programmable direct-connect microbump pad is used to transmit the configurable signal reconfig that is directly connected to the chip.

[0114] The second functional area 320 mainly provides power to the chip for data paths and interface circuits. Specifically, the second functional area 320 includes a data strobe microbump pad, a channel reset microbump pad, a data transmission microbump pad, a second power supply microbump pad, and a second ground microbump pad. The data strobe microbump pad is used to transmit the data strobe signal line_strb to the chip, the channel reset microbump pad is used to transmit the channel reset signal line_rstn, the data transmission microbump pad is used to transmit the data transmission signal line_data, the second power supply microbump pad is used to provide the chip with the interface power signal VDDIO, and the second ground microbump pad is used to provide the chip with the interface common ground signal VSSIO.

[0115] The second functional area 320 includes four data path areas: a first data path area 301, a second data path area 302, a third data path area 303, and a fourth data path area 304. Each of these four data path areas has a data selection microbump pad, a channel reset microbump pad, a data transmission microbump pad, a second power supply microbump pad, and a second grounding microbump pad evenly distributed within it.

[0116] To reduce power consumption during data communication, the power supply voltage of the data path interface is generally lower than the system power supply voltage. In this embodiment, the system power supply voltage can be 0.9V, and the interface power supply voltage can be 0.8V. The system power supply voltage corresponds to the first power pad (first power micro-bump pad), and the interface power supply voltage corresponds to the second power pad (second power micro-bump pad).

[0117] In order to reduce the interference of digital circuits to analog units in the data path, the active silicon interposer 20 isolates the common ground signal VSS and the interface common ground signal VSSIO during the design phase. In this application example, the method adopted is to route the two sets of ground signals separately and add a dedicated isolation unit between the two sets of ground signals.

[0118] While ensuring that the pads used to provide the functions of the first functional area 310 are deployed in the same continuous area, and the pads used to provide the functions of the second functional area are deployed in another continuous area, such as the pads of the first functional area 310 being located to the left of the active silicon interposer 20 and the pads of the second functional area being located to the right of the active silicon interposer 20, the type and number of pads included in each area can be set according to the actual situation. This application does not make specific limitations in this regard.

[0119] It should be noted that the number of rows and columns in the standard pad array can be set according to the actual situation, and the number of rows and columns in each area can be set according to the actual situation.

[0120] Each of the four data path areas described above can operate independently and can be configured for either transmitting (TX) or receiving (RX) data. For example, configuring the first data path area 301 and the second data path area 302 for transmitting (TX), and the third data path area 303 and the fourth data path area 304 for RX, results in a standard data operating mode. Configuring the first data path area 301 for TX, and the second, third, and fourth data path areas 302 and 303 for RX, results in a data receiving-centric operating mode. Configuring the first data path area 301, the second data path area 302, and the third data path area 303 for TX, and the fourth data path area 304 for RX, results in a data transmitting-centric operating mode. Furthermore, the third data path area 303 and the fourth data path area 304 both support floating, so the size of the chip's pad array can be smaller than that of a standard pad array. For example, if the microbump pads covered by the chip are not arranged in a 7x11 array, they can be arranged in a 7x7 array. The chip can correspond to the first functional area 310, the first data path area 301, and the second data path area 302 on the third pad array 22, and can also realize complete system functions.

[0121] The embodiments of this application do not specifically limit the number of data path areas included in the second functional area. For example, the second functional area 320 may include three data path areas or four data path areas.

[0122] Furthermore, the packaging structure 100 based on an active silicon interposer provided in this application embodiment may also include the following technical effects:

[0123] In this embodiment, the pads of the third pad array 22 and the pads of the fourth pad array 31 of the chip are set based on the same pad layout. The third pad array 22 can adapt to chips of different array sizes, which can improve the reuse rate of the active silicon interposer 20, avoid setting up a dedicated active silicon interposer 20 for different types of chips, and reduce the cost of the active silicon interposer 20.

[0124] Please see Figure 4 , Figure 4 This is a schematic diagram illustrating the interface function between the chip and the active silicon interposer provided in an embodiment of this application.

[0125] In this embodiment, the active silicon interposer 20 is a chip containing basic logic of common system-on-a-chip (SoC), such as power management, clock / reset signal generation, and communication functions. The active silicon interposer 20 is electrically connected to the chip through packaging and provides power, clock, and reset signals to the connected chip. Furthermore, the active silicon interposer 20 also provides data interconnection functionality between the chips. The active silicon interposer 20 implements data transmission functionality through an internal data link, thereby enabling data interaction between multiple chips in the chip module 30.

[0126] For example, with Figure 1Taking a portion of the pads in chip 1, the third pad array 22, and the fourth pad array 31a as examples, the second functional area 310a in the fourth pad array 31a includes a data transmission microbump pad 401a, and the first functional area 320a includes a first power microbump pad 402a, a first ground microbump pad 403a, a system clock microbump pad 404a, and a system reset microbump pad 405a. Correspondingly, the second functional area 310b in the third pad array 22 includes a data transmission microbump pad 401b, and the first functional area 320b includes a first power microbump pad 402b, a first ground microbump pad 403b, a system clock microbump pad 404b, and a system reset microbump pad 405b. Specifically, the data transmission microbump pads 401a of the fourth pad array 31a and 401b of the third pad array 22 are connected through a first bump 32, thereby transmitting data between the chip 1 and the active silicon interposer 20. Correspondingly, the system clock microbump pads 404 of the fourth pad array 31a and 404 of the third pad array 22 are connected through another first bump 32, thereby transmitting the system clock signal sys_clk between the chip 1 and the active silicon interposer 20, and so on.

[0127] In this embodiment, the active silicon interposer 20 includes a power management module, a clock management module, and a reset management module. The power management module provides power. The clock management module manages the system clock, and the reset management module manages the system reset.

[0128] Please see Figure 5 , Figure 5 This is a schematic diagram of the pad layout of the chip provided in an embodiment of this application.

[0129] like Figure 5 As shown, according to the above pad layout plan, a fourth pad array 31a is provided on the surface 1a of the active silicon interposer layer corresponding to the chip 1. The fourth pad array 31a includes a standard pad array and includes a first functional area 310 and a second functional area 320. Figure 5 The fourth pad array 31a, with 7 rows and 11 columns, is merely an example. It is understood that the number of rows and columns in the fourth pad array 31a can be set according to circumstances, such as 7 rows and 7 columns. This application does not impose specific limitations on this. The shape of each micro-bump pad in the fourth pad array 31a is not specifically limited here, and the deployment of pads in each functional area of ​​the fourth pad array can be set according to actual conditions.

[0130] The pad settings on the active silicon interposer 20 will be described in detail below.

[0131] In this embodiment, a second pad array 21 and a third pad array 22 are disposed on the first surface 201 of the active silicon interposer 20. The second pad array 21 is located around the perimeter of the first surface 201, and the third pad array 22 is enclosed within the second pad array 21. In other embodiments, the second pad array 21 is located on the left half of the first surface 201, and the third pad array 22 is located on the right half of the first surface 201. The specific positional relationship between the second pad array 21 and the third pad array 22 is not specifically limited.

[0132] In this embodiment of the application, there is a preset interval between the pads in the second pad array 21 and the pads in the third pad array 22. The preset interval is set according to a first distance limit and a second distance limit, wherein the first distance limit is the distance limit between the wedge used by the second pad array 21 when performing wire bonding and the corresponding chip, and the second distance limit is the distance limit between the third pad array 22 and the edge of the corresponding chip.

[0133] Specifically, after the chip is soldered to the third pad array 22 located at the center of the active silicon interposer 20, there is a certain distance limitation (i.e., the first distance limitation) between the wedge used in the wire bonding process of the second pad array 21 located around the active silicon interposer 20 and the chip located inside, and there is a certain distance limitation (i.e., the second distance limitation) between the fourth pad array of the chip and the edge of the chip. The two distance limitations together determine the spacing limitation of the pads in the second pad array 21 and the pads in the third pad array 22.

[0134] In this embodiment of the application, when the number of standard pad arrays in the third pad array 22 is greater than or equal to 2, the third pad array 22 further includes a fifth pad array arranged between the standard pad arrays, and the fifth pad array includes power pads and ground pads.

[0135] Please see Figure 6 , Figure 6 This is a schematic diagram of the pad layout of the active silicon interposer provided in an embodiment of this application.

[0136] like Figure 6 As shown, a second pad array 21 is disposed around the first surface 201 of the active silicon interposer 20, and a third pad array 22 is disposed inside the first surface 201 of the active silicon interposer 20, the third pad array 22 being surrounded by the second pad array 21. The third pad array 22 includes four standard pad arrays (601, 602, 603, and 604) and a fifth pad array 605.

[0137] The wire bonding pads 211 in the second pad array 21 can be square with a missing corner or triangular. The bump pads 221 in the third pad array 22 can be hexagonal, square with a missing corner, or circular. The bump pads 221 can be micro-bump pads. This application does not specifically limit the shape of the wire bonding pads 211 and the bump pads 221.

[0138] The fifth pad array 605 is shaped like a cross, and includes one row of pads and two columns of pads. The first power pad and the first ground pad in the fifth pad array 605 are evenly distributed outside the standard pad array area.

[0139] In this embodiment, the active silicon interposer 20 includes a socket 23, which serves as an interface for each chip. Based on this socket 23, a corresponding standard pad array can be defined, such as... Figure 6 As shown, it includes four sockets 23, and correspondingly, four standard pad arrays (601, 602, 603 and 604) are divided by the four sockets 23.

[0140] In some embodiments, sockets 23 may also be provided in the fifth pad array 605, such as a row of sockets 23 in the two rows of pads of the fifth pad array 605. By flexibly setting the position of the sockets 23, it is convenient to connect chips of different array sizes to the active silicon interposer 20.

[0141] The side length of the wire bonding pads 211 can be 50µm, etc., and the spacing between the wire bonding pads 211 can be 54µm, etc. The side length of the bump pads 221 (such as micro-bump pads) can be 72µm, etc., and the spacing between the bump pads 221 can be 110µm, etc. The preset interval between the wire bonding pads 211 in the second pad array 21 and the bump pads 221 in the third pad array 22 is approximately 300µm. This application does not specifically limit the specific dimensions of the wire bonding pads 211, the spacing of the wire bonding pads 211, the specific dimensions of the bump pads 221, the spacing of the bump pads 221, or the preset interval between the bump pads 221 and the wire bonding pads 211.

[0142] Figure 6 The third pad array 22 includes four standard pad arrays. The number of power pads and ground pads in each standard pad array can be set according to actual conditions. The shape and size of the microbump pads and the shape and size of the wire bonding pads can be set according to actual conditions. This application does not make specific limitations in this regard.

[0143] In this embodiment, the number of bump pads in the third pad array 22 located in the active silicon interposer 20 is scalable, meaning it can be expanded to support multiple standard pad arrays to support multiple chips. Correspondingly, the number of bump pads in the third pad array 22 is also scalable; that is, the size of the fourth pad array on the chip can be larger or smaller than the size of a standard pad array. For example, when the size of the fourth pad array on the chip is larger than the size of a standard pad array in the active silicon interposer 20, the chip can connect to the bump pads in the fifth pad array, i.e., connect the first power pad and the first ground pad located between the standard pad arrays, thereby providing more sufficient power supply. When the size of the fourth pad array on the chip is smaller than the size of a standard pad array in the active silicon interposer 20, the chip can connect only the bump pads with the necessary functions, still achieving complete system functionality.

[0144] The standard pad array in the third pad array 22 of the active silicon interposer 20 is composable, that is, multiple standard pad arrays can be combined into a whole area, thereby supporting large-size chips that occupy multiple standard pad arrays.

[0145] Please see Figure 7 , Figure 7 This is a schematic diagram of another pad layout for the active silicon interposer provided in an embodiment of this application.

[0146] like Figure 7 As shown, with Figure 3 The pad layout shown features a standard pad array on an active silicon interposer. Figure 7 It includes four standard pad arrays (701, 702, 703, and 704). Figure 7 and Figure 6 The difference is that, Figure 7 The standard pad array in the image is 7 rows and 11 columns, and the fifth pad array 705 includes two rows of pads and two columns of pads. For example... Figure 7 As shown, the first power pad and the first ground pad are evenly distributed outside the standard pad array.

[0147] Taking a standard pad array of 7 rows and 11 columns as an example, when the fourth pad array of the chip is 8 rows and 12 columns, the chip can connect to the bump pads in the active silicon interposer 20, including the bump pads of a standard pad array and the first power pad and the first ground pad from the fifth pad array adjacent to the standard pad array, providing the chip with richer power electrical connections.

[0148] For example, with the fourth pad array 31b of chip 2 arranged in 9 rows and 13 columns, and a standard pad array in the third pad array 22 arranged in 7 rows and 11 columns, the fourth pad array 31b of chip 2 is soldered to the third pad array 22 of the active silicon interposer 20. Specifically, the bump pads in the standard pad array 701, the bump pads located in the middle, and the bump pads of the fifth pad array 705 located near the standard pad array 701 are soldered. That is, the bump pads in the standard pad array 701, as well as the two rows of first power pads and two columns of bump pads near the standard pad array 701 are soldered, thus occupying 9 rows and 13 columns of the third pad array 22. As long as the chip and the bump pads in the standard pad array of the active silicon interposer 20 have the same function, the correct connection between this chip with a 9-row, 13-column bump array and the active silicon interposer can be guaranteed. At the same time, this will not affect the placement of chips connected to the standard pad arrays 702, 703, and 704. Therefore, the active silicon interposer 20 with this standardized pad layout can support a wider range of bump array size options.

[0149] Please see Figure 8 , Figure 8 for Figure 7 The diagram shows the connection between the active silicon interposer and the chip.

[0150] like Figure 8 As shown, with Figure 3 The pad layout shown features a standard pad array on an active silicon interposer. For example... Figure 8 As shown, the fourth pad array 801 on chip A connects to some pads in the standard pad array 701; the fourth pad array 802 on chip B connects to all pads in the standard pad array 702 and some pads in the fifth pad array 705; the fourth pad array 803 on chip C connects to all pads in the standard pad array 703 and some pads in the fifth pad array 705; and the fourth pad array 804 on chip D connects to some pads in the standard pad array 704. Chips A and B are rotationally symmetrical, and chips C and D are rotationally symmetrical. Using a standardized pad layout plan, the standardization of the micro-bump pad layout in the chip can be well supported. That is, as long as the chip and the active silicon interposer 20 use the same pad layout plan to deploy the bump pads, the chip can be soldered to any standard array in the active silicon interposer 20 without mirroring the chip layout. A chip that uses the same pad layout as the active silicon interposer 20 to deploy bump pads can be soldered to any... Figure 7 Any standard pad array area in the middle.

[0151] by Figure 3The first functional area 310 shown has a layout of 7 rows and 3 columns, and any complete data path area in the second functional area 320 has a layout of 7 rows and 2 columns. Figure 8 Chips A through D shown all cover the complete first functional area 310 and the complete data path area. For example, chip A covers 7 rows and 9 columns on the active silicon interposer, that is, it covers one complete first functional area and three complete data path areas (such as the first data path area 301, the second data path area 302, and the third data path area 303) on the active silicon interposer.

[0152] In other embodiments, the chip may not cover the entire first functional area and / or the entire data path area, for example... Figure 8 Chip A in the example can cover 6 rows and 11 columns on the active silicon interposer, that is, it covers the incomplete first functional area and the incomplete four data path areas. For example, Figure 8 The chip D in the middle can cover 7 rows and 8 columns, that is, it covers a complete first functional area, two complete data path areas and one incomplete data path area on the active silicon interposer.

[0153] It is understood that, with the pads in the active silicon interposer and the chip both set according to the same pad layout plan, the chip can be connected to the active silicon interposer according to the actual situation, and this application does not make any specific limitations on this.

[0154] Please see Figure 9 , Figure 9 for Figure 7 Another schematic diagram showing the connection between the active silicon interposer and the chip.

[0155] like Figure 9 As shown, the fourth pad array 901 on chip G connects to all pads in standard pad array 701, all pads in standard pad array 703, and some pads in fifth pad array 705. The fourth pad array 902 on chip H connects to all pads in standard pad array 702, all pads in standard pad array 704, and some pads in fifth pad array 705. Chips G and H are rotationally symmetrical.

[0156] During chip design, it is only necessary to ensure that the bump pads within the standard pad array area function correctly to achieve proper connection with the active silicon interposer. The active silicon interposer layer 20 can support the merging of standard pad array areas, thereby supporting the layout of larger upper-layer chips.

[0157] In some embodiments, all standard pad array areas can be combined into one area, and a chip can be connected. Figure 7 The third pad array 22 shown can support a chip array size of 16 rows and 24 columns.

[0158] When an active silicon interposer needs to connect two or more chips, the connection between the two or more chips and the active silicon interposer shall be adjusted according to the actual situation. The two or more chips are not limited to rotational symmetry, and this application does not make any specific limitation in this regard.

[0159] Please see Figure 10 , Figure 10 This is a schematic diagram of the process for fabricating a packaging structure based on an active silicon interposer, as provided in an embodiment of this application.

[0160] Step S 101: Provide a packaging carrier and form a first pad array on the packaging carrier.

[0161] The details regarding the packaging carrier and the first pad array can be found above.

[0162] In the embodiments of this application, the first pad array can be deployed according to the specific type of the packaging carrier and the actual situation. For example, when the packaging carrier is a packaging shell, the first pad array can be deployed around the perimeter of the packaging shell. When the packaging carrier is a packaging substrate, the first pad array can be deployed around the upper surface of the packaging substrate. The deployment method and position of the first pad array can be set according to the actual situation, and this application does not impose specific limitations on them.

[0163] Step S 102: Provide an active silicon interposer, and form a second pad array on the first surface of the active silicon interposer, and form a third pad array on the first surface according to the pad layout plan.

[0164] The relevant details regarding the active silicon interposer, the second pad array, and the third pad array can be found above.

[0165] In this embodiment, pads in the second and third pad arrays can be deployed at preset intervals, and the positional relationship between the second and third pad arrays can be referred to the above.

[0166] Step S 103: Provide a chip module, which includes at least one chip, and form a fourth pad array on the chip according to the pad layout plan.

[0167] The relevant memory for the chip module, chip, and third pad array can be referenced above.

[0168] In this embodiment, pads in the third and fourth pad arrays are deployed according to the first and second functional areas indicated by the same pad layout plan. For details, please refer to the above. Figures 3 to 9 .

[0169] The execution order of the above steps S101, S102 and S103 can be adjusted according to the actual situation.

[0170] Step S 104: Connect the fourth pad array and the third pad array through the first bump.

[0171] The relevant memory for the first convex point can be referenced above.

[0172] In this embodiment of the application, when the fourth pad array is generated on the chip, a first bump corresponding to each bump pad in the fourth pad array is generated. Then, the chip is flip-chip bonded to the active silicon interposer to connect the fourth pad array and the third pad array through the first bump.

[0173] Step S 105: Place the second surface of the active silicon interposer on the packaging carrier and connect the second pad array and the first pad array through the first metal lead, with the second surface facing the first surface.

[0174] The relevant memory for the first metal lead can be referenced above.

[0175] In this embodiment, the second surface of the active silicon interposer is placed on the upper surface of the packaging carrier, and the second pad array of the active silicon interposer is electrically connected to the first pad array of the packaging carrier by wire bonding.

[0176] The above can be executed by first performing step S 105 and then step S 104.

[0177] Those skilled in the art should recognize that the above embodiments are only used to illustrate this application and are not intended to limit this application. Any appropriate changes and variations made to the above embodiments within the essential spirit and scope of this application fall within the scope of protection claimed in this application.

Claims

1. A packaging structure based on an active silicon interposer, characterized in that, include: The packaging carrier includes a first pad array; An active silicon interposer is located above the packaging carrier, and the active silicon interposer includes a second pad array and a third pad array; The first metal lead is used to connect the second pad array to the first pad array; A chip module is located above the active silicon interposer. The chip module includes at least one chip, and the chip includes a fourth pad array. The pads in the fourth pad array are arranged according to the same pad layout as those in the third pad array. The fourth pad array and the third pad array are connected by a first bump. The active silicon interposer includes a first surface and a second surface opposite to each other. The first surface corresponds to the chip module, and the second surface corresponds to the packaging carrier. The second pad array and the third pad array are located on the first surface, and the second pad array is located around the first surface, while the third pad array is enclosed within the second pad array. The third pad array includes at least one standard pad array configured according to the pad layout plan, and the fourth pad array includes at least one standard pad array configured according to the pad layout plan. The standard pad array includes pads in a first functional area and pads in a second functional area. The pads in the first functional area include one or more of the following: a first power pad, a first ground pad, a system clock pad, a system reset pad, and a programmable direct-connect pad. The pads in the second functional area include one or more of the following: a data strobe pad, a channel reset pad, a data transmission pad, a second power pad, and a second ground pad.

2. The packaging structure based on an active silicon interposer as described in claim 1, characterized in that, When the number of standard pad arrays in the third pad array is greater than or equal to 2, the third pad array has at least one pair of rotationally symmetric standard pad arrays.

3. The packaging structure based on an active silicon interposer as described in claim 1, characterized in that, When the number of standard pad arrays in the third pad array is greater than or equal to 2, the third pad array further includes a fifth pad array arranged among the standard pad arrays, and the fifth pad array includes a first power pad and a first ground pad.

4. The packaging structure based on an active silicon interposer as described in claim 1, characterized in that, The first metal lead is a bonding lead, and the first bump is a microbump, which is integrally formed with the pads in the fourth pad array.

5. The packaging structure based on an active silicon interposer as described in claim 1, characterized in that, There is a preset interval between the pads in the second pad array and the pads in the third pad array.

6. The packaging structure based on an active silicon interposer as described in claim 1, characterized in that, The spacing between the pads in the third pad array is the same as the spacing between the pads in the fourth pad array, and the functionally corresponding pads in the third pad array and the fourth pad array are connected by the first bump.

7. The packaging structure based on an active silicon interposer as described in claim 1, characterized in that, The packaging carrier includes any one of a packaging substrate, a packaging shell, or a circuit board.

8. A method for fabricating a packaging structure based on an active silicon interposer as described in any one of claims 1 to 7, characterized in that, The method includes: A packaging carrier is provided, and a first pad array is formed on the packaging carrier; An active silicon interposer is provided, and a second pad array is formed on a first surface of the active silicon interposer, and a third pad array is formed on the first surface according to the pad layout plan. A chip module is provided, the chip module including at least one chip, and a fourth pad array is formed on the chip according to the pad layout plan; The fourth pad array is connected to the third pad array via a first bump; The second surface of the active silicon interposer is placed on the packaging carrier, and the second pad array is connected to the first pad array via a first metal lead, with the second surface opposite to the first surface.

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