A method for reducing the number of photomasks on an array substrate

Abstract

This invention relates to the field of display technology and provides a method for reducing the number of photomasks on an array substrate, comprising the following steps: S1, fixing a first insulating layer; S2, fixing a semiconductor layer on the upper surface of the first insulating layer; S3, applying photoresist to the upper surface of the semiconductor layer; exposing the photoresist using a grayscale photomask; developing the photoresist; S4, forming DC holes using dry etching; S5, performing wet etching on the semiconductor layer to form an active layer for the GIP circuit area and an active layer for the in-plane display area; S6, removing the photoresist. The advantages of this invention are: it combines the two traditional manufacturing processes of DC holes and active layers into a single new manufacturing process, using a single photomask, thus reducing the number of photomasks and lowering production costs.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a method for reducing the number of photomasks on an array substrate. Background Technology

[0002] With LCD panel manufacturers continuously investing in high-generation production lines and expanding production scale, they face intense market competition, significantly thinning their profit margins. Under the pressure of intensified competition and continuously plummeting prices, cost reduction has become essential for LCD panel manufacturers to survive. Reducing raw material costs and streamlining production processes are among the methods adopted by manufacturers to compress production costs, increase profits, and enhance market competitiveness.

[0003] The existing manufacturing process for in-cell TFT-LCD array substrates requires two different photomasks to form the holes and layer patterns. These photomasks are also called optical masks. In-cell technology refers to the method of embedding touch panel functionality into liquid crystal pixels, i.e., embedding touch sensor functionality inside the display screen. Screens using in-cell technology are lighter, thinner, and have better light transmittance, reducing the bonding time between screen layers and improving production efficiency.

[0004] See Figure 1 The diagram shows the structure of an embedded touch array substrate for existing line drive technology. The array substrate is divided into a GIP circuit area and an in-plane display area. The GIP circuit area is represented by only one TFT device in the diagram, just to show the design of the hole connection between the drain of the GIP circuit area and the gate of the in-plane display area. Figure 1The traditional method for fabricating an array substrate is as follows: (1) A gate of the GIP circuit region and a gate of the in-plane display region are fixedly disposed on the upper surface of a glass substrate, and a first photomask is used in this process; (2) A first insulating layer is fixedly disposed on the gate of the GIP circuit region, the gate of the in-plane display region and the upper surface of the glass substrate; (3) An active layer of the GIP circuit region and an active layer of the in-plane display region are fixedly disposed on the upper surface of the first insulating layer, and a second photomask is used in this process; (4) A DC hole is opened in the first insulating layer, and a third photomask is used in this process; the DC hole is a hole used to connect the drain of the GIP circuit region and the gate of the in-plane display region; the DC hole extends from the left end of the gate of the in-plane display region to the GIP circuit region; (5) A source of the GIP circuit region, a drain of the GIP circuit region, a source of the in-plane display region and a drain of the in-plane display region are fixedly disposed on the upper surface of the first insulating layer, and a fourth photomask is used in this process, and the drain of the GIP circuit region is connected to the gate of the in-plane display region through the DC hole; (6) A first insulating layer is fixedly disposed on the source, drain, and in-plane display region of the GIP circuit region. (7) A second insulating layer is fixedly disposed on the upper surface of the active layer, the source and drain of the in-plane display area, the active layer, and the first insulating layer; (8) A TP trace is fixedly disposed on the upper surface of the second insulating layer, and a fifth photomask is used in this process; (9) A third insulating layer is fixedly disposed on the upper surface of the TP trace and the second insulating layer; (10) A PV hole is opened on the third insulating layer, and a sixth photomask is used in this process; the PV hole is a hole for connecting the pixel electrode to the drain of the in-plane display area; (11) A pixel electrode is fixedly disposed on the third insulating layer, and the pixel electrode is connected to the drain of the in-plane display area through the PV hole, and a seventh photomask is used in this process; (12) A fourth insulating layer is fixedly disposed on the upper surface of the pixel electrode and the third insulating layer; (13) A CH hole is opened on the fourth insulating layer, and an eighth photomask is used in this process; the CH hole is a hole for connecting the common electrode to the TP trace; (14) A common electrode is fixedly disposed on the fourth insulating layer, and the common electrode is connected to the TP trace through the CH hole, and a ninth photomask is used in this process.

[0005] Figure 1 The traditional fabrication of array substrates uses a total of nine photomasks with different structures. The cost of the photomasks is one of the production costs of the array substrate, resulting in high production costs. Therefore, how to reduce the number of photomasks and lower production costs is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for reducing the number of photomasks on an array substrate, thereby reducing the number of photomasks and lowering production costs.

[0007] This invention is implemented as follows: a method for reducing the number of photomasks on an array substrate, comprising the following steps:

[0008] S1. The gate of the GIP circuit area and the gate of the in-plane display area are fixedly disposed on the upper surface of the glass substrate;

[0009] A first insulating layer is fixedly disposed on the gate of the GIP circuit area, the gate of the in-plane display area, and the upper surface of the glass substrate;

[0010] S2. A semiconductor layer is fixedly disposed on the upper surface of the first insulating layer;

[0011] S3. Apply photoresist to the upper surface of the semiconductor layer;

[0012] The photoresist is exposed using a grayscale photomask. The grayscale photomask has a first light-shielding area, a second light-shielding area, a fully transparent area, and a partially transparent area. The first light-shielding area is aligned with the active layer of the GIP circuit area of ​​the array substrate. The second light-shielding area is aligned with the active layer of the in-plane display area of ​​the array substrate. The fully transparent area is aligned with the DC hole of the array substrate.

[0013] Then the photoresist is developed to form a shape consisting of a first bump, a second bump, a pit, and a reference layer. The first bump corresponds to the position of the first light-blocking area, the second bump corresponds to the position of the second light-blocking area, the pit corresponds to the position of the fully transparent area, and the reference layer corresponds to the position of the partially transparent area.

[0014] S4. Using dry etching, the semiconductor layer and the first insulating layer are etched downwards from the pit to form a DC hole. The gate of the in-plane display area is exposed in the DC hole. The reference layer is completely etched and the semiconductor layer is exposed. The first bump is etched into a first blocking block and the second bump is etched into a second blocking block.

[0015] S5. Perform wet etching on the semiconductor layer to form an active layer of the GIP circuit region and an active layer of the in-plane display region. The active layer of the GIP circuit region is located directly below the first blocking block, and the active layer of the in-plane display region is located directly below the second blocking block.

[0016] S6. Remove the photoresist.

[0017] Furthermore, it also includes the following steps:

[0018] S7. A source electrode, a drain electrode, an in-plane display area source electrode, and an in-plane display area drain electrode are fixedly disposed on the upper surface of the first insulating layer. The source electrode and the drain electrode of the GIP circuit area are respectively connected to both ends of the active layer of the GIP circuit area. The source electrode and the drain electrode of the in-plane display area are respectively connected to both ends of the active layer of the in-plane display area. The drain electrode of the GIP circuit area is connected to the gate electrode of the in-plane display area through the DC hole.

[0019] A second insulating layer is fixedly disposed on the upper surface of the source, drain, active layer of the GIP circuit region, source, drain of the in-plane display region, active layer of the in-plane display region, and the first insulating layer.

[0020] TP traces are fixedly disposed on the upper surface of the second insulating layer;

[0021] A third insulating layer is fixedly disposed on the upper surface of the TP trace and the second insulating layer;

[0022] A PV hole is formed in the third insulating layer, and the PV hole also penetrates the second insulating layer and exposes the drain electrode of the in-plane display area;

[0023] A pixel electrode is fixedly disposed in the third insulating layer, and the pixel electrode is connected to the drain of the in-plane display area through the PV hole;

[0024] A fourth insulating layer is fixedly disposed on the upper surface of the pixel electrode and the third insulating layer;

[0025] A CH hole is formed in the fourth insulating layer, and the CH hole also penetrates the third insulating layer and exposes the TP trace;

[0026] A common electrode is fixedly disposed on the upper surface of the fourth insulating layer, and the common electrode is connected to the TP trace through the CH hole.

[0027] Furthermore, both the first and second light-shielding areas are light-shielding plates, the fully light-transmitting area is a light-transmitting through-hole, and the partially light-transmitting area is a grating.

[0028] Furthermore, in S3, the upper surface of the photoresist is a flat surface before the exposure process.

[0029] Furthermore, in S2, the semiconductor layer is made of metal oxide semiconductor, and the semiconductor layer is deposited on the upper surface of the first insulating layer by PVD film deposition technology.

[0030] Furthermore, the photoresist is a positive photoresist.

[0031] Furthermore, the light transmittance of the partially transparent area is 50%.

[0032] Furthermore, in S4, the reference layer, the first bump, and the second bump are not dry etched, but are developed again. The reference layer is completely dissolved by the developer to expose the semiconductor layer, the first bump is dissolved by the developer to form the first blocking block, and the second bump is dissolved by the developer to form the second blocking block.

[0033] The advantages of this invention are: optimized manufacturing process, grayscale photomask is prefabricated according to the position of the active layer of the GIP circuit area, the active layer of the in-plane display area, and the DC hole on the array substrate, and this grayscale photomask is used for exposure and development etching, realizing the merging of the two traditional manufacturing processes of DC hole and active layer into a new manufacturing process, and sharing a photomask. Compared with the prior art, this invention reduces the number of photomasks and lowers the production cost. Attached Figure Description

[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0035] Figure 1 This is a schematic diagram of the array substrate structure in the background technology.

[0036] Figure 2 This is a flowchart of the method for reducing the number of photomasks on the array substrate of the present invention.

[0037] Figure 3 This is a schematic diagram of the thin film fabrication process of the method of the present invention.

[0038] Figure 4 This is a schematic diagram of the photoresist coating process in the photolithography method of the present invention.

[0039] Figure 5 This is a schematic diagram of photoresist exposure and development according to the method of the present invention.

[0040] Figure 6 This is a schematic diagram of the dry etching process of the method of the present invention.

[0041] Figure 7 This is a schematic diagram of the wet etching process of the method of the present invention.

[0042] Figure 8 This is a schematic diagram of the film peeling process of the method of the present invention.

[0043] Reference numerals: Glass substrate 10; Gate of GIP circuit area 11; Gate of in-plane display area 12;

[0044] First insulating layer 21; DC hole 211; Second insulating layer 22; Third insulating layer 23; PV hole 231; Fourth insulating layer 24; CH hole 241;

[0045] Semiconductor layer 30; active layer of GIP circuit region 31; active layer of in-plane display region 32; source of GIP circuit region 33; drain of GIP circuit region 34; source of in-plane display region 35; drain of in-plane display region 36;

[0046] TP trace 40;

[0047] Pixel electrode 50;

[0048] Common electrode 60;

[0049] Photoresist 70; First bump 71; First blocking block 711; Second bump 72; Second blocking block 721; Recess 73; Reference layer 74;

[0050] Grayscale mask 80; First shading area 81; Second shading area 82; Fully transparent area 83; Partially transparent area 84;

[0051] Light intensity 90. Detailed Implementation

[0052] This invention provides a method for reducing the number of photomasks on an array substrate, overcoming the shortcomings of traditional array substrate fabrication methods that use a total of nine photomasks with different structures, resulting in high production costs. This method optimizes the manufacturing process, reduces the number of photomasks, and lowers production costs. This invention utilizes a total of eight photomasks with different structures.

[0053] The overall concept of the technical solution of this invention is as follows:

[0054] A grayscale photomask is pre-fabricated based on the positions of the active layer of the GIP circuit region, the active layer of the in-plane display region, and the DC aperture on the array substrate. The grayscale photomask has a first light-blocking area, a second light-blocking area, a fully transparent area, and a partially transparent area. The first light-blocking area is aligned with the active layer of the GIP circuit region on the array substrate, the second light-blocking area is aligned with the active layer of the in-plane display region on the array substrate, the fully transparent area is aligned with the DC aperture on the array substrate, and correspondingly, the partially transparent area is aligned with the remaining positions on the array substrate. The DC aperture is used for connecting the drain of the GIP circuit region to the gate of the in-plane display region.

[0055] A semiconductor layer is fabricated using a thin-film process. Then, a grayscale photomask is used to expose and develop the photoresist on the semiconductor layer, transforming it into a shape composed of a first bump, a second bump, a pit, and a reference layer. A DC hole is formed at the pit location using dry etching, and the reference layer is removed. The first bump is transformed into a first blocking block, and the second bump into a second blocking block. A portion of the semiconductor layer is retained at the location of the first blocking block as the active layer of the GIP circuit area, and a portion of the semiconductor layer is retained at the location of the second blocking block as the active layer of the in-plane display area. Finally, the first and second blocking blocks are peeled off using a stripping process, completing the fabrication process of the DC hole and the active layer.

[0056] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0057] See Figures 1 to 8 The preferred embodiment of the present invention.

[0058] A method for reducing the number of photomasks on an array substrate includes the following steps:

[0059] S1. A GIP circuit area gate 11 and an in-plane display area gate 12 are fixedly disposed on the upper surface of the glass substrate 10; the first photomask is used in this process.

[0060] A first insulating layer 21 is fixedly disposed on the gate 11 of the GIP circuit area, the gate 12 of the in-plane display area, and the upper surface of the glass substrate 10;

[0061] S2, Thin Film Process: Combination Figure 3 A semiconductor layer 30 is fixedly disposed on the upper surface of the first insulating layer 21; the semiconductor layer 30 is made of metal oxide semiconductor and is deposited on the upper surface of the first insulating layer 21 by PVD film deposition technology.

[0062] S3, Huangguang process: combined with Figure 4 Photoresist 70 is applied to the upper surface of the semiconductor layer 30. The upper surface of photoresist 70 is flat, which helps to form a specific shape for subsequent photoresist 70. The photoresist 70 is a positive photoresist, the part of which is exposed to light will dissolve in the photoresist developer, while the part that is not exposed to light will not dissolve in the photoresist developer.

[0063] Combination Figure 5 Light 90 illuminates a grayscale photomask 80, exposing the photoresist 70 through the grayscale photomask 80. The grayscale photomask 80 has a first light-blocking area 81, a second light-blocking area 82, a fully transparent area 83, and a partially transparent area 84. The first light-blocking area 81 is aligned with the active layer 31 of the GIP circuit area of ​​the array substrate, the second light-blocking area 82 is aligned with the active layer 32 of the in-plane display area of ​​the array substrate, and the fully transparent area 83 is aligned with the DC hole 211 of the array substrate. Correspondingly, the partially transparent area 84 is aligned with the remaining areas of the array substrate. The fully transparent area 83 is 100% transparent, the first light-blocking area 81 and the second light-blocking area 82 are both 100% opaque, and the transmittance of the partially transparent area 84 is 50%. Specifically, the first light-blocking area 81 and the second light-blocking area 82 are both light-blocking plates, the fully transparent area 83 is a light-transmitting through-hole, and the partially transparent area 84 is a grating. The grayscale mask 80 used in this process is the second mask.

[0064] Then, the photoresist 70 is developed to form a shape composed of a first bump 71, a second bump 72, a recess 73, and a reference layer 74. The first bump 71 corresponds to the position of the first light-blocking area 81, the second bump 72 corresponds to the position of the second light-blocking area 82, the recess 73 corresponds to the position of the fully light-transmitting area 83, and the reference layer 74 corresponds to the position of the partially light-transmitting area 84.

[0065] S4, Dry Etching Process: Combined with Figure 6 Using dry etching, the semiconductor layer 30 and the first insulating layer 21 are etched downwards from the pit 73 to form a DC hole 211. The in-plane display area gate 12 is exposed through the DC hole 211. The reference layer 74 is completely etched to expose the semiconductor layer 30. The first bump 71 is etched into a first blocking block 711, and the second bump 72 is etched into a second blocking block 721. In the figure, the DC hole 211 is in the GIP circuit area, and the left end of the in-plane display area gate 12 extends into the GIP circuit area.

[0066] The semiconductor layer 30 and the first insulating layer 21 at the DC hole 211 are etched using dry etching technology. Simultaneously, the photoresist in the reference layer 74, i.e., the thinner photoresist layer, is also etched. Under normal etching speeds, the metal-oxide semiconductor layer 30 and the first insulating layer 21 at the DC hole 211 are etched away first, followed by the thinner photoresist layer. Therefore, the dry etching process ends when all the photoresist in the thinner layer is etched away.

[0067] In another implementation of this embodiment, in S4, the reference layer 74, the first bump 71, and the second bump 72 are not dry etched, but are developed again. The reference layer 74 is completely dissolved by the developing solution to expose the semiconductor layer 30. The first bump 71 is dissolved by the developing solution to form the first blocking block 711, and the second bump 72 is dissolved by the developing solution to form the second blocking block 721.

[0068] After the DC hole 211 is etched out, the thickness of the reference layer 74 may not have been completely etched away. Therefore, the remaining reference layer 74 can be removed by extending the dry etching time or by using a developer.

[0069] S5, Wet Etching Process: Combined Figure 7The semiconductor layer 30 is wet-etched to form a GIP circuit region active layer 31 and an in-plane display region active layer 32. The GIP circuit region active layer 31 is located directly below the first blocking block 711, and the in-plane display region active layer 32 is located directly below the second blocking block 721. Specifically, the metal oxide semiconductor is etched by acid wet etching until the shape of the active layer is formed.

[0070] S6, film peeling process, combined with Figure 8 The photoresist 70 is then peeled off. At this point, only the first blocking block 711 and the second blocking block 721 remain of the photoresist 70, i.e., the first blocking block 711 and the second blocking block 721 are peeled off. The fabrication process of the DC hole and the active layer is complete.

[0071] S7, see also Figure 1 A GIP circuit region source 33, a GIP circuit region drain 34, an in-plane display region source 35, and an in-plane display region drain 36 are fixedly disposed on the upper surface of the first insulating layer 21. The GIP circuit region source 33 and GIP circuit region drain 34 are respectively connected to both ends of the GIP circuit region active layer 31, and the in-plane display region source 35 and in-plane display region drain 36 are respectively connected to both ends of the in-plane display region active layer 32. The GIP circuit region drain 34 is connected to the in-plane display region gate 12 through the DC hole 211. The formed GIP circuit region TFT device includes a GIP circuit region gate 11, a GIP circuit region source 33, a GIP circuit region drain 34, and a GIP circuit region active layer 31. The in-plane display region TFT device includes an in-plane display region gate 12, a GIP circuit in-plane display region source 35, an in-plane display region drain 36, and an in-plane display region active layer 32. A third photomask is used in this process.

[0072] A second insulating layer 22 is fixedly disposed on the upper surface of the source 33, drain 34, active layer 31, source 35, drain 36, and active layer 32 of the GIP circuit area and the first insulating layer 21.

[0073] TP traces 40 are fixedly disposed on the upper surface of the second insulating layer 22; a fourth photomask is used in this process.

[0074] A third insulating layer 23 is fixedly disposed on the upper surface of the TP trace 40 and the second insulating layer 22;

[0075] A PV hole 231 is formed in the third insulating layer 23, which also penetrates the second insulating layer 22 and exposes the drain electrode 36 of the in-plane display area; a fifth photomask is used in this process.

[0076] A pixel electrode 50 is fixedly disposed on the third insulating layer 23, and the pixel electrode 50 is connected to the drain electrode 36 of the in-plane display area through the PV hole 231; a sixth photomask is used in this process.

[0077] A fourth insulating layer 24 is fixedly disposed on the upper surface of the pixel electrode 50 and the third insulating layer 23;

[0078] A CH hole 241 is formed in the fourth insulating layer 24. The CH hole 241 also penetrates the third insulating layer 23 and exposes the TP trace 40. A seventh photomask is used in this process.

[0079] A common electrode 60 is fixedly disposed on the upper surface of the fourth insulating layer 24, and the common electrode 60 is connected to the TP trace 40 through the CH hole 241. An eighth photomask is used in this process. The TP trace provides a voltage signal to the common electrode.

[0080] The method for reducing the number of photomasks in the array substrate of the present invention optimizes the manufacturing process under the existing structure of embedded touch array substrates using row driving technology. It proposes to combine the two conventional manufacturing processes of the DC hole 211 (i.e., the hole used to connect the drain 34 of the GIP circuit area to the gate 12 of the in-plane display area) and the active layer into a new manufacturing process, using only one photomask. Compared with the prior art, the present invention uses eight photomasks, reducing the number of photomasks and lowering production costs.

[0081] The method for reducing the number of photomasks in this invention mainly utilizes a grayscale photomask 80, which is 100% transparent at the position aligned with the DC hole 211, 100% opaque at the position aligned with the active layer, and partially transparent at other positions. After depositing a full layer of metal oxide semiconductor on the first insulating layer 21, the photolithography process is initiated. Since the photoresists 70 used are all positive photoresists, the parts exposed to light will dissolve in the photoresist developer, while the parts not exposed to light will not dissolve. After development, there is no photoresist 70 above the position where the DC hole 211 needs to be formed, i.e., a recess 73 is provided; the photoresist 70 above the position where the active layer needs to be formed is the thickest, i.e., the first bump 71 and the second bump 72 are provided; the photoresist 70 above other positions is thinner, i.e., a reference layer 74 is provided. Then, dry etching is performed directly to etch away the metal oxide semiconductor layer 30 and the first insulating layer 21 at the DC hole 211 position; then dry etching is continued or another development process is performed to remove the reference layer photoresist, so that only the position where the active layer needs to be made has photoresist present, that is, at this time only the first blocking block 711 and the second blocking block 721 remain as photoresist. Then, wet acid etching is performed directly to make the shape of the active layer. Finally, the remaining photoresist is stripped off, thus completing the fabrication process of the DC hole and the active layer.

[0082] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for reducing the number of photomasks on an array substrate, characterized in that, Includes the following steps: S1. The gate of the GIP circuit area and the gate of the in-plane display area are fixedly disposed on the upper surface of the glass substrate; A first insulating layer is fixedly disposed on the gate of the GIP circuit area, the gate of the in-plane display area, and the upper surface of the glass substrate; S2. A semiconductor layer is fixedly disposed on the upper surface of the first insulating layer; S3. Apply photoresist to the upper surface of the semiconductor layer; The photoresist is exposed using a grayscale photomask. The grayscale photomask has a first light-shielding area, a second light-shielding area, a fully transparent area, and a partially transparent area. The first light-shielding area is aligned with the active layer of the GIP circuit area of ​​the array substrate. The second light-shielding area is aligned with the active layer of the in-plane display area of ​​the array substrate. The fully transparent area is aligned with the DC hole of the array substrate. Then the photoresist is developed to form a shape consisting of a first bump, a second bump, a pit, and a reference layer. The first bump corresponds to the position of the first light-blocking area, the second bump corresponds to the position of the second light-blocking area, the pit corresponds to the position of the fully transparent area, and the reference layer corresponds to the position of the partially transparent area. S4. Using dry etching, the semiconductor layer and the first insulating layer are etched downwards from the pit to form a DC hole. The gate of the in-plane display area is exposed in the DC hole. The reference layer is completely etched and the semiconductor layer is exposed. The first bump is etched into a first blocking block and the second bump is etched into a second blocking block. S5. Perform wet etching on the semiconductor layer to form an active layer of the GIP circuit region and an active layer of the in-plane display region. The active layer of the GIP circuit region is located directly below the first blocking block, and the active layer of the in-plane display region is located directly below the second blocking block. S6. Remove the photoresist.

2. The method for reducing the number of photomasks on an array substrate according to claim 1, characterized in that, It also includes the following steps: S7. A source electrode, a drain electrode, an in-plane display area source electrode, and an in-plane display area drain electrode are fixedly disposed on the upper surface of the first insulating layer. The source electrode and the drain electrode of the GIP circuit area are respectively connected to both ends of the active layer of the GIP circuit area. The source electrode and the drain electrode of the in-plane display area are respectively connected to both ends of the active layer of the in-plane display area. The drain electrode of the GIP circuit area is connected to the gate electrode of the in-plane display area through the DC hole. A second insulating layer is fixedly disposed on the upper surface of the source, drain, active layer of the GIP circuit region, source, drain of the in-plane display region, active layer of the in-plane display region, and the first insulating layer. TP traces are fixedly disposed on the upper surface of the second insulating layer; A third insulating layer is fixedly disposed on the upper surface of the TP trace and the second insulating layer; A PV hole is formed in the third insulating layer, and the PV hole also penetrates the second insulating layer and exposes the drain electrode of the in-plane display area; A pixel electrode is fixedly disposed in the third insulating layer, and the pixel electrode is connected to the drain of the in-plane display area through the PV hole; A fourth insulating layer is fixedly disposed on the upper surface of the pixel electrode and the third insulating layer; A CH hole is formed in the fourth insulating layer, and the CH hole also penetrates the third insulating layer and exposes the TP trace; A common electrode is fixedly disposed on the upper surface of the fourth insulating layer, and the common electrode is connected to the TP trace through the CH hole.

3. The method for reducing the number of photomasks on an array substrate according to claim 1, characterized in that, Both the first and second light-shielding areas are light-shielding plates, the fully light-transmitting area is a light-transmitting through hole, and the partially light-transmitting area is a grating.

4. The method for reducing the number of photomasks on an array substrate according to claim 1, characterized in that, In S3, the upper surface of the photoresist is a flat surface before the exposure process.

5. The method for reducing the number of photomasks on an array substrate according to claim 1, characterized in that, In S2, the semiconductor layer is made of metal oxide semiconductor and is deposited on the upper surface of the first insulating layer by PVD film deposition technology.

6. The method for reducing the number of photomasks on an array substrate according to claim 1, characterized in that, The photoresist is a positive photoresist.

7. The method for reducing the number of photomasks on an array substrate according to claim 1, characterized in that, The light transmittance of the partially transparent area is 50%.

8. The method for reducing the number of photomasks on an array substrate according to claim 1, characterized in that, In S4, the reference layer, the first bump, and the second bump are not dry etched, but are developed again. The reference layer is completely dissolved by the developer to expose the semiconductor layer. The first bump is dissolved by the developer to form the first barrier block, and the second bump is dissolved by the developer to form the second barrier block.

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