A semiconductor device, a method of manufacturing the same, and application of a low temperature issg process
Patent Information
- Application Number
- CN202310896473.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-20
- Publication Date
- 2026-09-22
- Estimated Expiration
- 2043-07-20
AI Technical Summary
[0005]鉴于上述的分析，本发明实施例旨在提供一种半导体器件及其制备方法和低温ISSG工艺的应用，用以解决现有的垂直型3D全环绕栅极晶体管中的纳米片边缘的尖角易引发高电场带来栅电压击穿的问题
[0029]1、本发明利用低温原位水汽生成氧化(in-situ stream gate oxide，ISSG)工艺对尖角的超高氧化能力，在不影响源极和漏极的情况下，将后栅工艺(尤其是对于GAA晶体管)中释放的纳米片的尖角修饰为圆角，避免尖角高电场引起的栅电压击穿问题。
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Figure CN116845088B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, its fabrication method, and the application of a low-temperature ISSG process. Background Technology
[0002] As transistor feature sizes continue to shrink, traditional MOSFET devices have undergone a transformation from planar to three-dimensional structures. This evolution of MOSFET structures has been accompanied by the emergence of numerous new processes and materials. 3D FinFET technology accompanied the development of the semiconductor industry, reaching the 7nm / 5nm era. After the 5nm technology node, 3D FinFET technology has reached its limit, replaced by 3D gate-all-around (GAA) transistors.
[0003] The manufacturing technology required for 3D gate-all-around (GAA) transistors is similar to that for 3D FinFET transistors. The main difference lies in the use of multiple nanosheets or nanowires instead of fins to achieve gate current switching control. Currently, the gate current control section of 3D GAA transistors mainly includes nanosheet channels formed by back gate release and fully-all-around HKMG structures.
[0004] The existing method for fabricating 3D GAA transistors involves first growing the source and drain, then releasing the nanosheets, and finally fabricating the gate—a post-gate process. The sharp edges of the nanosheets in 3D GAA transistors fabricated using this method are prone to causing gate voltage breakdown due to high electric fields. Summary of the Invention
[0005] Based on the above analysis, the embodiments of the present invention aim to provide a semiconductor device and its fabrication method and the application of the low-temperature ISSG process, in order to solve the problem that the sharp corners of the nanosheet edges in existing vertical 3D all-around gate transistors are prone to causing high electric fields and gate voltage breakdown.
[0006] On one hand, the present invention provides a method for fabricating a semiconductor device, the method comprising: after releasing the nanosheet structure in a back gate process, using a low-temperature ISSG process to modify the sharp corners of the nanosheet edges into rounded corners.
[0007] Preferably, the reaction temperature of the low-temperature ISSG process is below 600°C.
[0008] Preferably, the method for preparing the released nanosheet structure in the post-gate process includes:
[0009] Provide a base;
[0010] Si / SiGe nanosheet stacked structures and sidewalls are formed on the substrate;
[0011] The inner sidewalls are etched, and the source and drain electrodes are epitaxially grown. A silicon dioxide structure is deposited around the source and drain electrodes.
[0012] Corrosion of the pseudogates in the nanosheet stack structure releases the nanosheet structure.
[0013] Preferably, after using the low-temperature ISSG process to round the sharp corners of the nanosheet edges, the process further includes:
[0014] The ISSG oxide layer on the surface of the nanosheets was removed to obtain nanosheets with smooth edges and surfaces;
[0015] Depositing gates in a nanosheet stacked structure.
[0016] Preferably, the ISSG oxide layer on the surface of the nanosheets is removed by rinsing with hydrofluoric acid.
[0017] Preferably, in the low-temperature ISSG process, the reaction time is 150-200s.
[0018] Preferably, the exhaust gas is combusted simultaneously with the low-temperature ISSG process.
[0019] Preferably, a Si / SiGe nanosheet stacked structure is formed on the substrate, and sidewalls are grown on both sides of the nanosheet stacked structure.
[0020] Preferably, after growing sidewalls on both sides of the nanosheet stacked structure, the process further includes:
[0021] The inner sidewalls are etched, and the source and drain electrodes are epitaxially grown on the outer sides of the two sidewalls, respectively. A silicon dioxide structure is deposited around the source and drain electrodes.
[0022] Secondly, the present invention also provides a semiconductor device obtained according to the above-described preparation method.
[0023] Thirdly, the present invention provides a semiconductor device comprising a nanosheet with rounded edges.
[0024] Preferably, a low-temperature ISSG process is used to modify the sharp corners of the nanosheet edges into rounded corners to obtain nanosheets with rounded edges.
[0025] Preferably, the reaction temperature of the low-temperature ISSG process is below 600°C.
[0026] Preferably, in the low-temperature ISSG process, the reaction time is 150-200s.
[0027] Preferably, the semiconductor device is a vertical 3D all-around gate transistor.
[0028] Fourthly, this invention also provides the application of low-temperature ISSG technology in the modification of sharp corners at the edges of nanosheets, using the low-temperature ISSG process to modify the sharp corners at the edges of nanosheets into rounded corners. Compared with the prior art, this invention can achieve at least one of the following beneficial effects:
[0029] 1. This invention utilizes the ultra-high oxidation capability of in-situ stream gate oxide (ISSG) technology to modify the sharp corners of nanosheets released in the post-gate process (especially for GAA transistors) into rounded corners without affecting the source and drain, thus avoiding gate voltage breakdown caused by high electric field at sharp corners.
[0030] 2. This invention utilizes a low-temperature ISSG process to smooth the edges and surface of nanosheets, thereby obtaining interface states with a low defect density.
[0031] 3. This invention utilizes a low-temperature ISSG process to modify the sharp corners of nanosheets. By controlling the volume ratio of hydrogen and oxygen and the reaction time in the ISSG process, an oxide layer can be formed on the nanosheets even at temperatures below 600°C, thereby modifying the sharp corners of the nanosheets. This overcomes the conventional belief that the ISSG process must be above 900°C to form an oxide layer.
[0032] 4. Since the low-temperature ISSG process of the present invention is carried out in a low-temperature chamber, if the hydrogen in the low-temperature chamber does not react completely, it is easy to cause danger. Therefore, the present invention performs combustion treatment on the exhaust gas while the low-temperature ISSG process is being carried out, so as to ensure that even if there is unreacted hydrogen in the exhaust gas, it can be treated.
[0033] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0034] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0035] Figure 1 This is a schematic diagram of the device structure after forming a Si / SiGe nanosheet stacked structure and sidewalls on the substrate according to the present invention.
[0036] Figure 2 This is a schematic diagram of the device structure after depositing silicon dioxide structures around the source and drain electrodes according to the present invention.
[0037] Figure 3 This is a schematic diagram of the device structure after the nanosheet structure of the present invention is released;
[0038] Figure 4 This is a schematic diagram of the structure of the nanosheet with sharp corners rounded off using the low-temperature ISSG process of this invention.
[0039] Figure label:
[0040] 1-Substrate; 2-Nanosheet; 3-Sidewall; 4-Dummy gate; 5-Source; 6-Drain; 7-Silica structure; 8-ISSG oxide layer. Detailed Implementation
[0041] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0042] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0043] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0044] For existing conventional planar gate transistors, furnace-tube high-temperature thermal oxidation technology is typically used, employing oxygen or water vapor as the oxidant to round off the sharp corners of the nanosheets, thus avoiding gate voltage breakdown caused by the high electric field at the sharp corners. This method requires temperatures above 800°C to grow the oxide film. However, in the post-gate fabrication process of GAA transistors (growing the source and drain first, then fabricating the gate), nanosheet surface treatment is required after nanosheet release. By this time, source and drain epitaxy has already formed, and subsequent processes need to be controlled below 600°C to avoid affecting the source and drain structure. Therefore, the existing furnace-tube high-temperature thermal oxidation technology cannot be used to modify the sharp corners of the nanosheets in GAA transistors.
[0045] Therefore, the present invention provides a method for fabricating a semiconductor device, the method comprising: after releasing the nanosheet structure in a back gate process, using a low-temperature ISSG process to modify the sharp corners of the nanosheet edges into rounded corners.
[0046] Compared with existing technologies, this invention utilizes the ultra-high oxidation capability of in-situ stream gate oxide (ISSG) process to modify the sharp corners of nanosheets released in the post-gate process (especially for GAA transistors) into rounded corners without affecting the source and drain. This avoids the gate voltage breakdown problem caused by the high electric field at the sharp corners and makes the edges and surfaces of the nanosheets smooth, resulting in interface states with a lower defect density.
[0047] It should be noted that the ISSG process is carried out in ISSG equipment, using nitrogen gas for heating. The reaction gas is a mixture of oxygen and hydrogen. Under low pressure and a certain temperature, oxygen and hydrogen react to generate water and high-density gaseous oxygen atoms. Due to the strong oxidizing effect of oxygen atoms, the high-density gaseous oxygen atoms react with silicon nanosheets to form an oxide layer.
[0048] In this invention, the ISSG process includes: placing the device after releasing the nanosheet in the back gate process into the chamber of the ISSG machine, purging nitrogen gas to bring the chamber temperature to the reaction temperature, purging a reaction gas, adjusting the chamber pressure, so that gaseous oxygen atoms react with the nanosheet and form an oxide layer on the surface of the nanosheet. Since the nanosheet is made of silicon, the gaseous oxygen atoms only react with the nanosheet, and other places are dielectrics and will not react with the gaseous oxygen atoms.
[0049] For example, the method for preparing the released nanosheet structure in the post-gate process includes:
[0050] Provide substrate 1;
[0051] A Si / SiGe nanosheet stacked structure and sidewalls 3 are formed on substrate 1; as shown in the figure. Figure 1 As shown; the nanosheet stacked structure includes nanosheets 2 and pseudogates 4 stacked at intervals; specifically, a Si / SiGe nanosheet stacked structure is formed on the substrate 1, and sidewalls 2 are grown on both sides of the nanosheet stacked structure.
[0052] The inner sidewalls are etched, and source electrode 5 and drain electrode 6 are epitaxially grown. A silicon dioxide structure 7 is deposited around source electrode 5 and drain electrode 6, such as... Figure 2 As shown; specifically, the inner sidewalls are etched, and source electrode 5 and drain electrode 6 are epitaxially grown on the outer sides of the two sidewalls respectively, and silicon dioxide structure 7 is deposited around source electrode 5 and drain electrode 6.
[0053] Corrosion of pseudogates in nanosheet stacked structures releases the nanosheet structure; such as... Figure 3As shown.
[0054] In this invention, a low-temperature ISSG process is used to round the sharp corners of the nanosheet edges, such as... Figure 4 As shown, an ISSG oxide layer 8 is formed on the surface of the nanosheet, and the sharp corners of the nanosheet edges are modified into rounded corners.
[0055] For example, after using the low-temperature ISSG process to round the sharp corners of the nanosheet edges, the process further includes:
[0056] Remove the ISSG oxide layer 8 from the surface of the nanosheet to obtain nanosheets with smooth edges and surfaces; specifically, rinse off the ISSG oxide layer with hydrofluoric acid to obtain nanosheets with arc-shaped edges and smooth surfaces.
[0057] Depositing gates in a nanosheet stacked structure.
[0058] It should be noted that the existing ISSG process typically requires a reaction temperature above 900℃ to generate an oxide film. Since this temperature is greater than 600℃, the existing ISSG process cannot be directly used to modify the sharp corners of nanosheets in the back gate process of GAA transistors.
[0059] In this invention, the reaction temperature of the low-temperature ISSG process is below 600°C.
[0060] For example, the reaction temperature of the low-temperature ISSG process is 500-600°C.
[0061] In this invention, during the low-temperature ISSG process, the volume ratio of H2 to O2 is less than or equal to 0.2, more preferably 0.15-0.2, such as 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, etc. In existing ISSG processes, the volume ratio of H2 to O2 is typically 1-2. This invention reduces the hydrogen content in the reaction gas, thereby reducing the water generated in the reaction, resulting in a high oxygen atom density and strong oxidizing power in the final product. This allows the ISSG process to generate an oxide layer even at low temperatures (below 600°C).
[0062] Since the low-temperature ISSG process of this invention is carried out in a low-temperature chamber, if the hydrogen in the low-temperature chamber does not react fully, it can easily lead to danger. Therefore, this invention reduces the hydrogen content to ensure the safety of the low-temperature chamber.
[0063] For example, in the low-temperature ISSG process, the reaction time is 150-200s, such as 160s, 170s, 180s, 190s, etc.
[0064] For example, in the low-temperature ISSG process, the flow rate of H2 is 1.5-2.5 L / min, such as 1.6 L / min, 1.7 L / min, 1.8 L / min, 1.9 L / min, 2.0 L / min, 2.1 L / min, 2.2 L / min, 2.3 L / min, 2.4 L / min, etc.; and the flow rate of O2 is 9-11 L / min, such as 9.5 L / min, 10 L / min, 10.5 L / min, 11 L / min, etc.
[0065] In the low-temperature ISSG process, oxygen atoms react with nanosheets in a low-pressure environment. For example, the reaction pressure in the low-temperature ISSG process is 7-9 Torr, such as 7.5 Torr, 8.0 Torr, 8.5 Torr, 9 Torr, etc.
[0066] To further ensure safety, for example, the exhaust gas is combusted during the ISSG process to ensure that any unreacted hydrogen in the exhaust gas can be removed.
[0067] Secondly, the present invention also provides a semiconductor device prepared by the above-described method. The edges of the nanosheets (channel layer) of the semiconductor device are rounded to avoid gate voltage breakdown caused by high electric fields at sharp corners; the surface of the nanosheets is smooth and has interface states with low defect density.
[0068] Thirdly, the present invention also provides a semiconductor device comprising a nanosheet with rounded edges.
[0069] For example, a low-temperature ISSG process is used to modify the sharp corners of the nanosheet edges into rounded corners to obtain nanosheets with rounded edges.
[0070] For example, the reaction temperature of the low-temperature ISSG process is below 600°C, and more preferably 500-600°C.
[0071] For example, in the low-temperature ISSG process, the volume ratio of H2 to O2 is less than or equal to 0.2, and more preferably 0.15-0.2, such as 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, etc.
[0072] For example, in the low-temperature ISSG process, the reaction time is 150-200s, such as 160s, 170s, 180s, 190s, etc.
[0073] For example, in the low-temperature ISSG process, the flow rate of H2 is 1.5-2.5 L / min, such as 1.6 L / min, 1.7 L / min, 1.8 L / min, 1.9 L / min, 2.0 L / min, 2.1 L / min, 2.2 L / min, 2.3 L / min, 2.4 L / min, etc.; and the flow rate of O2 is 9-11 L / min, such as 9.5 L / min, 10 L / min, 10.5 L / min, 11 L / min, etc.
[0074] For example, in the low-temperature ISSG process, the reaction pressure is 7-9 Torr, such as 7.5 Torr, 8.0 Torr, 8.5 Torr, 9 Torr, etc.
[0075] For example, the semiconductor device is a vertical 3D all-around gate transistor.
[0076] Fourthly, the present invention also provides the application of low-temperature ISSG process in the modification of sharp corners at the edges of nanosheets, using the low-temperature ISSG process to modify the sharp corners at the edges of nanosheets into rounded corners.
[0077] The fabrication method of the vertical 3D all-around gate transistor of the present invention will be further illustrated below through specific embodiments.
[0078] Example 1
[0079] This embodiment provides a method for fabricating a vertical 3D all-around gate transistor, including:
[0080] Step 1: Form a Si / SiGe nanosheet stacked structure on the substrate, and grow sidewalls on both sides of the nanosheet stacked structure;
[0081] Step 2: Etch the inner sidewalls, and epitaxially grow the source and drain electrodes on the outer sides of the two sidewalls respectively. Deposit silicon dioxide structures around the source and drain electrodes.
[0082] Step 3: Corrode the pseudogates in the nanosheet stacked structure to release the nanosheet structure;
[0083] Step 4: Place the device obtained in Step 3 into the chamber of the ISSG instrument, purge with nitrogen to raise the chamber temperature to 600℃, and simultaneously purge with hydrogen and oxygen at a volume ratio of 0.2, a flow rate of H2 of 2 L / min, a flow rate of O2 of 10 L / min, and adjust the chamber pressure to 8 Torr to allow gaseous oxygen atoms to react with the nanosheets for 180 s, generating an oxide layer on the nanosheet surface; while the ISSG process is underway, the exhaust gas is combusted.
[0084] Step 5: Rinse off the ISSG oxide layer with hydrofluoric acid to obtain nanosheets with smooth edges and surfaces;
[0085] Step 6: Deposit the gate in the nanosheet stack structure.
[0086] The vertical 3D all-around gate transistor prepared in Example 1 was tested, and no gate voltage breakdown problem was observed at a gate voltage of 1.1V; the surface defect density of the gate nanosheet was less than 1*10. 11 atom / cm 2 .
[0087] Example 2
[0088] This embodiment provides a method for fabricating a vertical 3D all-around gate transistor, including:
[0089] Step 1: Form a Si / SiGe nanosheet stacked structure on the substrate, and grow sidewalls on both sides of the nanosheet stacked structure;
[0090] Step 2: Etch the inner sidewalls, and epitaxially grow the source and drain electrodes on the outer sides of the two sidewalls respectively. Deposit silicon dioxide structures around the source and drain electrodes.
[0091] Step 3: Corrode the pseudogates in the nanosheet stacked structure to release the nanosheet structure;
[0092] Step 4: Place the device obtained in Step 3 into the chamber of the ISSG instrument, purge with nitrogen to raise the chamber temperature to 550°C, and simultaneously purge with hydrogen and oxygen at a volume ratio of 0.18, a flow rate of H2 of 2.5 L / min, a flow rate of O2 of 10.5 L / min, and adjust the chamber pressure to 8.5 Torr to allow gaseous oxygen atoms to react with the nanosheets for 160 s, generating an oxide layer on the nanosheet surface; while the ISSG process is underway, the exhaust gas is combusted.
[0093] Step 5: Rinse off the ISSG oxide layer with hydrofluoric acid to obtain nanosheets with smooth edges and surfaces;
[0094] Step 6: Deposit the gate in the nanosheet stack structure.
[0095] The vertical 3D all-around gate transistor prepared in Example 2 was tested, and no gate voltage breakdown problem was observed at a gate voltage of 1.15V; the surface defect density of the gate nanosheet was less than 1*10⁻⁶. 11 atom / cm 2 .
[0096] Example 3
[0097] This embodiment provides a method for fabricating a vertical 3D all-around gate transistor, including:
[0098] Step 1: Form a Si / SiGe nanosheet stacked structure on the substrate, and grow sidewalls on both sides of the nanosheet stacked structure;
[0099] Step 2: Etch the inner sidewalls, and epitaxially grow the source and drain electrodes on the outer sides of the two sidewalls respectively. Deposit silicon dioxide structures around the source and drain electrodes.
[0100] Step 3: Corrode the pseudogates in the nanosheet stacked structure to release the nanosheet structure;
[0101] Step 4: Place the device obtained in Step 3 into the chamber of the ISSG instrument, purge with nitrogen to raise the chamber temperature to 500°C, and simultaneously purge with hydrogen and oxygen at a volume ratio of 0.19, a flow rate of H2 of 1.5 L / min, a flow rate of O2 of 9 L / min, and adjust the chamber pressure to 7 Torr. This allows gaseous oxygen atoms to react with the nanosheets for 190 s, generating an oxide layer on the nanosheet surface. Simultaneously with the ISSG process, the exhaust gas is combusted.
[0102] Step 5: Rinse off the ISSG oxide layer with hydrofluoric acid to obtain nanosheets with smooth edges and surfaces;
[0103] Step 6: Deposit the gate in the nanosheet stack structure.
[0104] The vertical 3D all-around gate transistor prepared in Example 3 was tested, and no gate voltage breakdown problem was observed at a gate voltage of 1.0V; the surface defect density of the gate nanosheet was less than 1*10. 11 atom / cm 2 .
[0105] Comparative Example 1
[0106] This comparative example provides a method for fabricating a vertical 3D all-around gate transistor, including:
[0107] Step 1: Form a Si / SiGe nanosheet stacked structure on the substrate, and grow sidewalls on both sides of the nanosheet stacked structure;
[0108] Step 2: Etch the inner sidewalls, and epitaxially grow the source and drain electrodes on the outer sides of the two sidewalls respectively. Deposit silicon dioxide structures around the source and drain electrodes.
[0109] Step 3: Corrode the pseudogates in the nanosheet stacked structure to release the nanosheet structure;
[0110] Step 4: Deposit the gate in the nanosheet stack structure.
[0111] Testing of the vertical 3D all-around gate transistor prepared in Comparative Example 1 revealed gate voltage breakdown; the surface defect density of the gate nanosheets was greater than 1*102.11 atom / cm 2 .
[0112] Comparative Example 2
[0113] This comparative example provides a method for fabricating a vertical 3D all-around gate transistor, including:
[0114] Step 1: Form a Si / SiGe nanosheet stacked structure on the substrate, and grow sidewalls on both sides of the nanosheet stacked structure;
[0115] Step 2: Etch the inner sidewalls, and epitaxially grow the source and drain electrodes on the outer sides of the two sidewalls respectively. Deposit silicon dioxide structures around the source and drain electrodes.
[0116] Step 3: Corrode the pseudogates in the nanosheet stacked structure to release the nanosheet structure;
[0117] Step 4: Place the device obtained in Step 3 into the chamber of the ISSG instrument, purge with nitrogen to raise the chamber temperature to 900℃, and simultaneously purge with hydrogen and oxygen at a volume ratio of 1.8, a flow rate of H2 of 2 L / min and an O2 flow rate of 10 L / min, and adjust the chamber pressure to 8 Torr to allow gaseous oxygen atoms to react with the nanosheets and generate an oxide layer on the surface of the nanosheets.
[0118] Step 5: Rinse off the ISSG oxide layer with hydrofluoric acid;
[0119] Step 6: Deposit the gate in the nanosheet stack structure.
[0120] In this comparative example, because the ISSG process temperature is higher than 600°C, the ISSG process in step 4 damages the source and drain that have already formed in the device, and ultimately it is impossible to fabricate a complete vertical 3D all-around gate transistor.
[0121] Analysis of results from examples and comparative examples:
[0122] A comparison of the results of Example 1 and Comparative Example 1 shows that the method of the present invention uses the ISSG process to modify the sharp corners of the nanosheets into rounded corners, thus avoiding the gate voltage breakdown problem caused by the high electric field at the sharp corners; at the same time, the ISSG process makes the surface of the nanosheets smooth, giving the nanosheets a low defect density interface state.
[0123] As can be seen from the comparison of the results of Example 1 and Comparative Example 2, this application abandons the reaction temperature of conventional ISSG process and applies low temperature ISSG process to modify the sharp corners of nanosheets in vertical 3D all-around gate transistor, overcoming the technical bias that conventional ISSG process must be above 900°C to form oxide layer.
[0124] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: after releasing the nanosheet structure in the post-gate process, using a low-temperature ISSG process to modify the sharp corners of the nanosheet edges into rounded corners; The method of using a low-temperature ISSG process to round off the sharp corners of the nanosheets includes: forming an ISSG oxide layer on the surface of the nanosheets using a low-temperature ISSG process with a reaction temperature below 600°C, and then removing the ISSG oxide layer from the surface of the nanosheets to round off the sharp corners of the nanosheets; and, when forming an ISSG oxide layer on the surface of the nanosheets, controlling the volume ratio of hydrogen to oxygen in the ISSG process to be less than or equal to 0.2, and the reaction time to be 150-200s.
2. The preparation method according to claim 1, characterized in that, The method for preparing the released nanosheet structure in the post-gate process includes: Provide a base; Si / SiGe nanosheet stacked structures and sidewalls are formed on the substrate; The inner sidewalls are etched, and the source and drain electrodes are epitaxially grown. A silicon dioxide structure is deposited around the source and drain electrodes. Corrosion of the pseudogates in the nanosheet stack structure releases the nanosheet structure.
3. The preparation method according to claim 1, characterized in that, The process of rounding the sharp corners of the nanosheet edges using a low-temperature ISSG process also includes: Depositing gates in a nanosheet stacked structure.
4. The preparation method according to claim 1, characterized in that, The ISSG oxide layer on the surface of the nanosheets was removed by rinsing with hydrofluoric acid.
5. The preparation method according to claim 1, characterized in that, While the low-temperature ISSG process is being carried out, the exhaust gas is also being combusted.
6. The preparation method according to claim 2, characterized in that, A Si / SiGe nanosheet stacked structure is formed on the substrate, and sidewalls are grown on both sides of the nanosheet stacked structure.
7. The preparation method according to claim 6, characterized in that, After growing sidewalls on both sides of the nanosheet stacked structure, the process further includes: The inner sidewalls are etched, and the source and drain electrodes are epitaxially grown on the outer sides of the two sidewalls, respectively. A silicon dioxide structure is deposited around the source and drain electrodes.
8. A semiconductor device obtained by the preparation method according to any one of claims 1-7.
9. A semiconductor device, characterized in that, Including nanosheets with rounded edges; The sharp corners of the nanosheets were rounded using a low-temperature ISSG process to obtain nanosheets with rounded edges; The method of using a low-temperature ISSG process to round off the sharp corners of the nanosheets includes: forming an ISSG oxide layer on the surface of the nanosheets using a low-temperature ISSG process with a reaction temperature below 600°C, and then removing the ISSG oxide layer from the surface of the nanosheets, thereby rounding off the sharp corners of the nanosheets. Furthermore, when forming an ISSG oxide layer on the surface of the nanosheet, the volume ratio of hydrogen to oxygen in the ISSG process is controlled to be less than or equal to 0.2, and the reaction time is 150-200s.
10. The semiconductor device according to claim 9, characterized in that, The semiconductor device is a vertical 3D fully surround gate transistor.
11. The application of low-temperature ISSG process in the modification of sharp corners at the edges of nanosheets, characterized in that, The sharp edges of the nanosheets were rounded using a low-temperature ISSG process. The method of using a low-temperature ISSG process to round off the sharp corners of the nanosheets includes: forming an ISSG oxide layer on the surface of the nanosheets using a low-temperature ISSG process with a reaction temperature below 600°C, and then removing the ISSG oxide layer from the surface of the nanosheets, thereby rounding off the sharp corners of the nanosheets. Furthermore, when forming an ISSG oxide layer on the surface of the nanosheet, the volume ratio of hydrogen to oxygen in the ISSG process is controlled to be less than or equal to 0.2, and the reaction time is 150-200s.
Citation Information
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Stacked nanosheet ring gate transistor and preparation method thereof
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