protection circuit

Abstract

A protection circuit is disclosed. The protection circuit is coupled to a solder pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor and a second transistor, both having a first conductivity type, connected in series between the solder pad and a ground terminal. The trigger circuit detects whether a transient event occurs on the solder pad. The discharge circuit is coupled between the solder pad and the ground terminal and is controlled by the trigger circuit. When a transient event occurs on the solder pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the solder pad and the ground terminal.

Description

Technical Field

[0001] This invention relates to a protection circuit, and more particularly to a protection circuit with high voltage tolerance and the ability to quickly provide a discharge path. Background Technology

[0002] With the development of semiconductor technology in integrated circuits, the size of semiconductor devices has shrunk to the sub-micron level, improving the performance and processing speed of integrated circuits. However, the reduction in device size makes semiconductor devices more susceptible to damage from large currents caused by voltage spikes. Therefore, when a large current / voltage occurs on the pads used for input / output connections of an integrated circuit for a very short period of time, a protection circuit that can quickly respond to the large current / voltage and provide a stable discharge path is needed. For example, electrostatic discharge (ESD) protection circuits, transient voltage suppressors (TVS), and other protective devices or circuits can provide a discharge path to protect semiconductor devices from damage by large currents. Therefore, the discharge efficiency (i.e., protection capability) of such protective devices or circuits is crucial. Summary of the Invention

[0003] In view of this, the present invention proposes a protection circuit. The protection circuit is coupled to a solder pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor and a second transistor, both having a first conductivity type, connected in series between the solder pad and a ground terminal. The trigger circuit detects whether a transient event occurs on the solder pad. The discharge circuit is coupled between the solder pad and the ground terminal and is controlled by the trigger circuit. When a transient event occurs on the solder pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the solder pad and the ground terminal. Attached Figure Description

[0004] Figure 1 This represents a protection circuit according to an embodiment of the present invention.

[0005] Figure 2 This represents a protection circuit according to another embodiment of the present invention.

[0006] Figure 3A and Figure 3B express Figure 2 A schematic diagram of the operation of the protection circuit.

[0007] Figure 4 This represents a protection circuit according to another embodiment of the present invention.

[0008] Figure 5 express Figure 4 Parasitic NPN bipolar junction transistors in the protection circuit.

[0009] Figure 6 This represents a protection circuit according to another embodiment of the present invention.

[0010] Figure 7A and Figure 7B express Figure 6 A schematic diagram of the operation of the protection circuit.

[0011] Figure 8 This represents a protection circuit according to another embodiment of the present invention.

[0012] Figure 9 express Figure 8 Parasitic NPN bipolar junction transistors in the protection circuit.

[0013] Figure 10A This refers to an electronic circuit according to an embodiment of the present invention, which has a protection circuit according to any embodiment of the present invention.

[0014] Figure 10B This refers to an electronic circuit according to another embodiment of the present invention, which has a protection circuit according to any embodiment of the present invention.

[0015] Icon labels:

[0016] 1, 1A, 1B, 1C, 1D: Protection circuit

[0017] 10: Trigger circuit

[0018] 11: Discharge Circuit

[0019] 12: Solder pad

[0020] 13A, 13B: Electronic devices

[0021] 20, 21, 23: NMOS transistors

[0022] 22: Resistor

[0023] 40: NPN bipolar junction transistor (BJT)

[0024] 60, 61, 63: NMOS transistors

[0025] 62: Resistor

[0026] 80: NPN bipolar junction transistor (BJT)

[0027] 100: Core Circuit

[0028] 1000: Electronic components or circuits

[0029] 600, 610, 630: Drain (first electrode)

[0030] 601, 611, 631: Source electrode (second electrode terminal)

[0031] 602, 612, 632: Gate (control electrode)

[0032] 633: Base

[0033] GND: Ground terminal

[0034] N20, N21, N60: Nodes

[0035] P30: Discharge Path

[0036] R30, R31, R60, R61: On-resistance

[0037] V30, V60: Trigger voltage

[0038] VCC, VDD: Supply voltage Detailed Implementation

[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, a preferred embodiment is described below in detail with reference to the accompanying drawings.

[0040] Figure 1 This illustrates a protection circuit according to an embodiment of the present invention. (See also...) Figure 1 In order to explain in detail, Figure 1 In addition to displaying the protection circuit 1, pad 12 is also shown. For example... Figure 1 As shown, the protection circuit 1 is coupled to the solder pad 12 and includes a trigger circuit 10 and a discharge circuit 11. Both the trigger circuit 10 and the discharge circuit 11 are coupled between the solder pad 12 and the ground terminal GND.

[0041] When the protection circuit 1 operates in a normal operating mode, a supply voltage is provided to the solder pad 12. At this time, the trigger circuit 10 controls the discharge circuit 11 to not provide any discharge path between the solder pad 12 and the ground terminal GND. When the protection circuit 1 is not operating in a normal operating mode, the solder pad 12 does not receive any supply voltage. At this time, the trigger circuit 10 detects whether a transient event has occurred on the solder pad 12. When a transient event is detected on the solder pad 12, the trigger circuit 10 generates a signal or voltage to control or trigger the discharge circuit 11 to provide a discharge path between the solder pad 12 and the ground terminal GND.

[0042] In this embodiment, the transient event can be an event involving a large voltage or a large current. For example, a transient event can be an electrostatic discharge (ESD) event or a surge event. In one embodiment, the protection circuit 1 can be an electrostatic discharge (ESD) protection circuit or a transient voltage suppressor (TVS).

[0043] Figure 2 This represents a protection circuit according to another embodiment of the present invention. Figure 1 The protection circuit 1 can Figure 2 This is achieved using a 1A protection circuit. (See attached image.) Figure 2 The trigger circuit 10 of the protection circuit 1A may include transistors 20 and 21 and resistor 22. Transistors 20 and 21 have the same conductivity type, and each has three terminals: a first terminal, a second terminal, and a control terminal. In this embodiment, transistors 20 and 21 are both implemented as N-type metal-oxygen-semiconductor (NMOS) transistors, meaning that transistors 20 and 21 are of the N-type conductivity type. The first terminal, second terminal, and control terminal of each of transistors 20 and 21 are respectively the drain, source, and gate of the NMOS transistor. Figure 2 As shown. The drain (first terminal) 200 of NMOS transistor 20 is coupled to pad 12, its source (second terminal) 201 is coupled to node N20, and its gate (control terminal) 202 is coupled to node N21. The drain 210 of NMOS transistor 21 is coupled to node N20, its source 211 is grounded (GND), and its gate 212 is coupled to node N21. According to the above connection architecture, NMOS transistors 20 and 21 are connected in series between pad 12 and ground (GND). Resistor 22 is coupled between node N21 and ground (GND).

[0044] like Figure 2 As shown, the discharge circuit 11 includes a transistor 23. The transistor 23 has three terminals: a first terminal, a second terminal, and a control terminal. In this embodiment, the transistor 23 is also implemented as an NMOS transistor. The first terminal, second terminal, and control terminal of the transistor 23 are the drain, source, and gate of the NMOS transistor 23, respectively. The drain 230 of the NMOS transistor 23 is coupled to the pad 12, its source 231 is grounded to GND, and its gate 232 is coupled to node N20. Based on the above connection architecture, the NMOS transistor 23 is also coupled between the pad 12 and the ground terminal GND.

[0045] In embodiments of the present invention, the voltage withstand capability of NMOS transistor 23 is higher than that of NMOS transistors 20 and 21. In one example, NMOS transistors 20 and 23 are high-voltage transistors, and the voltage withstand capability of NMOS transistor 23 is higher than that of NMOS transistor 20. For example, NMOS transistor 20 is a 20V transistor, NMOS transistor 21 is a 5V transistor, and NMOS transistor 23 is a 24V transistor; however, the present invention is not limited thereto.

[0046] In one embodiment, NMOS transistors 20 and 23 can be implemented as high-voltage transistors by increasing the doped region size of their drains (e.g., thickness, lateral diffusion distance).

[0047] In one embodiment, the channel widths of NMOS transistors 20 and 21 are approximately several hundred micrometers (µm), while the channel width of NMOS transistor 23 is approximately 100 to 150 kilomicrometers (kµm). The resistance value of resistor 22 is approximately in the range of 1 to 10 kiloohms (kohm).

[0048] The following will explain the detailed operation of protection circuit 1A.

[0049] See Figure 3A When the protection circuit 1A operates in a normal operating mode, a supply voltage VDD is provided to the pad 12. In this embodiment, the supply voltage VDD is, for example, a voltage of 24V. At this time, since resistor 22 is coupled between node N21 and ground GND, the voltage at node N21 is at a low level relative to the supply voltage VDD, that is, the voltages at the gates 202 and 212 of NMOS transistors 20 and 21 are both at a low level. Based on the low level voltages at gates 202 and 212, NMOS transistors 20 and 21 are both turned off. Figure 3A In subsequent diagrams, the off transistors will be marked with "(OFF)". Since both NMOS transistors 20 and 21 are off, the voltage at node N20 is at a low level relative to the supply voltage VDD, meaning the voltage at the gate 232 of NMOS transistor 23 is also at a low level, which causes NMOS transistor 23 to also be off.

[0050] As described above, in normal operating mode, all NMOS transistors coupled between the solder pad 12 and the ground terminal GND within the protection circuit 1A are in the off state. In other words, the protection circuit 1A of this invention cuts off any discharge path between the solder pad 12 and the ground terminal GND. Therefore, in normal operating mode, the protection circuit 1A will not cause unnecessary leakage current, avoiding unnecessary power consumption caused by the setting of the protection circuit 1A.

[0051] See Figure 3B When protection circuit 1A is not in normal operating mode, the supply voltage VDD is not provided to pad 12, i.e., pad 12 is in a floating state, or the voltage of pad 12 is equal to 0V. When a transient event (e.g., ESD event or surge event) occurs on pad 12, the voltage of pad 12 increases instantaneously. There is a parasitic capacitance between the drain 200 and gate 202 of transistor 20, which forms an RC circuit with resistor 22. Through the coupling effect of the parasitic capacitance between drain 200 and gate 202, the voltage at node N21 increases instantaneously with the voltage of pad 12. At this time, in response to the instantaneous increase in voltage at node N21, NMOS transistors 20 and 21 are instantaneously turned on. Figure 3B In subsequent illustrations, the conducting transistors will be marked with "(ON)".

[0052] Due to the conduction of NMOS transistors 20 and 21, each NMOS transistor 20 and 21 has an on-resistance R30 and R31, respectively. The on-resistances R30 and R31 form a voltage divider. This voltage divider divides the voltage difference between the pad 12 and the ground terminal GND to generate a trigger voltage V30 at node N20. The trigger voltage V30 generated by the voltage divider operation has a high-level voltage to turn on (ON) NMOS transistor 23. Therefore, a discharge path P30 is formed between the pad 12 and the ground terminal GND, allowing the large current charge accompanying transient events on the pad 12 to be conducted to the ground terminal GND through this discharge path P30.

[0053] As described above, when a transient event occurs on the pad 12, the trigger circuit 10 can quickly generate a high-level trigger voltage V30 through the operation of NMOS transistors 20 and 21 and resistor 22, so as to trigger the discharge circuit 11 to provide a discharge path P30, so that a large amount of charge on the pad 12 can be quickly conducted to the ground terminal GND through the discharge path P30, thereby protecting the components in other circuits coupled to the pad 12 from being damaged by large current.

[0054] exist Figure 2 In the embodiments, although not in Figure 2 As shown, the base of NMOS transistor 23 can be connected to its source 231.

[0055] Figure 4 This represents a protection circuit according to another embodiment of the present invention. Figure 1 The protection circuit 1 can Figure 4 The protection circuit 1B is used to achieve this. Figure 4 The circuit architecture of the protection circuit 1B and Figure 2 The circuit architecture of the protection circuit 1A is roughly the same. See [reference needed]. Figure 4 The difference between protection circuits 1B and 1A is that the base of NMOS transistor 23 is 233. The base of NMOS transistor 23 is coupled to node N21, that is, the base 233 is coupled to the gates 202 and 212 of NMOS transistors 20 and 21.

[0056] because Figure 4 and Figure 5 The circuit architecture of the protection circuit 1B and Figure 2 The circuit architecture of protection circuit 1B is roughly the same as that of protection circuit 1A. Therefore, the operation of protection circuit 1B is also roughly the same as that of protection circuit 1A. Please refer to the above-mentioned... Figure 3A and Figure 3B The same operation will be omitted in the following text; only the operation of NMOS transistor 23 will be specifically described.

[0057] See Figure 4 The drain 230, source 231, and base 233 of NMOS transistor 23 form a parasitic NPN bipolar junction transistor (BJT) 40. The drain 230, source 231, and base 233 of NMOS transistor 23 serve as the collector (C), emitter (E), and base (B) of the NPN BJT 40, respectively. When protection circuit 1B operates in a normal operating mode, the voltage at node N21 is at a low level relative to the supply voltage VDD. Based on the low voltage level at node N21 and the source 231 being coupled to ground GND, the NPN BJT 40 is turned off. When protection circuit 1B is not in a normal operating mode and a transient event occurs on pad 12, the base-emitter voltage (VDD) of the NPN BJT 40 is high due to the high voltage level at node N21. BE The voltage is greater than 0.7V, which causes the NPN type BJT 40 to conduct. At this time, the charge of the large current accompanying the transient event on the pad 12 is also conducted to the ground terminal GND through the conducting NPN type BJT 40.

[0058] Based on the above, Figure 4 In the protection circuit 1B, the base 233 of the NMOS transistor 23 is coupled to node N21. Therefore, when a transient event occurs on the pad 12, the parasitic NPN BJT 40 can quickly turn on in response to the high level voltage of node N21, thus improving the overall discharge capability of the NMOS transistor 23.

[0059] Figure 6 This represents a protection circuit according to another embodiment of the present invention. Figure 1 The protection circuit 1 can Figure 6 This is achieved through the protection circuit 1C. See [reference needed]. Figure 6 The trigger circuit 10 of the protection circuit 1C may include transistors 60 and 61 and resistor 62. Transistors 60 and 61 have the same conductivity type, and each has three terminals: a first terminal, a second terminal, and a control terminal. In this embodiment, transistors 60 and 61 are both implemented as NMOS transistors, meaning their conductivity type is N-type. The first terminal, second terminal, and control terminal of each of transistors 60 and 61 are respectively the drain, source, and gate of the NMOS transistor. Figure 6 As shown. The drain 600 of NMOS transistor 60 is coupled to pad 12, and its source 601 is coupled to node N60. The drain 610 of NMOS transistor 61 is coupled to node N60, its source 611 is grounded (GND), and its gate 612 is coupled to power supply (T60). According to the above connection architecture, NMOS transistors 60 and 61 are connected in series between pad 12 and ground (GND). Resistor 62 is coupled between the gate 602 of NMOS transistor 60 and node N60.

[0060] like Figure 6 As shown, the discharge circuit 11 includes a transistor 63. The transistor 63 has three terminals: a first terminal, a second terminal, and a control terminal. In this embodiment, the transistor 63 is also implemented as an NMOS transistor. The first terminal, second terminal, and control terminal of the transistor 63 are the drain, source, and gate of the NMOS transistor 63, respectively. The drain 630 of the NMOS transistor 63 is coupled to the pad 12, its source 631 is grounded (GND), and its gate 632 is coupled to node N60. Based on the above connection architecture, the NMOS transistor 63 is also coupled between the pad 12 and the ground terminal GND.

[0061] In embodiments of the present invention, the voltage withstand capability of NMOS transistor 63 is higher than that of NMOS transistors 60 and 61. In one example, NMOS transistors 60 and 63 are high-voltage transistors, and the voltage withstand capability of NMOS transistor 63 is higher than that of NMOS transistor 60. For example, NMOS transistor 60 is a 20V transistor, NMOS transistor 61 is a 5V transistor, and NMOS transistor 63 is a 24V transistor.

[0062] In one embodiment, NMOS transistors 60 and 63 may be implemented as high-voltage transistors by increasing the doped region size of their drains (e.g., vertical doping depth or lateral diffusion distance), but the invention is not limited thereto.

[0063] In one embodiment, the channel widths of NMOS transistors 60 and 61 are approximately several hundred micrometers (µm), while the channel width of NMOS transistor 63 is approximately 100 to 150 kilomicrometers (kµm). The resistance value of resistor 62 is approximately in the range of 1 to 10 kiloohms (kohm).

[0064] The following will explain the detailed operation of protection circuit 1C.

[0065] See Figure 7A When the protection circuit 1C operates in a normal operating mode, a supply voltage VDD is provided to the pad 12, and another supply voltage VCC is provided to the power supply terminal T60. In this embodiment, the supply voltage VDD is, for example, a voltage of 24V, and the supply voltage VCC is, for example, a voltage of 5V. At this time, since the 5V supply voltage VCC is provided to the gate 612 of the NMOS transistor 61 through the power supply terminal T60, the NMOS transistor 61 is always in the ON state. Due to the ON NMOS transistor 61, the voltage at node N60 is at a low level relative to the supply voltage VDD, that is, the voltage at the gate 632 of the NMOS transistor 63 is at a low level. Based on the low level voltage at gate 632, the NMOS transistor 63 is OFF. In addition, due to the resistor 62 coupled between the gate 602 of the NMOS transistor 60 and node N60, the voltage at gate 602 is at a low level relative to the supply voltage VDD. Based on the low level voltage at gate 602, the NMOS transistor 60 is OFF.

[0066] As described above, under normal operating conditions, NMOS transistors 60 and 63, coupled between pad 12 and ground GND, are in the off state within protection circuit 1C. In other words, protection circuit 1C in this invention cuts off any discharge path between pad 12 and ground GND. Therefore, under normal operating conditions, protection circuit 1C will not cause unnecessary leakage current, avoiding unnecessary power consumption caused by its configuration.

[0067] See Figure 7BWhen the protection circuit 1C is not in normal operating mode, the supply voltage VDD is not provided to pad 12, and the supply voltage VCC is not provided to power supply terminal T60. That is, pad 12 and / or power supply terminal T60 are in a floating state, or the voltage of pad 12 and / or power supply terminal T60 is equal to 0V. When a transient event (e.g., an ESD event or a surge event) occurs on pad 12, the voltage of pad 12 increases instantaneously. There is a parasitic capacitance between the drain 600 and gate 602 of transistor 60, which forms an RC circuit with resistor 62. Through the coupling effect of the parasitic capacitance between drain 600 and gate 602, the voltage of gate 602 of NMOS transistor 60 increases instantaneously with the voltage of pad 12. At this time, in response to the instantaneous increase in the voltage of gate 602, NMOS transistor 60 is turned on. In addition, since the power supply terminal T60 is in a floating state or the voltage of the power supply terminal T60 is equal to 0V, the NMOS transistor 61 is in a fully conducting state or a weakly conducting state (ON).

[0068] Due to the conduction of NMOS transistors 60 and 61, each NMOS transistor 60 and 61 has an on-resistance R60 and R61, respectively. The on-resistances R60 and R61 form a voltage divider. This voltage divider divides the voltage difference between the pad 12 and the ground terminal GND to generate a trigger voltage V60 at node N60. The trigger voltage V60 generated by the voltage divider operation has a high-level voltage to turn on NMOS transistor 63. Therefore, a discharge path P60 is formed between the pad 12 and the ground terminal GND, allowing the large current charge accompanying transient events on the pad 12 to be conducted to the ground terminal GND through this discharge path P60.

[0069] As described above, when a transient event occurs on the pad 12, the trigger circuit 10 can quickly generate a high-level trigger voltage V60 through the operation of NMOS transistors 60 and 61 and resistor 62, so as to trigger the discharge circuit 11 to provide a discharge path P60, so that a large amount of charge on the pad 12 can be quickly conducted to the ground terminal GND through the discharge path P60, thereby protecting the components in other circuits coupled to the pad 12 from being damaged by large current.

[0070] exist Figure 6 In the embodiments, although not in Figure 6 As shown in the figure, the base of NMOS transistor 63 can be connected to its source 631.

[0071] Figure 8 This represents a protection circuit according to another embodiment of the present invention. Figure 1 The protection circuit 1 can Figure 8 The protection circuit is implemented using 1D. Figure 8 The protection circuit 1D circuit architecture and Figure 6The protection circuit 1C has a roughly the same circuit architecture. See [reference needed]. Figure 8 The difference between protection circuits 1D and 1C is that the base (bulk) 633 of NMOS transistor 63 is coupled to node N60, that is, the base 633 is coupled to the gate 632 of NMOS transistor 63.

[0072] because Figure 8 The protection circuit 1D circuit architecture and Figure 6 The circuit architecture of protection circuit 1C is roughly the same; therefore, the operation of protection circuit 1D is also roughly the same as that of protection circuit 1C. Please refer to the above information regarding... Figure 7A and Figure 7B The same operation will be omitted in the following text; only the operation of NMOS transistor 63 will be specifically described.

[0073] See Figure 8 and Figure 9 The drain 630, source 631, and base 633 of NMOS transistor 63 form a parasitic NPN bipolar junction transistor (BJT) 80. The drain 630, source 631, and base 633 of NMOS transistor 63 serve as the collector (C), emitter (E), and base (B) of the NPN BJT 80, respectively. When protection circuit 1D operates in a normal operating mode, the voltage at node N60 is at a low level relative to the supply voltage VDD. Based on the low voltage level at node N60 and the source 631 being coupled to ground GND, the NPN BJT 80 is turned off. When protection circuit 1D is not in a normal operating mode and a transient event occurs on pad 12, the base-emitter voltage (V60) of the NPN BJT 80 is high due to the high level of the trigger voltage V60 at node N60. BE The voltage is greater than 0.7V, which turns on the NPN BJT 80. At this time, the charge of the large current accompanying the transient event on the pad 12 is also conducted to the ground terminal GND through the turned-on NPN BJT 80.

[0074] Based on the above, Figure 8 In the protection circuit 1D, the base 633 of the NMOS transistor 63 is coupled to node N60. Therefore, when a transient event occurs on the pad 12, the parasitic NPN BJT 80 can react to the high level voltage of node N60 and turn on quickly, improving the overall discharge capability of the NMOS transistor 63.

[0075] Figure 10A This describes an electronic circuit according to an embodiment of the present invention. (See also...) Figure 10A The electronic device 13A includes a core circuit 100, solder pads 12, and the present invention. Figure 1The protection circuit 1 shown is shown. This protection circuit 1 can... Figure 2 , Figure 4 , Figure 6 , Figure 8 This can be achieved using any of the protection circuits 1A to 1D shown. Figure 10A In this embodiment, the protection circuit 1 is disposed outside the core circuit 100. When a transient event occurs at the solder pad 12, the protection circuit 1 provides or triggers a discharge path between the solder pad 12 and the ground terminal GND. A large amount of charge on the solder pad 12 can be quickly conducted to the ground terminal GND through this discharge path, thereby protecting the components or circuits within the core circuit 100 from damage by the large current accompanying the transient event.

[0076] In other embodiments, the protection circuit 1 may be located inside the core circuit 100. For example... Figure 10B As shown, a protection circuit 1 and other electronic components or circuits 1000 are provided within the core circuit 100 of electronic device 13B. When a transient event occurs on the solder pad 12, the protection circuit 1 provides or triggers a discharge path between the solder pad 12 and the ground terminal GND. A large amount of charge on the solder pad 12 can be quickly conducted to the ground terminal GND through this discharge path, thereby protecting the electronic components or circuits 1000 within the core circuit 100 from damage by the large current accompanying the transient event.

[0077] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims of this application.

Claims

1. A protection circuit, characterized in that, Coupled to a solder pad, including: A trigger circuit includes a first transistor and a second transistor, both having a first conductivity type, connected in series between the solder pad and a ground terminal, wherein the trigger circuit detects whether a transient event occurs on the solder pad; and A discharge circuit is coupled between the solder pad and the ground terminal and is controlled by the trigger circuit; in: When the transient event occurs on the solder pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the solder pad and the ground terminal; The discharge circuit includes a third transistor coupled between the pad and the ground terminal and having the first conductivity type; The first conductivity type is N-type; The trigger circuit also includes a resistor; The first transistor has a first terminal coupled to the bonding pad, a second terminal coupled to a first node, and a control terminal coupled to a second node; The second transistor has a first terminal coupled to the first node, a second terminal coupled to the ground terminal, and a control terminal coupled to the second node; The third transistor has a first terminal coupled to the bonding pad, a second terminal coupled to the ground terminal, and a control terminal coupled to the first node, and the trigger voltage is generated at the first node; and The resistor is coupled between the second node and the ground terminal.

2. The protection circuit according to claim 1, characterized in that, When the transient event occurs on the pad, both the first transistor and the second transistor are turned on.

3. The protection circuit according to claim 1, characterized in that, The third transistor also has a base, and the base of the third transistor is coupled to the second node.

4. The protection circuit according to claim 1 or 3, characterized in that, When a supply voltage is received on the pad, the first transistor, the second transistor, and the third transistor are all turned off.

5. A protection circuit, characterized in that, Coupled to a solder pad, including: A trigger circuit includes a first transistor and a second transistor, both having a first conductivity type, connected in series between the solder pad and a ground terminal, wherein the trigger circuit detects whether a transient event occurs on the solder pad; and A discharge circuit is coupled between the solder pad and the ground terminal and is controlled by the trigger circuit; in: When the transient event occurs on the solder pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the solder pad and the ground terminal; The discharge circuit includes a third transistor coupled between the pad and the ground terminal and having the first conductivity type; The trigger circuit also includes a resistor; The first transistor has a first terminal coupled to the bonding pad, a second terminal coupled to a first node, and a control terminal; The second transistor has a first terminal coupled to the first node, a second terminal coupled to the ground terminal, and a control terminal coupled to a power supply terminal; The third transistor has a first terminal coupled to the bonding pad, a second terminal coupled to the ground terminal, and a control terminal coupled to the first node, and the trigger voltage is generated at the first node; and The resistor is coupled between the control terminal of the first transistor and the first node.

6. The protection circuit according to claim 5, characterized in that, The third transistor also has a base, and the base of the third transistor is coupled to the first node.

7. The protection circuit according to claim 5 or 6, characterized in that, When a first supply voltage is received on the pad and a second supply voltage is received at the power supply terminal, the first transistor and the third transistor are turned off, and the second transistor is turned on.

8. The protection circuit according to claim 7, characterized in that, The first supply voltage is greater than the second supply voltage.

9. The protection circuit according to claim 1 or 5, characterized in that, When the transient event occurs on the pad, the first transistor, the second transistor, and the third transistor are all turned on.

10. The protection circuit according to claim 1 or 5, characterized in that, The third transistor has a higher voltage withstand capability than the first transistor and the second transistor.

11. The protection circuit according to claim 1 or 5, characterized in that, The first transistor has a higher voltage withstand capability than the second transistor.

12. The protection circuit according to claim 1 or 5, characterized in that, The protection circuit is a transient voltage suppressor.

13. The protection circuit according to claim 5, characterized in that, The first conductivity type is N-type.

Images