Input overvoltage protection circuit for operational amplifier

Abstract

The application discloses an input overvoltage protection circuit of an operational amplifier, comprising a first comparator, a noninverting input end of which is connected with a signal input end of the operational amplifier, and an inverting input end of which is connected with a power supply voltage; and a current discharge circuit, which is connected between the signal input end and the ground, wherein the first comparator is configured to control the current discharge circuit to open the current discharge circuit from the signal input end to the ground when an input voltage of the signal input end is greater than the power supply voltage and a voltage difference between the two exceeds a first preset voltage, so that input devices in the operational amplifier can be protected from being damaged by an input high-voltage signal, and the stability of the operational amplifier is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to an input overvoltage protection circuit for an operational amplifier. Background Technology

[0002] Operational amplifiers are devices that amplify the voltage or power of input signals and are widely used in communications, PCs, consumer electronics, automobiles, and industrial fields. Figure 1 and Figure 2 The circuit diagrams of existing operational amplifiers in application are shown respectively. For example... Figure 1 As shown, existing operational amplifiers often have input voltages higher than their supply voltage during application. To protect the input devices from damage caused by high-voltage signals, diodes are typically added between the positive and negative input terminals of the operational amplifier, corresponding to the power supply (Vs+) and ground (Vs-). When an input voltage higher than the power supply voltage is applied to the operational amplifier's input, the diodes conduct in the forward direction, clamping the voltage at the input terminal to a potential no higher than the power supply voltage by one diode (i.e., Vs-Vd), effectively protecting the input devices. However, if the system supplying the operational amplifier cannot draw current, or its current-drawing capability is insufficient, the power supply may be pulled by the high-voltage signal, potentially damaging the entire operational amplifier. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide an input overvoltage protection circuit for an operational amplifier, which can protect the input devices in the operational amplifier from damage by high voltage signals.

[0004] According to an embodiment of the present invention, an input overvoltage protection circuit for an operational amplifier is provided, comprising: a first comparator, the non-inverting input terminal of which is connected to the signal input terminal of the operational amplifier, and the inverting input terminal of which is connected to a power supply voltage; and a current discharge circuit connected between the signal input terminal and ground, wherein the first comparator is configured to control the current discharge circuit to open the current discharge circuit from the signal input terminal to ground when the input voltage at the signal input terminal is greater than the power supply voltage and the voltage difference between the two exceeds a first preset voltage.

[0005] Optionally, the current discharge circuit includes: a diode, with its cathode connected to the power supply voltage and its anode connected to the signal input terminal; and a first transistor, with its first current terminal connected to the anode of the diode and the signal input terminal, its second current terminal grounded, and its control terminal connected to the output terminal of the first comparator.

[0006] Optionally, the input overvoltage protection circuit further includes: an isolating switch connected between the signal input terminal and the non-inverting input terminal of the first comparator, wherein the isolating switch is configured to disconnect the signal path between the signal input terminal and the non-inverting input terminal of the first comparator when the input voltage is less than the power supply voltage and the voltage difference between the two exceeds a second preset voltage.

[0007] Optionally, the input overvoltage protection circuit further includes a pull-up bias circuit connected between the power supply voltage and the non-inverting input terminal of the first comparator, wherein the pull-up bias circuit is configured to pull up the non-inverting input terminal of the first comparator to the power supply voltage during the disconnection period of the isolating switch.

[0008] Optionally, the input overvoltage protection circuit further includes: a second comparator, with its inverting input terminal connected to the signal input terminal of the operational amplifier, its non-inverting input terminal connected to the power supply voltage, and its output terminal connected to the control terminal of the isolating switch, wherein the second comparator is configured to control the isolating switch to turn off when the input voltage is less than the power supply voltage and the voltage difference between the two exceeds a second preset voltage.

[0009] Optionally, the pull-up bias circuit includes: a first current source and a third transistor connected in sequence between the power supply voltage and the non-inverting input terminal of the first comparator, wherein the control terminal of the third transistor is connected to the input voltage of the signal input terminal.

[0010] Optionally, the first comparator and the second comparator are hysteresis comparators.

[0011] Optionally, the first comparator includes: fourth to twelfth transistors and a second current source; a seventh and eleventh transistor connected to a first branch between the power supply voltage and ground; an eighth and fourth transistor connected to a second branch between the power supply voltage and a first terminal of the second current source; a ninth, sixth, and fifth transistor connected to a third branch between the power supply voltage and the first terminal of the second current source; a tenth and twelfth transistor connected to a fourth branch between the power supply voltage and ground; and a second terminal of the second current source grounded. The seventh and eighth transistors form a first current mirror, the ninth and tenth transistors form a second current mirror, and the eleventh and twelfth transistors form a third current mirror. The control terminal of the fourth transistor serves as the inverting input of the first comparator, the control terminals of the fifth and sixth transistors serve as the non-inverting input of the first comparator, and the intermediate node between the tenth and twelfth transistors serves as the output of the first comparator.

[0012] Optionally, the first preset voltage can be set by adjusting the size ratio between the fourth transistor and the fifth and sixth transistors.

[0013] Optionally, the second comparator includes: a thirteenth to a twenty-first transistor and a third current source; a sixteenth and a twentieth transistor connected in a fifth branch between the power supply voltage and ground; a seventeenth and a thirteenth transistor connected in a sixth branch between the power supply voltage and the first terminal of the third current source; an eighteenth, a fifteenth, and a fourteenth transistor connected in a seventh branch between the power supply voltage and the first terminal of the third current source; a nineteenth and a twenty-first transistor connected in an eighth branch between the power supply voltage and ground; and the second terminal of the third current source is grounded. The sixteenth and seventeenth transistors form a fourth current mirror, the eighteenth and nineteenth transistors form a fifth current mirror, and the twentieth and twenty-first transistors form a sixth current mirror. The control terminal of the thirteenth transistor serves as the inverting input of the second comparator, the control terminals of the fourteenth and fifteenth transistors serve as the non-inverting input of the second comparator, and the intermediate node between the nineteenth and twenty-first transistors serves as the output of the second comparator.

[0014] Optionally, the second preset voltage can be set by adjusting the size ratio between the thirteenth transistor and the fourteenth and fifteenth transistors.

[0015] In summary, the input overvoltage protection circuit for an operational amplifier according to embodiments of the present invention includes a first comparator and a current discharge circuit. The first comparator is configured to control the current discharge circuit to open the current discharge path from the signal input terminal to ground when the input voltage at the signal input terminal of the operational amplifier is greater than the power supply voltage and the voltage difference between the two exceeds a first preset voltage. This protects the input devices in the operational amplifier from damage by the input high-voltage signal, improving the stability of the operational amplifier.

[0016] Furthermore, the input overvoltage protection circuit of the present invention also includes an isolating switch, a second comparator, and a pull-up bias circuit. The second comparator is configured to disconnect the isolating switch between the signal input terminal and the non-inverting input terminal of the first comparator when the input voltage at the signal input terminal is much lower than the power supply voltage, and pull up the non-inverting input terminal of the first comparator to the power supply voltage through the pull-up bias circuit. This ensures that when the input voltage is lower than the power supply voltage, a large bias voltage will not exist between the two input terminals of the first comparator for a long time, which would cause the input pair transistors of the comparator to deviate, thus improving the accuracy of the comparator. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0018] Figure 1 A circuit diagram of an existing operational amplifier in application is shown;

[0019] Figure 2 This shows another circuit diagram of an existing operational amplifier in application;

[0020] Figure 3 A schematic diagram of the input overvoltage protection circuit of an operational amplifier according to an embodiment of the present invention is shown;

[0021] Figure 4 A circuit diagram of the input overvoltage protection circuit of an operational amplifier according to an embodiment of the present invention is shown. Detailed Implementation

[0022] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0023] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0024] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0025] In this application, the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first current terminal, the second current terminal, and the control terminal of the P-type MOSFET are the source, the drain, and the gate, respectively, and the first current terminal, the second current terminal, and the control terminal of the N-type MOSFET are the drain, the source, and the gate, respectively.

[0026] Figure 3 A schematic diagram of the input overvoltage protection circuit of an operational amplifier according to an embodiment of the present invention is shown. Figure 3 As shown, the input overvoltage protection circuit 100 includes a comparator 110, a current discharge circuit 120, an isolating switch M2, a comparator 130, and a pull-up bias circuit 140.

[0027] In this circuit, the isolating switch M2 is, for example, a PMOS transistor, with its source connected to the signal input terminal of the operational amplifier, its drain connected to the non-inverting input terminal of comparator 110, and its gate connected to a switching signal SW. The inverting input terminal of comparator 110 is connected to the power supply voltage Vdd, and its output terminal is connected to the control terminal of current discharge circuit 120, which is connected between the signal input terminal and ground.

[0028] The comparator 110 is configured to convert the input voltage V at the signal input terminal into a signal input terminal. IN The current discharge circuit 120 is controlled to turn on and off based on the comparison result, compared with the power supply voltage Vdd. When the input voltage Vdd at the signal input terminal... IN When the voltage difference between the two voltages exceeds the first preset voltage Vos1, the comparator 110 controls the current discharge circuit 120 to turn on, and the current at the signal input terminal flows to ground through the current discharge circuit 120, thereby protecting the input devices in the operational amplifier from damage by the input high voltage signal.

[0029] Furthermore, the current discharge circuit 120 includes a diode D1 and an NMOS transistor M1. The cathode of diode D1 is connected to the power supply voltage Vdd, and the anode is connected to the signal input terminal. The drain of NMOS transistor M1 is connected to the anode of diode D1 and the signal input terminal, the source is connected to ground GND, and the gate is connected to the output terminal of comparator 110.

[0030] Continue to refer to Figure 3 The inverting input of comparator 130 is connected to the signal input, the non-inverting input is connected to the power supply voltage Vdd, and the output is used to output the switching signal SW. Comparator 130 is used to output the switching signal SW at the input voltage Vdd. IN When the voltage is less than the power supply voltage Vdd, and the voltage difference between the two exceeds the second preset voltage Vos2, the isolating switch M2 is turned off.

[0031] Pull-up bias circuit 140 is connected between the power supply voltage Vdd and node A of the non-inverting input terminal of comparator 110. Pull-up bias circuit 140 is used to pull up the non-inverting input terminal of comparator 110 to the power supply voltage Vdd when the isolating switch M2 is open.

[0032] Furthermore, the pull-up bias circuit 140 includes a current source I1 and a PMOS transistor M3. The first terminal of the current source I1 is connected to the power supply voltage Vdd, and the second terminal is connected to the source of the PMOS transistor M3. The gate of the PMOS transistor M3 is connected to the input voltage Vdd. IN The drain of the comparator 110 is connected to node A.

[0033] Furthermore, comparators 110 and 130 are hysteresis comparators. The principle of the input overvoltage protection circuit 100 in this embodiment is as follows: when the input voltage V of the operational amplifier... IN When much smaller than the supply voltage Vdd (i.e., Vdd-V IN >Vos2), when the switching signal SW output by comparator 130 is high, PMOS transistor M2 is turned off, and node A is pulled up to the power supply voltage Vdd by current source I1. At this time, the output point B of comparator 110 is low, NMOS transistor M1 is turned off, and the entire circuit has no effect. Among them, comparator 130, isolating switch M2, and pull-up bias circuit 140 are auxiliary circuits, mainly to ensure that the input voltage Vdd is low. IN When the voltage is less than the power supply voltage Vdd, the input terminal of comparator 110 will not have an excessively large voltage difference for a long time, thus improving the comparison accuracy of comparator 110.

[0034] When the input voltage V IN When the voltage approaches Vdd-Vos2, the switching signal SW output by comparator 130 flips to a low level, PMOS transistor M2 turns on, and node A is connected to the signal input terminal. When the input voltage V... IN After increasing the voltage to Vdd + Vos1, the output of comparator 110 flips to a high level, NMOS transistor M1 turns on, and the current at the signal input terminal flows through NMOS transistor M1 to the ground terminal GND, and then combines... Figure 2 The resistor R in the circuit can protect the input devices in the operational amplifier from damage caused by high voltage signals.

[0035] Figure 4 A circuit diagram of the input overvoltage protection circuit of an operational amplifier according to an embodiment of the present invention is shown. Figure 4 As shown, comparator 110 includes NMOS transistors M4-M6, NMOS transistors M11-M12, PMOS transistors M7-M10, and current source I2. The specific connections are as follows: PMOS transistors M7 and M11 are connected to the first branch between the power supply voltage Vdd and ground GND; PMOS transistors M8 and M4 are connected to the second branch between the power supply voltage Vdd and the first terminal of current source I2; PMOS transistor M9, along with NMOS transistors M6 and M5, are connected to the third branch between the power supply voltage Vdd and the first terminal of current source I2; and PMOS transistors M10 and M12 are connected to the fourth branch between the power supply voltage Vdd.

[0036] In this configuration, NMOS transistors M4 to M6 form a differential input pair. The gate of NMOS transistor M4 serves as the inverting input of comparator 110 and is connected to the power supply voltage Vdd. The gates of NMOS transistors M5 and M6 serve as the non-inverting inputs of comparator 110 and are connected to node A. The sources of NMOS transistors M4 and M5 are connected to the second terminal of current source I2. The drain of NMOS transistor M4 is connected to the drain of PMOS transistor M8. The drain of NMOS transistor M5 is connected to the source of NMOS transistor M6. The drain of NMOS transistor M6 is connected to the drain of NMOS transistor M9. PMOS transistors M7 and M8 form a current mirror. The gates of PMOS transistors M7 and M8 are connected to each other and to the drain of PMOS transistor M8. The sources of PMOS transistors M7 and M8 are connected to the power supply voltage Vdd. PMOS transistors M9 and M10 form another current mirror. The gates of PMOS transistors M9 and M10 are connected to each other and to the drains of PMOS transistors. The sources of PMOS transistors M9 and M10 are connected to the power supply voltage Vdd. NMOS transistors M11 and M12 form a third current mirror. The gate and drain of NMOS transistor M11 are connected to the drain of PMOS transistor M7. The source of NMOS transistor M11 is grounded to GND. The gate of NMOS transistor M12 is connected to the gate of NMOS transistor M11, and its drain is connected to the drain of PMOS transistor M10. The source of NMOS transistor M12 is grounded to GND. Node B between PMOS transistors M10 and NMOS transistor M12 serves as the output of comparator 110 and is connected to the gate of NMOS transistor M1.

[0037] Comparator 130 includes NMOS transistors M13-M15, NMOS transistors M20-M21, PMOS transistors M16-M19, and current source I3. The specific connections are as follows: PMOS transistors M16 and M20 are connected to the fifth branch between the power supply voltage Vdd and ground GND; PMOS transistors M17 and M13 are connected to the sixth branch between the power supply voltage Vdd and the first terminal of current source I3; PMOS transistor M18, along with NMOS transistors M15 and M14, are connected to the seventh branch between the power supply voltage Vdd and the first terminal of current source I3; and PMOS transistors M19 and M21 are connected to the eighth branch between the power supply voltage Vdd.

[0038] In this configuration, NMOS transistors M13 to M15 form a differential input pair. The gate of NMOS transistor M13 serves as the inverting input terminal of comparator 130 and is connected to the input voltage V. INThe gates of NMOS transistors M14 and M15 are connected to the power supply voltage Vdd, serving as the non-inverting input of comparator 130. The sources of NMOS transistors M13 and M14 are connected to the second terminal of current source I3. The drain of NMOS transistor M13 is connected to the drain of PMOS transistor M17, the drain of NMOS transistor M14 is connected to the source of NMOS transistor M15, and the drain of NMOS transistor M15 is connected to the drain of NMOS transistor M18. PMOS transistors M16 and M17 form a current mirror, with their gates connected to each other and to the drain of PMOS transistor M17. The sources of PMOS transistors M16 and M17 are connected to the power supply voltage Vdd. PMOS transistors M18 and M19 form another current mirror, with their gates connected to each other and to the drain of PMOS transistor M19. The sources of PMOS transistors M18 and M19 are connected to the power supply voltage Vdd. NMOS transistors M20 and M21 form the third current mirror. The gate and drain of NMOS transistor M20 are connected to the drain of PMOS transistor M16. The source of NMOS transistor M20 is grounded to GND. The gate of NMOS transistor M21 is connected to the gate of NMOS transistor M20, and its drain is connected to the drain of PMOS transistor M19. The source of NMOS transistor M21 is grounded to GND. The intermediate node between PMOS transistors M19 and NMOS transistor M21 serves as the output terminal of comparator 130.

[0039] Furthermore, the voltage value of the first preset voltage Vos1 can be set by adjusting the size ratio between NMOS transistor M4 and NMOS transistors M5 and M6, and the voltage value of the second preset voltage Vos2 can be set by adjusting the size ratio between NMOS transistor M13 and NMOS transistors M14 and M15.

[0040] In addition, the structure of the current discharge circuit 120, the isolating switch M2, and the pull-up bias circuit 140, as well as their connection with comparators 110 and 130, have been described above and will not be repeated here.

[0041] In summary, the input overvoltage protection circuit for an operational amplifier according to embodiments of the present invention includes a first comparator and a current discharge circuit. The first comparator is configured to control the current discharge circuit to open the current discharge path from the signal input terminal to ground when the input voltage at the signal input terminal of the operational amplifier is greater than the power supply voltage and the voltage difference between the two exceeds a first preset voltage. This protects the input devices in the operational amplifier from damage by the input high-voltage signal, improving the stability of the operational amplifier.

[0042] Furthermore, the input overvoltage protection circuit of the present invention also includes an isolating switch, a second comparator, and a pull-up bias circuit. The second comparator is configured to disconnect the isolating switch between the signal input terminal and the non-inverting input terminal of the first comparator when the input voltage at the signal input terminal is much lower than the power supply voltage, and pull up the non-inverting input terminal of the first comparator to the power supply voltage through the pull-up bias circuit. This ensures that when the input voltage is lower than the power supply voltage, the input terminal of the first comparator will not have an excessively large voltage difference for a long time, which is beneficial to improving the accuracy of the comparator.

[0043] It should be noted that although devices are described herein as N-channel or P-channel devices, or N-type or P-type doped regions, those skilled in the art will understand that complementary devices are also possible according to the present invention. Those skilled in the art will understand that conductivity type refers to the mechanism by which conductivity occurs, such as conduction through holes or electrons; therefore, conductivity type relates to doping type, such as P-type or N-type, rather than doping concentration. Those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately at the start of a startup action, but rather that there may be one or more small but reasonable delays between the startup action and the reaction action initiated by it, such as various propagation delays. The terms “approximately” or “substantially” used herein mean that an element value has a parameter expected to be close to the declared value or location. However, as is well known in the art, there are always small deviations that make it difficult for the value or location to be strictly the declared value. It has been properly determined in the art that a deviation of at least 10 percent (10%) (or at least 20 percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

[0044] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0045] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An input overvoltage protection circuit for an operational amplifier, comprising: The first comparator has its non-inverting input connected to the signal input of the operational amplifier and its inverting input connected to the power supply voltage. as well as A current discharge circuit is connected between the signal input terminal and ground. The first comparator is configured to control the current discharge circuit to activate the current discharge circuit from the signal input terminal to ground when the input voltage at the signal input terminal is greater than the power supply voltage and the voltage difference between the two exceeds a first preset voltage. The input overvoltage protection circuit further includes: An isolating switch is connected between the signal input terminal and the non-inverting input terminal of the first comparator. The isolating switch is configured to disconnect the signal path between the signal input terminal and the non-inverting input terminal of the first comparator when the input voltage is less than the power supply voltage and the voltage difference between them exceeds a second preset voltage. A pull-up bias circuit is connected between the power supply voltage and the non-inverting input of the first comparator, and the pull-up bias circuit is configured to pull the non-inverting input of the first comparator to the power supply voltage during the period when the disconnecting switch is open.

2. The input overvoltage protection circuit according to claim 1, wherein, The current discharge circuit includes: A diode, with its cathode connected to the power supply voltage and its anode connected to the signal input terminal; and The first transistor has a first current terminal connected to the anode of the diode and the signal input terminal, a second current terminal grounded, and a control terminal connected to the output terminal of the first comparator.

3. The input overvoltage protection circuit according to claim 1, wherein, Also includes: The second comparator has its inverting input connected to the signal input of the operational amplifier, its non-inverting input connected to the power supply voltage, and its output connected to the control terminal of the isolating switch. The second comparator is configured to control the isolating switch to turn off when the input voltage is less than the power supply voltage and the voltage difference between the two exceeds a second preset voltage.

4. The input overvoltage protection circuit according to claim 1, wherein, The pull-up bias circuit includes: A first current source and a third transistor are sequentially connected between the power supply voltage and the non-inverting input terminal of the first comparator, and the control terminal of the third transistor is connected to the input voltage of the signal input terminal.

5. The input overvoltage protection circuit according to claim 3, wherein, The first comparator and the second comparator are hysteresis comparators.

6. The input overvoltage protection circuit according to claim 1, wherein, The first comparator includes: fourth to twelfth transistors and a second current source. The seventh and eleventh transistors are connected in the first branch between the power supply voltage and ground; The eighth transistor and the fourth transistor are connected in the second branch between the power supply voltage and the first terminal of the second current source; The ninth transistor, the sixth transistor, and the fifth transistor are connected to the third branch between the power supply voltage and the first terminal of the second current source; The tenth and twelfth transistors are connected in the fourth branch between the power supply voltage and ground; The second terminal of the second current source is grounded; Wherein, the seventh transistor and the eighth transistor constitute a first current mirror, the ninth transistor and the tenth transistor constitute a second current mirror, and the eleventh transistor and the twelfth transistor constitute a third current mirror; The control terminal of the fourth transistor serves as the inverting input terminal of the first comparator, the control terminals of the fifth and sixth transistors serve as the non-inverting input terminals of the first comparator, and the intermediate node between the tenth and twelfth transistors serves as the output terminal of the first comparator.

7. The input overvoltage protection circuit according to claim 6, wherein, The first preset voltage is set by adjusting the size ratio between the fourth transistor and the fifth and sixth transistors.

8. The input overvoltage protection circuit according to claim 3, wherein, The second comparator includes: transistors thirteenth to twenty-first and a third current source. The sixteenth transistor and the twentieth transistor are connected in the fifth branch between the power supply voltage and ground; The seventeenth and thirteenth transistors are connected in the sixth branch between the power supply voltage and the first terminal of the third current source; The eighteenth transistor, the fifteenth transistor, and the fourteenth transistor are connected to the seventh branch between the power supply voltage and the first terminal of the third current source; The nineteenth transistor and the twenty-first transistor are connected in the eighth branch between the power supply voltage and ground; The second terminal of the third current source is grounded; Wherein, the sixteenth transistor and the seventeenth transistor constitute the fourth current mirror, the eighteenth transistor and the nineteenth transistor constitute the fifth current mirror, and the twentieth transistor and the twenty-first transistor constitute the sixth current mirror; The control terminal of the thirteenth transistor serves as the inverting input terminal of the second comparator, the control terminals of the fourteenth and fifteenth transistors serve as the non-inverting input terminals of the second comparator, and the intermediate node between the nineteenth and twenty-first transistors serves as the output terminal of the second comparator.

9. The input overvoltage protection circuit according to claim 8, wherein, The second preset voltage is set by adjusting the size ratio between the thirteenth transistor and the fourteenth and fifteenth transistors.

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