Comparator circuit

Abstract

The application discloses a comparator circuit, which comprises a folded cascode input stage circuit, a current mirror circuit, a gate bias circuit, a Class AB floating bias circuit, a push-pull cascode output stage circuit and a clamping circuit. The clamping circuit is connected with a first node of the current mirror circuit, a second node of the folded cascode input stage circuit and the push-pull cascode output stage circuit respectively, and is used for adjusting the potentials of the first node and the second node according to the output feedback of the push-pull cascode output stage circuit. The MOS devices in the folded cascode input stage circuit, the current mirror circuit and the push-pull cascode output stage circuit can always work in the saturation region, so that the overall response speed of the circuit is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a comparator circuit. Background Technology

[0002] Operational amplifiers are devices that amplify the voltage or power of input signals and are widely used in communications, PCs, consumer electronics, automobiles, and industrial fields.

[0003] Figure 1 A circuit diagram of an operational amplifier according to the prior art is shown. Operational amplifiers can be further divided into single-stage operational amplifiers, two-stage operational amplifiers, and multi-stage operational amplifiers. When Figure 1 When operational amplifier 100 is used as a comparator, the significant difference between the positive input signal Inp and the negative input signal Inn causes the voltage at node A to rise to near the positive supply voltage Vdd, or the voltage at node B to drop to near the negative supply voltage Vss. This causes PMOS transistor MP4 or NMOS transistor MN2 to enter the linear region. Simultaneously, the difference between the positive and negative input signals Inp and Inn also causes the output to oscillate between the positive and negative supply voltages, causing PMOS output transistor MP12 or NMOS output transistor MN10 to enter the linear region. Therefore, as the differential input signals Inp and Inn continuously change and reverse, the four MOS devices mentioned above will constantly switch between the saturation and linear regions, thus affecting the response speed of the entire circuit.

[0004] Therefore, existing operational amplifiers need to be improved to increase their response speed when used as comparators. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a comparator circuit that can improve the response speed of the overall circuit.

[0006] According to an embodiment of the present invention, a comparator circuit is provided, comprising: a folded common-source common-gate input stage circuit for receiving a positive input signal and a negative input signal; a current mirror circuit connected to the folded common-source common-gate input stage circuit; a gate bias circuit connected to the current mirror circuit and the folded common-source common-gate input stage circuit at a first node and a second node, respectively; a Class AB floating bias circuit connected to the gate bias circuit; a push-pull common-source output stage circuit connected to the Class AB floating bias circuit to achieve rail-to-rail output; and a clamping circuit connected to the first node, the second node, and the push-pull common-source output stage circuit for adjusting the potentials of the first node and the second node according to the output feedback of the push-pull common-source output stage circuit.

[0007] Optionally, the folded common-source common-gate input stage circuit includes: a first current source, first and second PMOS transistors, and first to fourth NMOS transistors. The first terminal of the first current source is connected to a positive power supply voltage. The first current terminals of the first and second PMOS transistors are connected to the second terminal of the first current source. The control terminal of the first PMOS transistor is connected to the positive input signal, and the control terminal of the second PMOS transistor is connected to the negative input signal. The first current terminals of the first and second NMOS transistors are respectively connected to the second current terminals of the second and first PMOS transistors. The second current terminals of the first and second NMOS transistors are connected to a negative power supply voltage. The control terminals of the first and second NMOS transistors are connected to the first current terminal of a third NMOS transistor. The second current terminal of the third NMOS transistor is connected to the first current terminal of the first NMOS transistor. The second current terminal of the fourth NMOS transistor is connected to the first current terminal of the second NMOS transistor. The control terminals of the third and fourth NMOS transistors are connected to a first bias voltage. The first current terminals of the third and fourth NMOS transistors are respectively used for folded common-source common-gate signal output.

[0008] Optionally, the current mirror circuit includes: a third to a sixth PMOS transistor; the first current terminals of the third and fourth PMOS transistors are connected to the positive power supply voltage; the control terminals of the third and fourth PMOS transistors are connected to a second bias voltage; the second current terminal of the third PMOS transistor is connected to the first current terminal of the fifth PMOS transistor; the second current terminal of the fourth PMOS transistor is connected to the first current terminal of the sixth PMOS transistor; the control terminals of the fifth and sixth PMOS transistors are connected to a third bias voltage; the second current terminal of the fifth PMOS transistor serves as the signal input of the current mirror circuit and is connected to the first current terminal of the third PMOS transistor; the second current terminal of the sixth PMOS transistor serves as the signal output of the current mirror circuit.

[0009] Optionally, the gate bias circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The first current terminal of the fifth NMOS transistor is connected to the second current terminal of the sixth PMOS transistor; the second current terminal of the fifth NMOS transistor is connected to the first current terminal of the fourth NMOS transistor; the control terminal of the fifth NMOS transistor is connected to the Class AB floating bias circuit to provide an NMOS gate bias signal to the Class AB floating bias circuit; the first current terminal of the seventh PMOS transistor is connected to the first node between the fourth and sixth PMOS transistors; the control terminal of the seventh PMOS transistor is connected to the third bias voltage; the second current terminal of the seventh PMOS transistor is connected to the first current terminal of the eighth PMOS transistor; and the control terminal of the eighth PMOS transistor is connected to the Class AB floating bias circuit to provide an NMOS gate bias signal to the Class AB floating bias circuit. The AB floating bias circuit provides the PMOS gate bias signal; the second current terminal of the eighth PMOS transistor is connected to the first current terminal of the sixth NMOS transistor; the control terminal of the sixth NMOS transistor is connected to the first bias voltage; and the second current terminal of the sixth NMOS transistor is connected to the second node between the second and fourth NMOS transistors.

[0010] Optionally, the Class AB floating bias circuit includes: a second current source, a third current source, seventh to ninth NMOS transistors, and ninth to eleventh PMOS transistors. The first terminal of the second current source is connected to the positive power supply voltage; the first current terminal and control terminal of the seventh NMOS transistor are connected to the second terminal of the second current source; the second current terminal of the seventh NMOS transistor is connected to the first current terminal and control terminal of the eighth NMOS transistor; the second current terminal of the eighth NMOS transistor is connected to the negative power supply voltage; the first current terminal of the ninth NMOS transistor and the second current terminal of the sixth PMOS transistor are connected at a third node; the second current terminal of the ninth NMOS transistor and the first current terminal of the sixth NMOS transistor are connected at a fourth node; the ninth... The control terminal of the NMOS transistor is connected to the control terminal of the fifth NMOS transistor and the second terminal of the second current source; the first current terminal of the tenth PMOS transistor is connected to the positive power supply voltage; the second current terminal and control terminal of the tenth PMOS transistor are connected to the first current terminal of the eleventh PMOS transistor; the second current terminal of the eleventh PMOS transistor is connected to the first terminal of the third current source; the second terminal of the third current source is connected to the negative power supply voltage; the first current terminal of the ninth PMOS transistor is connected to the third node; the second current terminal of the ninth PMOS transistor is connected to the fourth node; the control terminal of the ninth PMOS transistor is connected to the control terminal of the eighth PMOS transistor and the first terminal of the third current source.

[0011] Optionally, the push-pull common-source output stage circuit includes: a twelfth PMOS transistor and a tenth NMOS transistor, wherein the first current terminal of the twelfth PMOS transistor is connected to the positive power supply voltage; the second current terminal of the twelfth PMOS transistor is connected to the first current terminal of the tenth NMOS transistor; the second current terminal of the tenth NMOS transistor is connected to the negative power supply voltage; the control terminal of the twelfth PMOS transistor is connected to the third node to receive the PMOS output transistor control signal; the control terminal of the tenth NMOS transistor is connected to the fourth node to receive the NMOS output transistor control signal; and the intermediate node between the twelfth PMOS transistor and the tenth NMOS transistor serves as the output of the push-pull common-source output stage circuit.

[0012] Optionally, the clamping circuit includes an eleventh NMOS transistor and a thirteenth PMOS transistor. The first current terminal of the eleventh NMOS transistor is connected to the first node; the second current terminal of the eleventh NMOS transistor is connected to the output of the push-pull common-source output stage circuit; the control terminal of the eleventh NMOS transistor is connected to a fourth bias voltage; the first current terminal of the thirteenth PMOS transistor is connected to the output of the push-pull common-source output stage circuit; the second current terminal of the thirteenth PMOS transistor is connected to the second node; and the control terminal of the thirteenth PMOS transistor is connected to a fifth bias voltage.

[0013] In summary, the comparator circuit of this invention includes a folded cascode input stage circuit, a current mirror circuit, a gate bias circuit, a Class AB floating bias circuit, a push-pull cascode output stage circuit, and a clamping circuit. The clamping circuit is connected to the current mirror circuit, the folded cascode input stage circuit, and the push-pull cascode output stage circuit, respectively. By clamping the node potentials of the current mirror circuit and the folded cascode input stage circuit according to the output feedback of the push-pull cascode output stage circuit, the MOS devices in the folded cascode input stage circuit, the current mirror circuit, and the push-pull cascode output stage circuit can always operate in the saturation region, thereby greatly improving the overall response speed of the circuit. Furthermore, the comparator circuit of this invention overcomes the problem of slow response speed of operational amplifiers with large differential input signals without requiring significant modifications to the existing operational amplifier circuit structure, resulting in lower improvement costs. Attached Figure Description

[0014] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0015] Figure 1 A circuit diagram of an operational amplifier according to the prior art is shown;

[0016] Figure 2 A schematic diagram of a comparator circuit according to an embodiment of the present invention is shown;

[0017] Figure 3 A circuit diagram of a comparator circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0018] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0019] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0020] In this application, the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first current terminal, the second current terminal, and the control terminal of the P-type MOSFET are the source, the drain, and the gate, respectively, and the first current terminal, the second current terminal, and the control terminal of the N-type MOSFET are the drain, the source, and the gate, respectively.

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] Figure 2 A schematic diagram of an operational amplifier according to an embodiment of the present invention is shown. Figure 2 As shown, the comparator circuit 200 of this embodiment includes a folded common-source common-gate input stage circuit 210, a current mirror circuit 220, a gate bias circuit 230, a Class AB floating bias circuit 240, a push-pull common-source output stage circuit 250, and a clamping circuit 260.

[0023] The input stage circuit 210, also known as the preamplifier circuit, is generally a high-performance differential amplifier circuit with dual-ended inputs. It includes a PMOS differential pair that receives the positive input signal Inp and the negative input signal Inn. Using a PMOS differential pair allows the substrate of the differential pair to be connected to the common-source terminal, thereby eliminating the substrate bias effect and improving linearity. Furthermore, the input stage circuit 210 also employs a cascaded structure with a folded cascode common-source, which can provide higher gain, larger input and output swing, as well as fast settling time and high unity-gain bandwidth.

[0024] The current mirror circuit 220 is connected to the folded cascode input stage circuit 210, and its function is to convert the two output signals output by the folded cascode input stage circuit 210 into one output signal.

[0025] The gate bias circuit 230 is connected to the current mirror circuit 220 and the folded cascode input stage circuit at nodes A and B, respectively. Its function is to provide another output signal for the folded cascode input stage circuit 210, and to provide a gate bias signal for the Class AB floating bias circuit.

[0026] The output stage circuit 250 can adopt a push-pull common-source structure that can provide near full-swing output, and its biasing method adopts a Class AB floating bias structure. Specifically, the Class AB floating bias circuit 240 is connected to the gate bias circuit 230 and the push-pull common-source output stage circuit 250, and is used to control the quiescent operating current of the push-pull common-source output stage circuit 250 and realize the Class AB operation mode. The push-pull common-source output stage circuit 250 provides a rail-to-rail output signal OUT based on the two output signals of the folded common-source common-gate input stage circuit 210.

[0027] The implementation of Class AB operation means that it has a small static current flowing through the output stage circuit when static, and can output a large current to the load when dynamic, with high output efficiency and small crossover distortion.

[0028] Clamping circuit 260 is connected to node A, node B and the output terminal OUT of the push-pull common source output stage circuit 250, respectively. It is used to adjust the potential of node A and node B according to the output feedback of the push-pull common source output stage circuit, so that the MOS devices in the folded common source common gate input stage circuit 210 and the push-pull common source output stage circuit 250 always work in the saturation region, thereby improving the overall response speed of the circuit.

[0029] Figure 3 A circuit diagram of a comparator circuit according to an embodiment of the present invention is shown. Figure 3As shown, the input stage circuit 210 is a folded common-source common-gate input stage, including PMOS transistors MP1-MP2, NMOS transistors MN1-MN4, and a current source I1. The sources of PMOS transistors MP1 and MP2 are connected together, and their drains are connected to the drains of NMOS transistors MN1 and MN2, respectively. The gate of PMOS transistor MP1 is connected to the positive input signal Inp, and the gate of PMOS transistor MP2 is connected to the negative input signal Inn, forming a differential input pair. The first terminal of the current source I1 is connected to the positive power supply voltage Vdd, and the second terminal is connected to the sources of PMOS transistors MP1 and MP2. NMOS transistors MN1 and MN2 serve as active loads for the PMOS input pair MP1 and MP2. Their sources are connected to the negative power supply voltage VSS, and their gates are connected to the drain of NMOS transistor MN3. Their drains are connected to the sources of NMOS transistors MN3 and MN4, respectively. NMOS transistors MN3 and MN4 are used as single-transistor cascode amplifiers. Their gates are connected to the bias voltage Vb1, and their drains are respectively the output terminals of the folded cascode signal.

[0030] The current mirror circuit 220 includes PMOS transistors MP3 to MP6. PMOS transistors MP3 and MP5 are self-biased cascode current mirrors, as are PMOS transistors MP4 and MP6. Specifically, the sources of PMOS transistors MP3 and MP4 are connected to the positive power supply voltage Vdd, their gates are connected to the bias voltage Vb2, their drains are connected to the sources of PMOS transistors MP5 and MP6 respectively, their gates are connected to the bias voltage Vb3, the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN3, and the drain of PMOS transistor MP6 serves as the signal output terminal of the current mirror, used to output a differential amplified signal.

[0031] The gate bias circuit 230 includes NMOS transistors MN5-MN6 and PMOS transistors MP7-MP8. The drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP6, and the node C between them provides one differential amplified signal for the common-source common-gate amplifier circuit. The source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN4, and the gate of NMOS transistor MN5 is connected to the gate of NMOS transistor MN9 in the Class AB floating bias circuit 240. The source of PMOS transistor MP7 is connected to node A between PMOS transistors MP4 and MP6. The gate of PMOS transistor MP7 is connected to the bias voltage Vb3. The drain of PMOS transistor MP7 is connected to the source of PMOS transistor MP8. The gate of PMOS transistor MP8 is connected to the gate of PMOS transistor MP9 in Class AB floating bias circuit 240. The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN6. The node D between them is used to provide another differential amplified signal for the cascode amplifier circuit. The gate of NMOS transistor MN6 is connected to the bias voltage Vb1. The source of NMOS transistor MN6 is connected to node B between NMOS transistors MN2 and MN4.

[0032] The Class AB floating bias circuit 240 includes current sources I2 and I3, NMOS transistors MN7-MN9, and PMOS transistors MP9-MP11. NMOS transistors MN9 and MP9 are connected in parallel to form the floating bias circuit. Current source I2, along with NMOS transistors MN7 and MN8, forms the bias circuit for NMOS transistor MN9. Current source I3, along with PMOS transistors MP10 and MP11, forms the bias circuit for PMOS transistor MP9. Specifically, the first terminal of current source I2 is connected to the positive power supply voltage Vdd, and the second terminal is connected to the drain and gate of NMOS transistor MN7. The source of NMOS transistor MN7 is connected to the drain and gate of NMOS transistor MN8. The source of NMOS transistor MN8 is connected to the negative power supply voltage Vss. The drain of NMOS transistor MN9 is connected to node C, the source of NMOS transistor MN9 is connected to node D, and the gate of NMOS transistor MN9 is connected to the second terminal of current source I2. The source of PMOS transistor MP10 is connected to the positive power supply voltage Vdd, and its drain and gate are connected to the source of PMOS transistor MP11. The drain and gate of PMOS transistor MP11 are connected to the first terminal of current source I3, and the second terminal of current source I3 is connected to the negative power supply voltage Vss. The source of PMOS transistor MP9 is connected to node C, the drain of PMOS transistor MP9 is connected to node D, and the gate of PMOS transistor MP9 is connected to the first terminal of current source I3.

[0033] The push-pull common-source output stage circuit 250 includes a PMOS transistor MP12 and an NMOS transistor MN10. The drains of the PMOS transistor MP12 and the NMOS transistor MN10 are the push-pull output terminals OUT. The source of the PMOS transistor MP12 is connected to the positive power supply voltage Vdd, and its gate is connected to the Class AB floating bias control signal terminal of the PMOS output transistor. The source of the NMOS transistor MN10 is connected to the negative power supply voltage Vss, and its gate is connected to the Class AB floating bias control signal terminal of the NMOS output transistor.

[0034] The clamping circuit 260 includes an NMOS transistor MN11 and a PMOS transistor MP13. The drain of NMOS transistor MN11 is connected to node A, its gate is connected to the bias voltage Vb4, and its source is connected to the push-pull output terminal OUT. The drain of PMOS transistor MP13 is connected to node B, its gate is connected to the bias voltage Vb5, and its source is connected to the push-pull output terminal OUT. By adjusting the potentials of the bias voltages Vb4 and Vb5, and simultaneously adjusting the dimensions of NMOS transistors MN11 and MP13, the potentials at nodes A and B, as well as the output terminal, are made equal. This prevents NMOS transistors MN2 and MP4, as well as output transistors MP12 and MN10, from entering the linear region when the differential input signals Inp and Inn differ significantly, thereby greatly improving the overall circuit response speed.

[0035] In summary, the comparator circuit of this invention includes a folded cascode input stage circuit, a current mirror circuit, a gate bias circuit, a Class AB floating bias circuit, a push-pull cascode output stage circuit, and a clamping circuit. The clamping circuit is connected to the current mirror circuit, the folded cascode input stage circuit, and the push-pull cascode output stage circuit, respectively. By clamping the node potentials of the current mirror circuit and the folded cascode input stage circuit according to the output feedback of the push-pull cascode output stage circuit, the MOS devices in the folded cascode input stage circuit, the current mirror circuit, and the push-pull cascode output stage circuit can always operate in the saturation region, thereby greatly improving the overall response speed of the circuit. Furthermore, the comparator circuit of this invention overcomes the problem of slow response speed of operational amplifiers with large differential input signals without requiring significant modifications to the existing operational amplifier circuit structure, resulting in lower improvement costs.

[0036] It should be noted that although devices are described herein as N-channel or P-channel devices, or N-type or P-type doped regions, those skilled in the art will understand that complementary devices are also possible according to the present invention. Those skilled in the art will understand that conductivity type refers to the mechanism by which conductivity occurs, such as conduction through holes or electrons; therefore, conductivity type relates to doping type, such as P-type or N-type, rather than doping concentration. Those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately at the start of a startup action, but rather that there may be one or more small but reasonable delays between the startup action and the reaction action initiated by it, such as various propagation delays. The terms “approximately” or “substantially” used herein mean that an element value has a parameter expected to be close to the declared value or location. However, as is well known in the art, there are always small deviations that make it difficult for the value or location to be strictly the declared value. It has been properly determined in the art that a deviation of at least 10 percent (10%) (or at least 20 percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

[0037] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0038] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A comparator circuit, comprising: The folded common-source common-gate input stage circuit receives both the positive and negative input signals. The current mirror circuit is connected to the folded cascode input stage circuit. The gate bias circuit is connected to the current mirror circuit and the folded cascode input stage circuit at the first node and the second node, respectively. A Class AB floating bias circuit is connected to the gate bias circuit. as well as The push-pull common-source output stage circuit is connected to the Class AB floating bias circuit to achieve rail-to-rail output; as well as A clamping circuit, connected to the first node, the second node, and the push-pull common-source output stage circuit, is used to adjust the potentials of the first node and the second node according to the output feedback of the push-pull common-source output stage circuit.

2. The comparator circuit according to claim 1, wherein, The folded common-source common-gate input stage circuit includes: a first current source, first and second PMOS transistors, and first to fourth NMOS transistors. The first terminal of the first current source is connected to the positive power supply voltage; The first current terminals of the first PMOS transistor and the second PMOS transistor are connected to the second terminal of the first current source. The control terminal of the first PMOS transistor is connected to the positive input signal, and the control terminal of the second PMOS transistor is connected to the negative input signal. The first current terminal of the first NMOS transistor and the second NMOS transistor are respectively connected to the second current terminal of the second PMOS transistor and the second current terminal of the first PMOS transistor. The second current terminals of the first NMOS transistor and the second NMOS transistor are connected to the negative power supply voltage. The control terminals of the first NMOS transistor and the second NMOS transistor are connected to the first current terminal of the third NMOS transistor; The second current terminal of the third NMOS transistor is connected to the first current terminal of the first NMOS transistor. The second current terminal of the fourth NMOS transistor is connected to the first current terminal of the second NMOS transistor; The control terminals of the third NMOS transistor and the fourth NMOS transistor are connected to the first bias voltage; The first current terminals of the third NMOS transistor and the fourth NMOS transistor are respectively used for folding the common source and common gate signal output.

3. The comparator circuit according to claim 2, wherein, The current mirror circuit includes: the third to the sixth PMOS transistors. The first current terminals of the third and fourth PMOS transistors are connected to the positive power supply voltage. The control terminals of the third PMOS transistor and the fourth PMOS transistor are connected to the second bias voltage. The second current terminal of the third PMOS transistor is connected to the first current terminal of the fifth PMOS transistor. The second current terminal of the fourth PMOS transistor is connected to the first current terminal of the sixth PMOS transistor. The control terminals of the fifth PMOS transistor and the sixth PMOS transistor are connected to the third bias voltage; The second current terminal of the fifth PMOS transistor is connected to the first current terminal of the third NMOS transistor as the signal input of the current mirror circuit. The second current terminal of the sixth PMOS transistor serves as the signal output of the current mirror circuit.

4. The comparator circuit according to claim 3, wherein, The gate bias circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The first current terminal of the fifth NMOS transistor is connected to the second current terminal of the sixth PMOS transistor; The second current terminal of the fifth NMOS transistor is connected to the first current terminal of the fourth NMOS transistor; The control terminal of the fifth NMOS transistor is connected to the Class AB floating bias circuit to provide an NMOS gate bias signal to the Class AB floating bias circuit; The first current terminal of the seventh PMOS transistor is connected to the first node between the fourth and sixth PMOS transistors. The control terminal of the seventh PMOS transistor is connected to the third bias voltage. The second current terminal of the seventh PMOS transistor is connected to the first current terminal of the eighth PMOS transistor. The control terminal of the eighth PMOS transistor is connected to the Class AB floating bias circuit to provide a PMOS gate bias signal to the Class AB floating bias circuit. The second current terminal of the eighth PMOS transistor is connected to the first current terminal of the sixth NMOS transistor. The control terminal of the sixth NMOS transistor is connected to the first bias voltage; The second current terminal of the sixth NMOS transistor is connected to the second node between the second and fourth NMOS transistors.

5. The comparator circuit according to claim 4, wherein, The Class AB floating bias circuit includes: a second current source, a third current source, seventh to ninth NMOS transistors, and ninth to eleventh PMOS transistors. The first terminal of the second current source is connected to the positive power supply voltage; The first current terminal and the control terminal of the seventh NMOS transistor are connected to the second terminal of the second current source; The second current terminal of the seventh NMOS transistor is connected to the first current terminal and the control terminal of the eighth NMOS transistor. The second current terminal of the eighth NMOS transistor is connected to the negative power supply voltage. The first current terminal of the ninth NMOS transistor and the second current terminal of the sixth PMOS transistor are connected to the third node. The second current terminal of the ninth NMOS transistor is connected to the first current terminal of the sixth NMOS transistor at the fourth node; The control terminal of the ninth NMOS transistor is connected to the control terminal of the fifth NMOS transistor and the second terminal of the second current source; The first current terminal of the tenth PMOS transistor is connected to the positive power supply voltage. The second current terminal and control terminal of the tenth PMOS transistor are connected to the first current terminal of the eleventh PMOS transistor. The second current terminal of the eleventh PMOS transistor is connected to the first terminal of the third current source. The second terminal of the third current source is connected to the negative power supply voltage; The first current terminal of the ninth PMOS transistor is connected to the third node; The second current terminal of the ninth PMOS transistor is connected to the fourth node; The control terminal of the ninth PMOS transistor is connected to the control terminal of the eighth PMOS transistor and the first terminal of the third current source.

6. The comparator circuit according to claim 5, wherein, The push-pull common-source output stage circuit includes: a twelfth PMOS transistor and a tenth NMOS transistor. The first current terminal of the twelfth PMOS transistor is connected to the positive power supply voltage. The second current terminal of the twelfth PMOS transistor is connected to the first current terminal of the tenth NMOS transistor. The second current terminal of the tenth NMOS transistor is connected to the negative power supply voltage; The control terminal of the twelfth PMOS transistor is connected to the third node to receive the control signal of the PMOS output transistor; The control terminal of the tenth NMOS transistor is connected to the fourth node to receive the NMOS output transistor control signal; The intermediate node between the twelfth PMOS transistor and the tenth NMOS transistor serves as the output of the push-pull common-source output stage circuit.

7. The comparator circuit according to claim 6, wherein, The clamping circuit includes an eleventh NMOS transistor and a thirteenth PMOS transistor. The first current terminal of the eleventh NMOS transistor is connected to the first node; The second current terminal of the eleventh NMOS transistor is connected to the output of the push-pull common-source output stage circuit. The control terminal of the eleventh NMOS transistor is connected to the fourth bias voltage. The first current terminal of the thirteenth PMOS transistor is connected to the output of the push-pull common-source output stage circuit. The second current terminal of the thirteenth PMOS transistor is connected to the second node; The control terminal of the thirteenth PMOS transistor is connected to the fifth bias voltage.

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