An adaptive soft-switching high voltage bleeder switch circuit

Abstract

This invention discloses an adaptive soft-switching high-voltage discharge switch circuit, relating to the field of electronic circuit technology. It includes: a first transistor, with its source connected to the voltage input terminal VPP, its drain connected to the voltage output terminal VOUT, and its gate used to receive a first control signal; a second transistor, with its source connected to VOUT and its drain connected to the voltage input terminal VDD; a third transistor, with its source connected to VOUT and its gate used to receive a reference voltage VREF; a first resistor, disposed between the source and VOUT of the third transistor; a fourth transistor, with its drain connected to VOUT and its gate used to receive a second control signal; a parasitic capacitor, with one end connected to VOUT and the other end grounded; a current mirror circuit connected to the drain of the third transistor and the source of the fourth transistor; an amplifier connected to the current mirror circuit; and a level conversion circuit connected to the amplifier, the gate of the second transistor, and VOUT. This invention can automatically switch the high-voltage output to a low-voltage output based on the degree of charge discharge.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to an adaptive soft-switching high-voltage discharge switch circuit. Background Technology

[0002] Existing charge discharge circuits generally use high-voltage gate (>10V) MOS transistors. These devices are typically found in EEPROM (Electrically Erasable Programmable Read Only Memory) and Flash technologies, which limits the selection of devices when designing high-voltage switches and charge discharge circuits. Summary of the Invention

[0003] The purpose of this invention is to provide an adaptive soft-switching high-voltage discharge switch circuit that can use a low-voltage gate single-sided asymmetric high-voltage (>9V) transistor to automatically switch the high-voltage output to the low-voltage output according to the degree of charge discharge.

[0004] To achieve the above objectives, the present invention provides the following solution:

[0005] An adaptive soft-switching high-voltage discharge switch circuit, the high-voltage discharge switch circuit comprising:

[0006] The first transistor has its source connected to the voltage input terminal VPP, its drain connected to the voltage output terminal VOUT, and its gate used to receive the first control signal.

[0007] The second transistor has its source connected to VOUT and its drain connected to the voltage input terminal VDD.

[0008] The third transistor has its source connected to VOUT and its gate used to receive the reference voltage VREF.

[0009] The first resistor is positioned between the source of the third transistor and VOUT.

[0010] The fourth transistor has its drain connected to VOUT and its gate used to receive the second control signal.

[0011] The parasitic capacitance is connected at one end to VOUT and at the other end to ground.

[0012] The current mirror circuit is connected to the drain of the third transistor and the source of the fourth transistor.

[0013] An amplifier is connected to the current mirror circuit;

[0014] A level conversion circuit is connected to the amplifier, the gate of the second transistor, and VOUT;

[0015] When the first control signal and the second control signal switch from low level to high level, the third transistor identifies the voltage at the VOUT terminal and converts it into a detection current. The current mirror circuit generates a discharge current based on the detection current. The discharge current is transmitted to the amplifier, causing the amplifier output to decrease and the level conversion circuit output to increase. The first transistor and the second transistor are turned off.

[0016] When the charge stored in the parasitic capacitor is discharged, making the voltage difference between VOUT and VREF equal to the voltage difference between the gate and source of the third transistor, the discharge current decreases. When the discharge current decreases to below the threshold point of the amplifier, the amplifier output jumps high, the level conversion circuit output jumps low, and the driving voltage of the second transistor changes from 0 to greater than VDD.

[0017] Optionally, the current mirror circuit includes:

[0018] The fifth transistor has its drain connected to the drain of the third transistor and the amplifier, its gate connected to the drain of the fifth transistor and the amplifier, and its source grounded.

[0019] The sixth transistor has its drain connected to the source of the fourth transistor, its gate connected to the amplifier, the gate of the fifth transistor, and the drain of the fifth transistor, and its source grounded.

[0020] Optionally, the amplifier includes:

[0021] The second resistor has one end connected to VDD and the other end connected to the level conversion circuit;

[0022] The seventh transistor has its drain connected to the other end of the second resistor and the level conversion circuit, its gate connected to the current mirror circuit, and its source grounded.

[0023] Optionally, the level conversion circuit includes:

[0024] The third resistor has one end connected to VOUT and the other end connected to the gate of the second transistor.

[0025] The eighth transistor has its drain connected to the other end of the third resistor and the gate of the second transistor, respectively. The gate is connected to the amplifier, and the source is grounded.

[0026] Optionally, the first transistor and the second transistor are both single-sided high-voltage PMOS transistors, the third transistor is a low-voltage PMOS transistor, and the fourth transistor is a single-sided high-voltage NMOS transistor.

[0027] Optionally, the fifth transistor is a low-voltage NMOS transistor, and the sixth transistor is an NMOS transistor.

[0028] Optionally, the seventh transistor is an NMOS transistor.

[0029] Optionally, the eighth transistor is a single-sided high-voltage NMOS transistor.

[0030] Optionally, when VDD = 5V, VPP < VDD + 5.5V.

[0031] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0032] The adaptive soft-switching high-voltage discharge switch circuit of this invention includes: a first transistor, with its source connected to the voltage input terminal VPP, its drain connected to the voltage output terminal VOUT, and its gate used to receive a first control signal; a second transistor, with its source connected to VOUT and its drain connected to the voltage input terminal VDD; a third transistor, with its source connected to VOUT and its gate used to receive a reference voltage VREF; a first resistor, disposed between the source and VOUT of the third transistor; a fourth transistor, with its drain connected to VOUT and its gate used to receive a second control signal; a parasitic capacitor, with one end connected to VOUT and the other end grounded; a current mirror circuit, connected to the drain of the third transistor and the source of the fourth transistor; an amplifier, connected to the current mirror circuit; and a level conversion circuit, connected to the amplifier, the gate of the second transistor, and VOUT. This invention can use a low-voltage gate single-sided asymmetric high-voltage transistor to automatically switch the high-voltage output to a low-voltage output through a switch according to the degree of charge discharge. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the adaptive soft-switching high-voltage discharge switch circuit of the present invention;

[0035] Figure 2 This is a schematic diagram illustrating the effect of adaptive soft handover in one embodiment of the present invention.

[0036] Symbol explanation:

[0037] First transistor 101, second transistor 102, third transistor 103, fourth transistor 104, first resistor 105, parasitic capacitance 106, current mirror circuit 110, fifth transistor 111, sixth transistor 112, amplifier 120, second resistor 121, seventh transistor 122, level conversion circuit 130, third resistor 131, eighth transistor 132. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] The purpose of this invention is to provide an adaptive soft-switching high-voltage discharge switch circuit, which can use a low-voltage gate single-sided asymmetric high-voltage transistor to automatically switch the high-voltage output to the low-voltage output according to the degree of charge discharge.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Specifically, such as Figure 1 As shown, the adaptive soft-switching high-voltage discharge switch circuit of the present invention includes: a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a first resistor 105, a parasitic capacitance 106, a current mirror circuit 110, an amplifier 120, and a level conversion circuit 130.

[0042] The source of the first transistor 101 is connected to the voltage input terminal VPP, the drain is connected to the voltage output terminal VOUT, and the gate is used to receive the first control signal.

[0043] The source of the second transistor 102 is connected to VOUT, and the drain is connected to the voltage input terminal VDD.

[0044] The source of the third transistor 103 is connected to VOUT, and its gate is used to receive the reference voltage VREF.

[0045] The first resistor 105 is disposed between the source of the third transistor 103 and VOUT.

[0046] The drain of the fourth transistor 104 is connected to VOUT, and the gate is used to receive the second control signal.

[0047] One end of the parasitic capacitor 106 is connected to VOUT, and the other end is grounded.

[0048] The current mirror circuit 110 is connected to the drain of the third transistor 103 and the source of the fourth transistor 104.

[0049] The amplifier 120 is connected to the current mirror circuit 110.

[0050] The level conversion circuit 130 is connected to the amplifier 120, the gate of the second transistor 102, and VOUT.

[0051] When the first control signal and the second control signal switch from low level to high level, the third transistor identifies the voltage at the VOUT terminal and converts it into a detection current. The current mirror circuit generates a discharge current based on the detection current. The discharge current is transmitted to the amplifier, causing the amplifier output to decrease and the level conversion circuit output to increase. The first transistor and the second transistor are turned off.

[0052] When the charge stored in the parasitic capacitor is discharged, making the voltage difference between VOUT and VREF equal to the voltage difference between the gate and source of the third transistor, the discharge current decreases. When the discharge current decreases to below the threshold point of the amplifier, the amplifier output jumps high, the level conversion circuit output jumps low, and the driving voltage of the second transistor changes from 0 to greater than VDD.

[0053] In addition, the first transistor 101 and the second transistor 102 serve as two main switches for transmitting high voltage VPP and low voltage VDD to VOUT. The first transistor 101 realizes the transmission of high voltage VPP to VOUT, and the second transistor 102 realizes the transmission of low voltage VDD to VOUT.

[0054] The third transistor 103 serves as a voltage detection transistor and is interconnected with the current mirror circuit 110, amplifier 120, and level conversion circuit 130 to achieve charge discharge and soft switching. Therefore, the high-voltage discharge switch circuit of the present invention with adaptive soft switching can automatically switch the high-voltage output to the low-voltage output according to the degree of charge discharge.

[0055] Furthermore, such as Figure 1 As shown, the current mirror circuit 110 includes a fifth transistor 111 and a sixth transistor 112; the amplifier 120 includes a second resistor 121 and a seventh transistor 122; and the level conversion circuit 130 includes a third resistor 131 and an eighth transistor 132.

[0056] The drain of the fifth transistor 111 is connected to the drain of the third transistor 103 and the amplifier 120. The gate of the fifth transistor 111 is connected to the drain of the fifth transistor 111 and the amplifier 120. The source of the fifth transistor 111 is grounded.

[0057] The drain of the sixth transistor 112 is connected to the source of the fourth transistor 104. The gate of the sixth transistor 112 is connected to the amplifier 120, the gate of the fifth transistor 111, and the drain of the fifth transistor 111. The source of the sixth transistor 112 is grounded.

[0058] One end of the second resistor 121 is connected to VDD. The other end of the second resistor 121 is connected to the gate of the eighth transistor.

[0059] The drain of the seventh transistor 122 is connected to the other end of the second resistor 121 and the level conversion circuit 130. The gate of the seventh transistor 122 is connected to the current mirror circuit 110. The source of the seventh transistor 122 is grounded.

[0060] Specifically, the drain of the fifth transistor 111 is connected to the gate of the seventh transistor 122; the gate of the fifth transistor 111 is connected to the gate of the seventh transistor 122; and the gate of the sixth transistor 112 is connected to the gate of the seventh transistor 122.

[0061] One end of the third resistor 131 is connected to VOUT. The other end of the third resistor 131 is connected to the gate of the second transistor 102.

[0062] The drain of the eighth transistor 132 is connected to the other end of the third resistor 131 and the gate of the second transistor 102. The gate of the eighth transistor 132 is connected to the amplifier 120. The source of the eighth transistor 132 is grounded.

[0063] Specifically, the drain of the seventh transistor 122 is connected to the gate of the eighth transistor 132.

[0064] Furthermore, the output voltage potential is detected through the first resistor, the third transistor, and the fifth transistor. VREF serves as a reference voltage for detecting the VOUT voltage; preferably, VREF = VDD - VGSP; where the reference voltage VGSP is the voltage difference between the gate and source of the third transistor.

[0065] Furthermore, when the first control signal vpp_en_n and the second control signal vpp_en_n_lv switch from low to high, the circuit enters the discharge and soft switching stage: firstly, the high potential voltage at the VOUT terminal is recognized by the third transistor VGS (driving voltage) and converted into current, which is then mirrored by the fifth transistor 111 to the sixth transistor 112 to generate a discharge current.

[0066] The ratio of the fifth transistor 111 to the sixth transistor 112 can be set according to the discharge rate; at the same time, the current of the fifth transistor 111 is also mirrored to the sixth transistor 112, which will make the output of the amplifier 120 lower, thereby keeping the output line of the level shift circuit 130 high, and turning off the first transistor 101 and the second transistor 102.

[0067] When the charge stored by the parasitic capacitor 106 is discharged through the path of the fourth transistor 104 and the sixth transistor 112 to such that the voltage difference between VOUT and VREF is equal to the voltage difference between the gate and source of the third transistor, the detection current generated by detecting the voltage potential at the VOUT terminal through the first resistor 105, the second transistor 102, and the fifth transistor 111 decreases. When the detection current is lower than the threshold point of the amplifier 120, the output of the amplifier 120 jumps high, and then the output of the level conversion circuit 130 jumps low, realizing soft switching. The driving voltage of the second transistor 102 changes from 0 to slightly greater than VDD, thereby ensuring that the gate-source voltage of the second transistor 102 is within a safe range (e.g., <5.5V).

[0068] Furthermore, the threshold point of the amplifier 120 can be set by changing the channel width ratio of the fifth transistor 111 and the seventh transistor 122, as well as the resistance value of the second resistor 121, thereby adjusting the difference in voltage between VOUT and VDD (e.g., <200mV). Specifically, the channel width of the seventh transistor 122 is 10 to 100 times the channel width of the fifth transistor 111; preferably, the channel width of the seventh transistor 122 is 60 times the channel width of the fifth transistor 111.

[0069] Furthermore, the first and second transistors are both single-sided high-voltage PMOS transistors, the third transistor is a low-voltage PMOS transistor, and the fourth transistor is a single-sided high-voltage NMOS transistor. The fifth transistor is a low-voltage NMOS transistor, the sixth transistor is an NMOS transistor, the seventh transistor is an NMOS transistor, and the eighth transistor is a single-sided high-voltage NMOS transistor.

[0070] Preferably, the first, second, fourth, and eighth transistors are all low-voltage gate single-sided high-voltage transistors. The third, fifth, sixth, and seventh transistors are all low-voltage 5V transistors; furthermore, when VDD = 5V, VPP < VDD + 5.5V.

[0071] The circuit structure involved in this invention can be implemented using a low-voltage gate (5V) single-sided asymmetric high-voltage transistor, and is suitable for various processes, such as high-voltage BCD (Bipolar CMOS DMOS) process, and can achieve automatic soft switching after the output voltage is discharged to near the target value. Furthermore, as... Figure 2 As shown, by observing the waveforms at each node, it can be seen that the voltage of line 100 automatically changes when VOUT is approximately equal to VDD.

[0072] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0073] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A high-voltage discharge switch circuit with adaptive soft switching, characterized in that, The high-voltage discharge switch circuit includes: The first transistor has its source connected to the voltage input terminal VPP, its drain connected to the voltage output terminal VOUT, and its gate used to receive the first control signal. The second transistor has its source connected to VOUT and its drain connected to the voltage input terminal VDD. The third transistor has its source connected to VOUT and its gate used to receive the reference voltage VREF. The first resistor is positioned between the source of the third transistor and VOUT. The fourth transistor has its drain connected to VOUT and its gate used to receive the second control signal. The parasitic capacitance is connected at one end to VOUT and at the other end to ground. The current mirror circuit is connected to the drain of the third transistor and the source of the fourth transistor. An amplifier is connected to the current mirror circuit; A level conversion circuit is connected to the amplifier, the gate of the second transistor, and VOUT; When the first control signal and the second control signal switch from low level to high level, the third transistor identifies the voltage at the VOUT terminal and converts it into a detection current. The current mirror circuit generates a discharge current based on the detection current. The discharge current is transmitted to the amplifier, causing the amplifier output to decrease and the level conversion circuit output to increase. The first transistor and the second transistor are turned off. When the charge stored in the parasitic capacitor is discharged, making the voltage difference between VOUT and VREF equal to the voltage difference between the gate and source of the third transistor, the discharge current decreases. When the discharge current decreases to below the threshold point of the amplifier, the amplifier output jumps high, the level conversion circuit output jumps low, and the driving voltage of the second transistor changes from 0 to greater than VDD.

2. The adaptive soft-switching high-voltage discharge switch circuit according to claim 1, characterized in that, The current mirror circuit includes: The fifth transistor has its drain connected to the drain of the third transistor and the amplifier, its gate connected to the drain of the fifth transistor and the amplifier, and its source grounded. The sixth transistor has its drain connected to the source of the fourth transistor, its gate connected to the amplifier, the gate of the fifth transistor, and the drain of the fifth transistor, and its source grounded.

3. The adaptive soft-switching high-voltage discharge switch circuit according to claim 1, characterized in that, The amplifier includes: The second resistor has one end connected to VDD and the other end connected to the level conversion circuit; The seventh transistor has its drain connected to the other end of the second resistor and the level conversion circuit, its gate connected to the current mirror circuit, and its source grounded.

4. The adaptive soft-switching high-voltage discharge switch circuit according to claim 1, characterized in that, The level conversion circuit includes: The third resistor has one end connected to VOUT and the other end connected to the gate of the second transistor. The eighth transistor has its drain connected to the other end of the third resistor and the gate of the second transistor, respectively. The gate is connected to the amplifier, and the source is grounded.

5. The adaptive soft-switching high-voltage discharge switch circuit according to claim 1, characterized in that, The first and second transistors are both single-sided high-voltage PMOS transistors, the third transistor is a low-voltage PMOS transistor, and the fourth transistor is a single-sided high-voltage NMOS transistor.

6. The adaptive soft-switching high-voltage discharge switch circuit according to claim 2, characterized in that, The fifth transistor is a low-voltage NMOS transistor, and the sixth transistor is an NMOS transistor.

7. The adaptive soft-switching high-voltage discharge switch circuit according to claim 3, characterized in that, The seventh transistor is an NMOS transistor.

8. The adaptive soft-switching high-voltage discharge switch circuit according to claim 4, characterized in that, The eighth transistor is a single-sided high-voltage NMOS transistor.

9. The adaptive soft-switching high-voltage discharge switch circuit according to claim 1, characterized in that, When VDD = 5V, VPP < VDD + 5.5V.

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