Latching circuit, array substrate and electrophoretic display device

Abstract

The application relates to a latch circuit, an array substrate and an electrophoretic display device. In the latch circuit, the output end of a first inverter is connected with the input end of a second inverter, the output end of the second inverter is electrically connected with the input end of the first inverter, the first power supply end of the first inverter and the first power supply end of the second inverter are connected with a first potential signal, the second power supply end of the first inverter is connected with a reference potential signal, and the second power supply end of the second inverter is electrically connected with the reference potential signal; the output end of a third inverter is connected with the input end of a fourth inverter, the output end of the fourth inverter is electrically connected with the input end of the third inverter, the first power supply end of the third inverter and the first power supply end of the fourth inverter are connected with a second potential signal, the second power supply end of the third inverter is connected with the reference potential signal, and the second power supply end of the fourth inverter is electrically connected with the reference potential signal. The application can realize fast writing of an input signal and long-term latching.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a latching circuit, an array substrate, and an electrophoretic display device. Background Technology

[0002] In display technology, latch circuits, as key driving components, can latch input signals (such as image signals) to maintain stable pixel voltage over a long period. Latch circuits that enable fast writing and long-term latching of input signals have always been a focus of research for developers. Summary of the Invention

[0003] This invention provides a latching circuit, an array substrate, and an electrophoretic display device to achieve fast writing and long-term latching of input signals.

[0004] In a first aspect, embodiments of the present invention provide a latching circuit, comprising: a first inverter, a second inverter, a third inverter, and a fourth inverter;

[0005] The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter. The first power supply terminal of the first inverter and the first power supply terminal of the second inverter are both connected to a first potential signal. The second power supply terminal of the first inverter is connected to a reference potential signal, and the second power supply terminal of the second inverter is electrically connected to the reference potential signal.

[0006] The output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is electrically connected to the input terminal of the third inverter. The first power supply terminals of the third inverter and the fourth inverter are both connected to the second potential signal. The second power supply terminal of the third inverter is connected to the reference potential signal, and the second power supply terminal of the fourth inverter is electrically connected to the reference potential signal. Relative to the reference potential signal, the first potential signal and the second potential signal have opposite signs.

[0007] The second inverter is used to output the first potential signal or the reference potential signal, and the output potential signal is the same type of potential signal as the potential signal input to the first inverter; the fourth inverter is used to output the second potential signal or the reference potential signal, and the output potential signal is the same type of potential signal as the potential signal input to the third inverter.

[0008] Secondly, embodiments of the present invention also provide a latching circuit, including: a first inverter, a second inverter, a third inverter, and a fourth inverter;

[0009] The output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is electrically connected to the input terminal of the first inverter, the input terminal of the first inverter is connected to the input terminal of the third inverter, and the first power supply terminal of the first inverter and the first power supply terminal of the second inverter are both connected to the first potential signal.

[0010] The output terminal of the third inverter is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the second power supply terminal of the first inverter and the second power supply terminal of the second inverter, respectively. The first power supply terminals of the third inverter and the fourth inverter are both connected to a second potential signal. The second power supply terminals of the third inverter and the fourth inverter are both connected to a reference potential signal. The first potential signal and the second potential signal are opposite in sign to the reference potential signal.

[0011] Thirdly, embodiments of the present invention also provide an array substrate, including a substrate and a plurality of pixel units located on one side of the substrate. The pixel unit includes a latching circuit as described in the first or second aspect and a pixel electrode located on the side of the latching circuit away from the substrate. The output terminal of the latching circuit is electrically connected to the pixel electrode.

[0012] Fourthly, embodiments of the present invention also provide an electrophoretic display device, including the array substrate, the common electrode layer, and the electrophoretic membrane located between the array substrate and the common electrode layer as described in the third aspect.

[0013] The technical solution provided by the embodiments of the present invention has the following advantages compared with the prior art:

[0014] The latch circuit provided in this embodiment of the invention employs four inverters. When a potential signal (such as an image signal) is input to the latch circuit, the four inverters work together to ensure that the latch circuit outputs a first potential signal, a reference potential signal, or a second potential signal of the same type as the input potential signal, thereby achieving fast writing of the input signal. Furthermore, when the input signal disappears, the latch circuit operates in a latching state, that is, the latch circuit feeds back the output potential signal to its input terminal. Since the potential signal output by the latch circuit is of the same type as the previously input potential signal, the latch circuit maintains the output of the input signal, i.e., latches the input signal, until a different type of potential signal is input, at which point the output of the latch circuit will change accordingly. Therefore, the technical solution of this invention can achieve long-term latching of the input signal. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A structural block diagram of a latch circuit provided in an embodiment of the present invention;

[0018] Figure 2 A circuit diagram of a latch circuit provided in an embodiment of the present invention;

[0019] Figure 3 A circuit diagram of another latching circuit provided in an embodiment of the present invention;

[0020] Figure 4 A circuit diagram of another latching circuit provided in an embodiment of the present invention;

[0021] Figure 5 A circuit diagram of another latching circuit provided in an embodiment of the present invention;

[0022] Figure 6 for Figure 5 The timing diagram of the latch circuit shown;

[0023] Figure 7 A circuit diagram of another latching circuit provided in an embodiment of the present invention;

[0024] Figure 8 A circuit diagram of another latching circuit provided in an embodiment of the present invention;

[0025] Figure 9 for Figure 8 The timing diagram of the latch circuit shown;

[0026] Figure 10 This is a structural block diagram of another latch circuit provided in an embodiment of the present invention;

[0027] Figure 11 A circuit diagram of another latching circuit provided in an embodiment of the present invention;

[0028] Figure 12 A cross-sectional view of an array substrate provided in an embodiment of the present invention;

[0029] Figure 13 This is a schematic diagram of the structure of a pixel unit provided in an embodiment of the present invention;

[0030] Figure 14 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention;

[0031] Figure 15 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention;

[0032] Figure 16 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention;

[0033] Figure 17 This is a cross-sectional view of an electrophoretic display device provided in an embodiment of the present invention. Detailed Implementation

[0034] To better understand the above-mentioned objectives, features, and advantages of the present invention, the solutions of the present invention will be further described below. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0035] In the embodiments of this invention, "connection" should be understood as two devices being directly connected, while "electrical connection" should be understood as two devices being connected by other devices, and the two devices being electrically connected through the aforementioned other devices.

[0036] The latching circuit provided in this invention can be applied to display devices, especially those where pixels are held for a long time per frame, such as low-frequency display devices, specifically wearable display devices and electrophoretic display devices. In particular, for electrophoretic display devices, the latching circuit can achieve long-term latching of three types of potential signals (pixel voltages).

[0037] Figure 1 This is a structural block diagram of a latch circuit provided in an embodiment of the present invention. Figure 1As shown, the latching circuit includes: a first inverter 1, a second inverter 2, a third inverter 3, and a fourth inverter 4; the output terminal of the first inverter 1 is connected to the input terminal of the second inverter 2, and the output terminal of the second inverter 2 is electrically connected to the input terminal of the first inverter 1; the first power supply terminals of the first inverter 1 and the second inverter 2 are both connected to a first potential signal; the second power supply terminal of the first inverter 1 is connected to a reference potential signal, and the second power supply terminal of the second inverter 2 is electrically connected to the reference potential signal; the output terminal of the third inverter 3 is connected to the input terminal of the fourth inverter 4, and the output terminal of the fourth inverter 4 is electrically connected to the input terminal of the third inverter 3. The first power supply terminal of inverter 3 and the first power supply terminal of inverter 4 are both connected to the second potential signal. The second power supply terminal of inverter 3 is connected to the reference potential signal, and the second power supply terminal of inverter 4 is electrically connected to the reference potential signal. The first potential signal and the second potential signal are opposite in sign to the reference potential signal. Inverter 2 is used to output the first potential signal or the reference potential signal, and the output potential signal is the same type of potential signal as the potential signal input to inverter 1. Inverter 4 is used to output the second potential signal or the reference potential signal, and the output potential signal is the same type of potential signal as the potential signal input to inverter 3.

[0038] In this embodiment of the invention, the type of potential signal refers to the positive or negative state of the potential signal or a reference potential signal. The positive or negative value of the potential signal is relative to the reference potential signal. For example, if the potential signal is greater than the reference potential signal, it is a positive potential signal; if the potential signal is less than the reference potential signal, it is a negative potential signal. The latch circuit provided in this embodiment mainly latches the type of the input potential signal. The magnitude of the potential signal output by the latch circuit can be equal to or different from the magnitude of the input potential signal, depending on the actual application. This invention does not impose any limitations on this. It should be noted that both the first inverter 1 and the third inverter 3 have operating voltage thresholds. When the difference between the input potential signal and the reference potential signal is less than or equal to the operating voltage threshold, the input potential signal is still considered equal to the reference potential signal.

[0039] In the above latch circuit, the output of the first inverter 1 is connected to the input of the second inverter 2, and the output of the second inverter 2 is electrically connected to the input of the first inverter 1, so that the first inverter 1 and the second inverter 2 constitute a latch, called the first latch; the output of the third inverter 3 is connected to the input of the fourth inverter 4, and the output of the fourth inverter 4 is electrically connected to the input of the third inverter 3, so that the third inverter 3 and the fourth inverter 4 also constitute a latch, called the second latch. Any of the above latches can operate in both write and latch states. Taking the first latch as an example, when the first latch is in the write state, the input terminal of the first inverter 1 receives an externally input potential signal, and the output terminal of the second inverter 2 is disconnected from the input terminal of the first inverter 1. At this time, the input potential signal is written into the first latch, and a potential signal of the same type as the input potential signal is output from the output terminal of the second inverter 2. When the first latch is in the latch state, there is no external potential signal input to the input terminal of the first inverter 1, and the output terminal of the second inverter 2 is connected to the input terminal of the first inverter 1. The second inverter 2 feeds back the output potential signal to the input terminal of the first inverter 1, so that the output terminal of the second inverter 2 maintains the original potential signal output.

[0040] Furthermore, by connecting the first power supply terminal of the first inverter 1 and the first power supply terminal of the second inverter 2 to the first potential signal, and connecting the second power supply terminal of the first inverter 1 to the reference potential signal, and electrically connecting the second power supply terminal of the second inverter 2 to the reference potential signal, the first latch can output and latch a first potential signal or a reference potential signal of the same type as the input potential signal according to the input potential signal. Simultaneously, by connecting the first power supply terminal of the third inverter 3 and the first power supply terminal of the fourth inverter 4 to the second potential signal, and connecting the second power supply terminal of the third inverter 3 to the reference potential signal, and electrically connecting the second power supply terminal of the fourth inverter 4 to the reference potential signal, the second latch can output and latch a second potential signal or a reference potential signal of the same type as the input potential signal according to the input potential signal.

[0041] In one optional embodiment, the output terminals of the second inverter 2 and the fourth inverter 4 serve as the output terminals of a latching circuit. In this case, the output terminals of the second inverter 2 and the fourth inverter 4 are connected. Therefore, to avoid conflict between the potential signals output by the second inverter 2 and the fourth inverter 4, the second power supply terminal of the second inverter 2 and the reference potential signal, as well as the second power supply terminal of the fourth inverter 4 and the reference potential signal, can be controlled to allow both the second inverter 2 and the fourth inverter 4 to simultaneously output the reference potential signal, or only the second inverter 2 to output the first potential signal, or only the fourth inverter 4 to output the second potential signal (see specific examples below for a detailed description).

[0042] In another optional embodiment, the potential signals output by the second inverter 2 and the fourth inverter 4 serve as intermediate control quantities. Combined with the node signals in the latch circuit, they control the selection of one preset level signal from three preset level signals as the output signal of the latch circuit. When the potential signals output by the second inverter 2 and the fourth inverter 4 are latched, i.e., when the output is maintained, the corresponding preset level signal is also maintained. Thus, by setting the positive or negative of the preset level signal, the latching function can be achieved (see the specific examples below for a detailed description).

[0043] The latch circuit provided in this embodiment of the invention employs four inverters. When a potential signal (such as an image signal) is input to the latch circuit, the four inverters work together to ensure that the latch circuit outputs a first potential signal, a reference potential signal, or a second potential signal of the same type as the input potential signal, thereby achieving fast writing of the input signal. Furthermore, when the input signal disappears, the latch circuit operates in a latching state, that is, the latch circuit feeds back the output potential signal to its input terminal. Since the potential signal output by the latch circuit is of the same type as the previously input potential signal, the latch circuit maintains the output of the input signal, i.e., latches the input signal, until a different type of potential signal is input, at which point the output of the latch circuit will change accordingly. Therefore, the technical solution of this invention can achieve long-term latching of the input signal.

[0044] Figure 2 A circuit diagram of a latching circuit provided for an embodiment of the present invention. In one embodiment, such as... Figure 2As shown, the first inverter 1 includes a first PMOS transistor T1 and a first NMOS transistor T2. The source of the first PMOS transistor T1 is connected to the first power supply terminal of the first inverter 1, and the source of the first NMOS transistor T2 is connected to the second power supply terminal of the first inverter 1. The gates of both the first PMOS transistor T1 and the first NMOS transistor T2 are connected to the input terminal of the first inverter 1, and the drains of both the first PMOS transistor T1 and the first NMOS transistor T2 are connected to the output terminal of the first inverter 1. The second inverter 2 includes a second PMOS transistor T3 and a second NMOS transistor T4. The source of the second PMOS transistor T3 is connected to the first power supply terminal of the second inverter 2, and the source of the second NMOS transistor T4 is connected to the second power supply terminal of the second inverter 2. The gates of both the second PMOS transistor T3 and the second NMOS transistor T4 are connected to the input terminal of the second inverter 2, and the drains of both the second PMOS transistor T3 and the second NMOS transistor T4 are connected to the output terminal of the second inverter 2. The third inverter 3 includes a third PMOS transistor T3 and a second NMOS transistor T4. The third inverter 3 consists of a PMOS transistor T5 and a third NMOS transistor T6. The source of the third NMOS transistor T6 is connected to the first power supply terminal of the third inverter 3, and the source of the third PMOS transistor T5 is connected to the second power supply terminal of the third inverter 3. The gates of both the third NMOS transistor T6 and the third PMOS transistor T5 are connected to the input terminal of the third inverter 3, and the drains of both the third NMOS transistor T6 and the third PMOS transistor T5 are connected to the output terminal of the third inverter 3. The fourth inverter 4 includes a fourth PMOS transistor T7 and a fourth NMOS transistor T8. The source of the fourth NMOS transistor T8 is connected to the first power supply terminal of the fourth inverter 4, and the source of the fourth PMOS transistor T7 is connected to the second power supply terminal of the fourth inverter 4. The gates of both the fourth NMOS transistor T8 and the fourth PMOS transistor T7 are connected to the input terminal of the fourth inverter 4, and the drains of both the fourth NMOS transistor T8 and the fourth PMOS transistor T7 are connected to the output terminal of the fourth inverter 4. The first potential signal VDD is greater than the second potential signal VEE.

[0045] This embodiment uses one PMOS transistor and one NMOS transistor to form an inverter, which has a simple structure and is easy to set up.

[0046] Optionally, the first potential signal VDD is a high potential signal (e.g., +15V), the second potential signal VEE is a low potential signal (e.g., -15V), and the reference potential signal is the ground signal GND.

[0047] Optionally, the output terminals of the second inverter 2 and the fourth inverter 4 are used as the output terminal Vp of the latch circuit. In this case, the input terminal of the first inverter 1 and the input terminal of the third inverter 3 are connected and used as the input terminal of the latch circuit. The output terminals of the second inverter 2 and the fourth inverter 4 are connected and then connected to the input terminal of the latch circuit to realize feedback of the output potential signal, thereby realizing the latching function.

[0048] Specifically, the threshold voltage of any of the above PMOS transistors is Vthp (Vthp<0), the threshold voltage of any of the NMOS transistors is Vthn (Vthn>0), and the input potential signal is Vin. When Vin>Vthn (that is, Vin is a high potential signal), the first PMOS transistor T1 is turned off, and the first NMOS transistor T2 is turned on. At this time, the signal at node N1 is the ground signal GND, then the second PMOS transistor T3 is turned on, the second NMOS transistor T4 is turned off, and the first potential signal VDD is output to the output terminal Vp of the latch circuit via the second PMOS transistor T3; in addition, the third PMOS transistor T5 is turned off, and the third NMOS transistor T6 is turned on. At this time, the signal at node N2 is the second potential signal VEE, then the fourth PMOS transistor T7 is turned on, the fourth NMOS transistor T8 is turned off, and the source of the fourth PMOS transistor T7 is controlled to be disconnected from the ground signal GND, so that the output terminal Vp of the latch circuit finally outputs the first potential signal VDD. When Vin<Vthp (that is, Vin is a low potential signal), the first PMOS transistor T1 is turned on, and the first NMOS transistor T2 is turned off. At this time, the signal at node N1 is the first potential signal VDD, then the second PMOS transistor T3 is turned off, the second NMOS transistor T4 is turned on, and the source of the second NMOS transistor T4 is controlled to be disconnected from the ground signal GND; in addition, the third PMOS transistor T5 is turned on, and the third NMOS transistor T6 is turned off. At this time, the signal at node N2 is the ground signal GND, then the fourth PMOS transistor T7 is turned off, the fourth NMOS transistor T8 is turned on, and the second potential signal VEE is output to the output terminal Vp of the latch circuit via the fourth NMOS transistor T8, so that the output terminal Vp of the latch circuit finally outputs the second potential signal VEE. When Vthp<Vin<Vthn (that is, Vin is a ground signal), the first PMOS transistor T1 is turned on, and the first NMOS transistor T2 is turned off. At this time, the signal at node N1 is the first potential signal VDD, then the second PMOS transistor T3 is turned off, and the second NMOS transistor T4 is turned on; in addition, the third PMOS transistor T5 is turned off, and the third NMOS transistor T6 is turned on. At this time, the signal at node N2 is the second potential signal VEE, then the fourth PMOS transistor T7 is turned on, and the fourth NMOS transistor T8 is turned off; meanwhile, the source of the second NMOS transistor T4 is controlled to be connected to the ground signal GND, and / or the source of the fourth PMOS transistor T7 is controlled to be connected to the ground signal GND, and the ground signal GND is output to the output terminal Vp of the latch circuit via the second NMOS transistor T4 and / or the fourth PMOS transistor T7, so that the output terminal Vp of the latch circuit finally outputs the ground signal GND. In this way, the latch circuit realizes the output of a high potential signal, a low potential signal or a ground signal. Similarly, based on the above principle, the latch circuit can realize the latching of a high potential signal, a low potential signal or a ground signal.

[0049] Figure 3 A circuit diagram of another latching circuit provided in an embodiment of the present invention. In one embodiment, such as... Figure 3 As shown, the latching circuit also includes a first output control switch 11 and a second output control switch 12. The second power supply terminal of the second inverter 2 is electrically connected to the reference potential signal (ground signal GND) through the first output control switch 11, and the second power supply terminal of the fourth inverter 4 is electrically connected to the reference potential signal (ground signal GND) through the second output control switch 12. The first output control switch 11 is used to connect the second power supply terminal of the second inverter 2 to the reference potential signal when the potential signal input to the first inverter 1 and the reference potential signal are of the same type, and when the potential signal input to the first inverter 1 and the reference potential signal are of different types (at this time the input potential signal is the second potential signal), and the second inverter 2 does not output the first potential signal. When the signal is received, the electrical connection between the second power supply terminal of the second inverter 2 and the reference potential signal is disconnected to prevent the reference potential signal from interfering with the second potential signal output by the fourth inverter 4. The second output control switch 12 is used to connect the electrical connection between the second power supply terminal of the fourth inverter 4 and the reference potential signal when the potential signal input to the third inverter 3 and the reference potential signal are of the same type, and to disconnect the electrical connection between the second power supply terminal of the fourth inverter 4 and the reference potential signal when the potential signal input to the third inverter 3 and the reference potential signal are of different types (at this time the input potential signal is the first potential signal) and the fourth inverter 4 does not output the second potential signal, to prevent the reference potential signal from interfering with the first potential signal output by the second inverter 2. Therefore, this embodiment realizes the on / off control of the second power supply terminal of the second inverter 2 and the reference potential signal by setting the first output control switch 11 and the second output control switch 12, and the on / off control of the second power supply terminal of the fourth inverter 4 and the reference potential signal, thereby realizing the output and latching of the first potential signal, the second potential signal or the reference potential signal by the latching circuit, and avoiding the output potential signal from conflicting.

[0050] Optionally, the control terminals of the first and second output control switches are connected to an external control signal. That is, the first and second output control switches can be independently controlled by an external control component, thereby improving the flexibility of controlling them. For example, when controlling the latch circuit to output a reference potential signal, either the first or second output control switch can be turned on, or both can be turned on simultaneously.

[0051] Optionally, Figure 4 A circuit diagram of another latching circuit provided in an embodiment of the present invention. For example... Figure 4As shown in the figure, the first output control switch includes a fifth PMOS transistor T9, the control terminal of the fifth PMOS transistor T9 is connected to the output terminal of the third inverter 3, the second output control switch includes a fifth NMOS transistor T10, and the control terminal of the fifth NMOS transistor T10 is connected to the output terminal of the first inverter 1. In this alternative solution, the second NMOS transistor T4 is electrically connected to the ground signal GND through the fifth PMOS transistor T9, and the fourth PMOS transistor T7 is electrically connected to the ground signal GND through the fifth NMOS transistor T10. Based on the description of the foregoing embodiments, when Vin>Vthn (that is, Vin is a high potential signal), the signal at node N1 is the ground signal GND, the fifth NMOS transistor T10 is turned off, the signal at node N2 is the second potential signal VEE, the fifth PMOS transistor T9 is turned on, but the second NMOS transistor T4 is turned off, which does not affect the output terminal Vp of the latch circuit to finally output the first potential signal VDD. When Vin<Vthp (that is, Vin is a low potential signal), the signal at node N1 is the first potential signal VDD, the fifth NMOS transistor T10 is turned on, the signal at node N2 is the ground signal GND, the fifth PMOS transistor T9 is turned off, but the fourth PMOS transistor T7 is turned off, which does not affect the output terminal Vp of the latch circuit to finally output the second potential signal VEE. When Vthp<Vin<Vthn (that is, Vin is a ground signal), the signal at node N1 is the first potential signal VDD, the fifth NMOS transistor T10 is turned on, the signal at node N2 is the second potential signal VEE, and the fifth PMOS transistor T9 is turned on, so that the output terminal Vp of the latch circuit finally outputs the ground signal GND. Therefore, this alternative solution controls the on and off states of the first output control switch and the second output control switch through the node signals inside the latch circuit, which saves external control components and reduces the wiring difficulty for the control terminals of the first output control switch and the second output control switch.

[0052] Figure 5 is a circuit diagram of another latch circuit provided by an embodiment of the present invention. In one embodiment, as shown in Figure 5 the figure, the latch circuit further includes a first pixel switch T11 and a first latch switch T12, and the on-off states of the first pixel switch T11 and the first latch switch T12 are opposite; the gate of the first pixel switch T11 is connected to the gate of the first latch switch T12, the first pole of the first pixel switch T11 is respectively connected to the input terminal of the first inverter 1 and the input terminal of the third inverter 3, the output terminal of the second inverter 2 is electrically connected to the input terminal of the first inverter 1 through the first latch switch T12, and the output terminal of the fourth inverter 4 is electrically connected to the input terminal of the third inverter 3 through the first latch switch T12. Optionally, the first pixel switch T11 is an NMOS transistor, and the first latch switch T12 is a PMOS transistor.

[0053] This embodiment achieves the writing and latching of the input potential signal by setting a first pixel switch T11 and a first latch switch T12. Specifically, combined with Figure 6 When the scan signal Gate controls the first pixel switch T11 to turn on, the first latch switch T12 turns off. The data signal Data is written to the input terminals of the first inverter 1 and the third inverter 3 via the first pixel switch T11. For example, if the data signal Data is a high-level signal, the output terminal Vp of the latch circuit outputs a high-level signal, realizing the writing function of the latch circuit. When the scan signal Gate controls the first pixel switch T11 to turn off, the first latch switch T12 turns on. At this time, the output terminal Vp of the latch circuit outputs a high-level signal, which is fed back to the input terminals of the first inverter 1 and the third inverter 3 via the first latch switch T12, so that the output terminal Vp of the latch circuit still outputs a high-level signal, realizing the latching function of the latch circuit. Subsequently, when the scan signal Gate controls the first pixel switch T11 to turn on again, the first latch switch T12 turns off, and the data signal Data becomes a low-level signal. This low-level signal is written to the input terminals of the first inverter 1 and the third inverter 3 via the first pixel switch T11. At this time, the potential signal output by the latch circuit's output terminal Vp changes from a high-level signal to a low-level signal. Thus, the potential signal output by the latch circuit's output terminal Vp only changes when the type of the potential signal input to the first inverter 1 and the third inverter 3 changes, achieving long-term latching of the potential signal.

[0054] Figure 7 A circuit diagram of another latching circuit provided in an embodiment of the present invention. In one embodiment, such as... Figure 7As shown, the latching circuit also includes a first pixel switch T11, a second pixel switch T13, a first latch switch T12, a second latch switch T14, a first gating unit 5, a second gating unit 6, and a third gating unit 7. The first pixel switch T11 and the second pixel switch T13 have the same on / off state, the first pixel switch T11 and the first latch switch T12 have opposite on / off states, and the second pixel switch T13 and the second latch switch T14 have opposite on / off states. The gate of the first pixel switch T11 and the second pixel switch T14 are connected in series. The gates of switch T13, T12, and T14 are interconnected. The first terminal of the first pixel switch T11 is connected to the input of the first inverter 1. The first terminal of the second pixel switch T13 is connected to the input of the third inverter 3. The output of the second inverter 2 is electrically connected to the input of the first inverter 1 via the first latch switch T12. The output of the fourth inverter 4 is electrically connected to the input of the third inverter 3 via the second latch switch T14. The input of the first gating unit 5... The input terminal of the first gating unit 5 is connected to the first level signal VA, the input terminal of the second gating unit 6 is connected to the second level signal VB, and the input terminal of the third gating unit 7 is connected to the third level signal VC. The output terminals of the first gating unit 5, the second gating unit 6, and the third gating unit 7 are interconnected. The first gating unit 5 is controlled by the output signal of the first inverter 1 (N1 node signal) and the output signal of the second inverter 2 (P1 node signal) to turn on or off the connection between the input terminal and the output terminal of the first gating unit 5. The second gating unit 6 is controlled by the output signal of the first inverter 1 and the output signal of the third inverter 3 (N2 node signal) to turn on or off the connection between the input terminal and the output terminal of the second gating unit 6. The third gating unit 7 is controlled by the output signal of the third inverter 3 and the output signal of the fourth inverter 4 (P2 node signal) to turn on or off the connection between the input terminal and the output terminal of the third gating unit 7. At any given time, only one of the first gating unit 5, the second gating unit 6, and the third gating unit 7 is on.

[0055] In this embodiment, the first level signal VA, the second level signal VB, and the third level signal VC are output under the sole control of node signals, and will not affect the latching function of the latch circuit. Therefore, the first level signal VA, the second level signal VB, and the third level signal VC can be fixed level signals or variable level signals, which improves the flexibility of the output signal of the latch circuit. In addition, the input ends and output ends of the first latch and the second latch are independent of each other. The first potential signal VDD and the second potential signal VEE will not be applied to the source and drain terminals of the second PMOS transistor T3 and the fourth NMOS transistor T8 at the same time, which reduces the voltage difference between the source and drain terminals of the second PMOS transistor T3 and the fourth NMOS transistor T8, thereby lowering the requirement for the withstand voltage characteristics of the source and drain terminals of the second PMOS transistor T3 and the fourth NMOS transistor T8, and improving reliability.

[0056] In a specific example, when Vin1>Vthn and Vthp<Vin2<Vthn, the node signal of node N1 is the ground signal GND, the node signal of node N2 is the second potential signal VEE, the node signal of node P1 is the first potential signal VDD, and the node signal of node P2 is the ground signal GND. At this time, the first gating unit 5 is gated, and the output terminal OUT of the latch circuit outputs the first level signal VA. When Vthp<Vin1<Vthn and Vthp<Vin2<Vthn, the node signal of node N1 is the first potential signal VDD, the node signal of node N2 is the second potential signal VEE, the node signal of node P1 is the ground signal GND, and the node signal of node P2 is the ground signal GND. At this time, the second gating unit 6 is gated, and the output terminal OUT of the latch circuit outputs the second level signal VB. When Vthp<Vin1<Vthn and Vin2<Vthp, the node signal of node N1 is the first potential signal VDD, the node signal of node N2 is the ground signal GND, the node signal of node P1 is the ground signal GND, and the node signal of node P2 is the second potential signal VEE. At this time, the third gating unit 7 is gated, and the output terminal OUT of the latch circuit outputs the third level signal VC.

[0057] Optionally, as Figure 8As shown, the first selection unit includes a sixth PMOS transistor T15 and a sixth NMOS transistor T16. The gate of the sixth PMOS transistor T15 is connected to the output terminal of the first inverter 1, and the gate of the sixth NMOS transistor T16 is connected to the output terminal of the second inverter 2. The first terminals of both the sixth PMOS transistor T15 and the sixth NMOS transistor T16 are connected to a first-level signal. The second selection unit includes a seventh PMOS transistor T17 and a seventh NMOS transistor T18. The gate of the seventh NMOS transistor T18 is connected to the output terminal of the first inverter 1, and the gate of the seventh PMOS transistor T17 is connected to the output terminal of the third inverter 3. The first terminal of the seventh PMOS transistor T17 is connected to a second-level signal. The second terminal of PMOS transistor T17 is connected to the first terminal of the seventh NMOS transistor T18; the third gating unit includes the eighth PMOS transistor T19 and the eighth NMOS transistor T20. The gate of the eighth PMOS transistor T19 is connected to the output terminal of the fourth inverter 4, and the gate of the eighth NMOS transistor T20 is connected to the output terminal of the third inverter 3. The first terminals of the eighth PMOS transistor T19 and the eighth NMOS transistor T20 are both connected to the third level signal. The second terminals of the sixth PMOS transistor T15, the sixth NMOS transistor T16, the seventh NMOS transistor T18, the eighth PMOS transistor T19, and the eighth NMOS transistor T20 are interconnected.

[0058] Based on the above embodiments, specifically, when Vin1>Vthn and Vthp<Vin2<Vthn, the signal at node N1 is the ground signal GND, the signal at node N2 is the second potential signal VEE, the signal at node P1 is the first potential signal VDD, and the signal at node P2 is the ground signal GND. At this time, the sixth NMOS transistor T16 is turned on, the sixth PMOS transistor T15, the seventh PMOS transistor T17, the seventh NMOS transistor T18, the eighth PMOS transistor T19 and the eighth NMOS transistor T20 are turned off, and the output terminal OUT of the latch circuit outputs the first level signal VA. When Vthp<Vin1<Vthn and Vthp<Vin2<Vthn, the signal at node N1 is the first potential signal VDD, the signal at node N2 is the second potential signal VEE, the signal at node P1 is the ground signal GND, and the signal at node P2 is the ground signal GND. At this time, the seventh PMOS transistor T17 and the seventh NMOS transistor T18 are turned on, the sixth PMOS transistor T15, the sixth NMOS transistor T16, the eighth PMOS transistor T19 and the eighth NMOS transistor T20 are turned off, and the output terminal OUT of the latch circuit outputs the second level signal VB. When Vthp<Vin1<Vthn and Vin2<Vthp, the signal at node N1 is the first potential signal VDD, the signal at node N2 is the ground signal GND, the signal at node P1 is the ground signal GND, and the signal at node P2 is the second potential signal VEE. At this time, the eighth PMOS transistor T19 is turned on, the sixth PMOS transistor T15, the sixth NMOS transistor T16, the seventh PMOS transistor T17, the seventh NMOS transistor T18 and the eighth NMOS transistor T20 are turned off, and the output terminal OUT of the latch circuit outputs the third level signal VC. Figure 9 shows a driving timing diagram of the latch circuit when the first level signal VA is a variable high level signal, the second level signal VB is a ground signal (0), and the third level signal VC is a variable low level signal.

[0059] The embodiment of the present invention further provides another latch circuit, Figure 10 is a structural block diagram of another latch circuit provided by the embodiment of the present invention. As shown in Figure 10As shown, the latching circuit includes: a first inverter 1, a second inverter 2, a third inverter 3, and a fourth inverter 4; the output terminal of the first inverter 1 is connected to the input terminal of the second inverter 2, the output terminal of the second inverter 2 is electrically connected to the input terminal of the first inverter 1, the input terminal of the first inverter 1 is connected to the input terminal of the third inverter 3, the first power supply terminal of the first inverter 1 and the first power supply terminal of the second inverter 2 are both connected to a first potential signal; the output terminal of the third inverter 3 is connected to the input terminal of the fourth inverter 4, the output terminal of the fourth inverter 4 is connected to the second power supply terminal of the first inverter 1 and the second power supply terminal of the second inverter 2 respectively, the first power supply terminal of the third inverter 3 and the first power supply terminal of the fourth inverter 4 are both connected to a second potential signal, the second power supply terminal of the third inverter 3 and the second power supply terminal of the fourth inverter 4 are both connected to a reference potential signal, and the first potential signal and the second potential signal are opposite in sign to the reference potential signal.

[0060] In this embodiment, the output terminal of the first inverter 1 is connected to the input terminal of the second inverter 2, and the output terminal of the second inverter 2 is electrically connected to the input terminal of the first inverter 1, so that the first inverter 1 and the second inverter constitute a latch. Under the action of the input potential signal and the potential signal output by the fourth inverter, this latch can output a first potential signal, a second potential signal, or a reference potential signal of the same type as the input potential signal, realizing fast writing and long-term latching of the input potential signal.

[0061] Specifically, such as Figure 11As shown, the first inverter 1 includes a first PMOS transistor T1 and a first NMOS transistor T2. The source of the first PMOS transistor T1 is connected to the first power supply terminal of the first inverter 1, and the source of the first NMOS transistor T2 is connected to the second power supply terminal of the first inverter 1. The gates of both the first PMOS transistor T1 and the first NMOS transistor T2 are connected to the input terminal of the first inverter 1, and the drains of both the first PMOS transistor T1 and the first NMOS transistor T2 are connected to the output terminal of the first inverter 1. The second inverter 2 includes a second PMOS transistor T3 and a second NMOS transistor T4. The source of the second PMOS transistor T3 is connected to the first power supply terminal of the second inverter 2, and the source of the second NMOS transistor T4 is connected to the second power supply terminal of the second inverter 2. The gates of both the second PMOS transistor T3 and the second NMOS transistor T4 are connected to the input terminal of the second inverter 2, and the drains of both the second PMOS transistor T3 and the second NMOS transistor T4 are connected to the output terminal of the second inverter 2. The third inverter 3 includes a third PMOS transistor T3 and a second NMOS transistor T4. The third inverter 3 consists of a PMOS transistor T5 and a third NMOS transistor T6. The source of the third NMOS transistor T6 is connected to the first power supply terminal of the third inverter 3, and the source of the third PMOS transistor T5 is connected to the second power supply terminal of the third inverter 3. The gates of both the third NMOS transistor T6 and the third PMOS transistor T5 are connected to the input terminal of the third inverter 3, and the drains of both the third NMOS transistor T6 and the third PMOS transistor T5 are connected to the output terminal of the third inverter 3. The fourth inverter 4 includes a fourth PMOS transistor T7 and a fourth NMOS transistor T8. The source of the fourth NMOS transistor T8 is connected to the first power supply terminal of the fourth inverter 4, and the source of the fourth PMOS transistor T7 is connected to the second power supply terminal of the fourth inverter 4. The gates of both the fourth NMOS transistor T8 and the fourth PMOS transistor T7 are connected to the input terminal of the fourth inverter 4, and the drains of both the fourth NMOS transistor T8 and the fourth PMOS transistor T7 are connected to the output terminal of the fourth inverter 4. The first potential signal VDD is greater than the second potential signal VEE.

[0062] Optionally, the first potential signal VDD is a high potential signal (e.g., +15V), the second potential signal VEE is a low potential signal (e.g., -15V), and the reference potential signal is the ground signal GND.

[0063] Exemplarily, the threshold voltage of any of the above PMOS transistors is Vthp (Vthp<0), the threshold voltage of any of the NMOS transistors is Vthn (Vthn>0), and the input potential signal is Vin. When Vin>Vthn (that is, Vin is a high potential signal), the first PMOS transistor T1 is turned off, the first NMOS transistor T2 is turned on, the third PMOS transistor T5 is turned off, and the third NMOS transistor T6 is turned on. At this time, the signal at node N2 is the second potential signal VEE, then the fourth PMOS transistor T7 is turned on, the fourth NMOS transistor T8 is turned off, the ground signal GND is output from the output terminal of the fourth inverter 4 via the fourth PMOS transistor T7, so that the signal at node N1 is the ground signal GND, then the second PMOS transistor T3 is turned on, the second NMOS transistor T4 is turned off, the first potential signal VDD is output to the output terminal Vp of the latch circuit via the second PMOS transistor T3, and the latch circuit outputs the first potential signal VDD. When Vin<Vthp (that is, Vin is a low potential signal), the first PMOS transistor T1 is turned on, the first NMOS transistor T2 is turned off, the third PMOS transistor T5 is turned on, and the third NMOS transistor T6 is turned off. At this time, the signal at node N2 is the ground signal GND, then the fourth PMOS transistor T7 is turned off, the fourth NMOS transistor T8 is turned on, and the second potential signal VEE is output from the output terminal of the fourth inverter 4 via the fourth NMOS transistor T8; at the same time, the signal at node N1 is the first potential signal VDD, then the second PMOS transistor T3 is turned off, the second NMOS transistor T4 is turned on, the second potential signal VEE is output to the output terminal Vp of the latch circuit via the second NMOS transistor T4, and the latch circuit outputs the second potential signal VEE. When Vthp<Vin<Vthn (that is, Vin is a ground signal), the first PMOS transistor T1 is turned on, the first NMOS transistor T2 is turned off, the third PMOS transistor T5 is turned off, and the third NMOS transistor T6 is turned on. At this time, the signal at node N2 is the second potential signal VEE, then the fourth PMOS transistor T7 is turned on, the fourth NMOS transistor T8 is turned off, and the ground signal GND is output from the output terminal of the fourth inverter 4 via the fourth PMOS transistor T7; at the same time, the signal at node N1 is the first potential signal VDD, then the second PMOS transistor T3 is turned off, the second NMOS transistor T4 is turned on, the ground signal GND is output to the output terminal Vp of the latch circuit via the second NMOS transistor T4, and the latch circuit outputs the ground signal GND. In this way, the latch circuit realizes the output of a high potential signal, a low potential signal or a ground signal. Similarly, based on the above principle, the latch circuit can realize the latching of a high potential signal, a low potential signal or a ground signal.

[0064] In one embodiment, with continued reference to Figure 11The latching circuit further includes a first pixel switch T11 and a first latching switch T12, whose on / off states are opposite. The gate of the first pixel switch T11 is connected to the gate of the first latching switch T12, and the first terminal of the first pixel switch T11 is connected to the input terminal of the first inverter 1. The output terminal of the second inverter 2 is electrically connected to the input terminal of the first inverter 1 through the first latching switch T12. Optionally, the first pixel switch T11 is an NMOS transistor, and the first latching switch T12 is a PMOS transistor. In this embodiment, by setting the first pixel switch T11 and the first latching switch T12, the writing and latching of the input potential signal are realized. Specifically, when the scan signal Gate controls the first pixel switch T11 to be turned on, the first latch switch T12 is turned off. The data signal Data is written to the input terminals of the first inverter 1 and the third inverter 3 via the first pixel switch T11. For example, if the data signal Data is a high-level signal, the output terminal Vp of the latch circuit outputs a high-level signal, realizing the writing function of the latch circuit. When the scan signal Gate controls the first pixel switch T11 to be turned off, the first latch switch T12 is turned on. At this time, the output terminal Vp of the latch circuit outputs a high-level signal, which is fed back to the input terminals of the first inverter 1 and the third inverter 3 via the first latch switch T12, so that the output terminal Vp of the latch circuit still outputs a high-level signal, realizing the latching function of the latch circuit. Subsequently, when the scan signal Gate controls the first pixel switch T11 to turn on again, the first latch switch T12 turns off, and the data signal Data becomes a low-level signal. This low-level signal is written to the input terminals of the first inverter 1 and the third inverter 3 via the first pixel switch T11. At this time, the potential signal output by the latch circuit's output terminal Vp changes from a high-level signal to a low-level signal. Thus, the potential signal output by the latch circuit's output terminal Vp only changes when the type of the potential signal input to the first inverter 1 and the third inverter 3 changes, achieving long-term latching of the potential signal.

[0065] This invention also provides an array substrate. Figure 12 A cross-sectional view of an array substrate provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of a pixel unit structure provided in an embodiment of the present invention. Figure 12 and Figure 13 As shown, the array substrate includes a substrate 10 and a plurality of pixel units 20 located on one side of the substrate 10. The pixel unit 20 includes a latch circuit 21 provided in any embodiment of the present invention and a pixel electrode 22 located on the side of the latch circuit 21 away from the substrate 10. The output terminal of the latch circuit 21 is electrically connected to the pixel electrode 22.

[0066] In one embodiment, continue to refer to Figure 13The output terminals Vp1 of the second inverter and Vp2 of the fourth inverter serve as output terminals of the latch circuit. The pixel unit also includes a first via at the output terminal Vp1 of the second inverter and a second via at the output terminal Vp2 of the fourth inverter. The output terminal Vp1 of the second inverter is electrically connected to the pixel electrode 22 through the first via, and the output terminal Vp2 of the fourth inverter is electrically connected to the pixel electrode 22 through the second via. Thus, the output terminals Vp1 and Vp2 of the second and fourth inverters are electrically connected to the pixel electrode 22 through vias, thereby achieving a connection between the output terminals Vp1 and Vp2 of the second and fourth inverters. This avoids wiring between the output terminals Vp1 and Vp2 of the second and fourth inverters, reducing the complexity of the manufacturing process.

[0067] In one embodiment, Figure 14 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention. For example... Figure 14 As shown, the latching circuit also includes a first pixel switch T11 and a first latching switch T12. The pixel unit also includes a third via located at the first electrode Vp' of the first latching switch T12. The first electrode Vp' of the first latching switch T12 is electrically connected to the pixel electrode 22 through the third via. In this way, the potential signal output by the latching circuit is fed back to the first latching switch T12 through the pixel electrode 22, avoiding wiring between the first electrode Vp' of the first latching switch T12 and the output terminal of the latching circuit, thus reducing the manufacturing process complexity.

[0068] In one embodiment, continue to refer to Figure 14Multiple pixel units are arranged in multiple rows and columns. The array substrate also includes multiple scan lines (signal lines for transmitting scan signals Gate) extending along the row direction and arranged along the column direction, as well as multiple data lines (signal lines for transmitting data signals Data), multiple first potential signal lines (signal lines for transmitting first potential signals VDD), multiple second potential signal lines (signal lines for transmitting second potential signals VEE), and multiple reference potential signal lines (signal lines for transmitting reference potential signals GND) extending along the column direction and arranged along the row direction. In the same row of pixel units, the gate of the first pixel switch T11 and the gate of the first latch switch T12 are both connected to the same scan line; in the same column of pixel units... In the first pixel switch T11, the second electrode is connected to the same data line. The first power supply terminal of the first inverter and the first power supply terminal of the second inverter are both connected to the same first potential signal line. The second power supply terminal of the first inverter and the second power supply terminal of the third inverter are both connected to the same reference potential signal line. The second power supply terminal of the second inverter and the second power supply terminal of the fourth inverter are both electrically connected to the same reference potential signal line. The first power supply terminal of the third inverter and the first power supply terminal of the fourth inverter are both connected to the same second potential signal line. In the direction perpendicular to the plane of the substrate, the pixel electrode 22 overlaps with the first potential signal line, the second potential signal line and the reference potential signal line, respectively.

[0069] In one embodiment, reference Figure 15 The output terminals OUT1 of the first gating unit, OUT2 of the second gating unit, and OUT3 of the third gating unit serve as the output terminals of the latch circuit (corresponding to...). Figure 8 (Structure shown); the pixel unit also includes a first via at the output terminal OUT1 of the first gating unit (including T15 and T16), a second via at the output terminal OUT2 of the second gating unit (including T17 and T18), and a third via at the output terminal OUT3 of the third gating unit (including T19 and T20). The output terminal OUT1 of the first gating unit is electrically connected to the pixel electrode 22 through the first via, the output terminal OUT2 of the second gating unit is electrically connected to the pixel electrode 22 through the second via, and the output terminal OUT3 of the third gating unit is electrically connected to the pixel electrode 22 through the third via. Similarly, wiring between the output terminals OUT1 of the first gating unit, OUT2 of the second gating unit, and OUT3 of the third gating unit can be avoided, reducing the process complexity.

[0070] In one embodiment, reference Figure 16 The output terminal Vp of the second inverter (including T3 and T4) serves as the output terminal of the latch circuit (corresponding to...). Figure 11(Structure shown); the latching circuit also includes a first pixel switch T11 and a first latching switch T12. The pixel unit also includes a first via located at the output terminal Vp of the second inverter and a second via located at the first electrode Vp' of the first latching switch T12. The output terminal Vp of the second inverter is electrically connected to the pixel electrode 22 through the first via, and the first electrode Vp' of the first latching switch T12 is electrically connected to the pixel electrode 22 through the second via. Similarly, wiring between the output terminal Vp of the second inverter and the first electrode Vp' of the first latching switch T12 can be avoided, reducing the manufacturing process difficulty.

[0071] This invention also provides an electrophoresis display device. Figure 17 This is a cross-sectional view of an electrophoretic display device provided in an embodiment of the present invention. Figure 17 As shown, the electrophoretic display device includes an array substrate 100, a common electrode layer 200, and an electrophoretic membrane 300 located between the array substrate 100 and the common electrode layer 200, as provided in any embodiment of the present invention.

[0072] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0073] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A latching circuit, characterized in that, include: First inverter, second inverter, third inverter, and fourth inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter. The first power supply terminal of the first inverter and the first power supply terminal of the second inverter are both connected to a first potential signal. The second power supply terminal of the first inverter is connected to a reference potential signal, and the second power supply terminal of the second inverter is electrically connected to the reference potential signal. The output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is electrically connected to the input terminal of the third inverter. The first power supply terminals of the third inverter and the fourth inverter are both connected to the second potential signal. The second power supply terminal of the third inverter is connected to the reference potential signal, and the second power supply terminal of the fourth inverter is electrically connected to the reference potential signal. Relative to the reference potential signal, the first potential signal and the second potential signal have opposite signs. The second inverter is used to output the first potential signal or the reference potential signal, and the output potential signal is the same type of potential signal as the potential signal input to the first inverter; the fourth inverter is used to output the second potential signal or the reference potential signal, and the output potential signal is the same type of potential signal as the potential signal input to the third inverter.

2. The latching circuit according to claim 1, characterized in that, The first inverter includes a first PMOS transistor and a first NMOS transistor. The source of the first PMOS transistor is connected to the first power supply terminal of the first inverter, the source of the first NMOS transistor is connected to the second power supply terminal of the first inverter, the gates of the first PMOS transistor and the first NMOS transistor are both connected to the input terminal of the first inverter, and the drains of the first PMOS transistor and the first NMOS transistor are both connected to the output terminal of the first inverter. The second inverter includes a second PMOS transistor and a second NMOS transistor. The source of the second PMOS transistor is connected to the first power supply terminal of the second inverter, the source of the second NMOS transistor is connected to the second power supply terminal of the second inverter, the gates of the second PMOS transistor and the second NMOS transistor are both connected to the input terminal of the second inverter, and the drains of the second PMOS transistor and the second NMOS transistor are both connected to the output terminal of the second inverter. The third inverter includes a third PMOS transistor and a third NMOS transistor. The source of the third NMOS transistor is connected to the first power supply terminal of the third inverter, the source of the third PMOS transistor is connected to the second power supply terminal of the third inverter, the gates of the third NMOS transistor and the third PMOS transistor are both connected to the input terminal of the third inverter, and the drains of the third NMOS transistor and the third PMOS transistor are both connected to the output terminal of the third inverter. The fourth inverter includes a fourth PMOS transistor and a fourth NMOS transistor. The source of the fourth NMOS transistor is connected to the first power supply terminal of the fourth inverter, the source of the fourth PMOS transistor is connected to the second power supply terminal of the fourth inverter, the gates of the fourth NMOS transistor and the fourth PMOS transistor are both connected to the input terminal of the fourth inverter, and the drains of the fourth NMOS transistor and the fourth PMOS transistor are both connected to the output terminal of the fourth inverter. Wherein, the first potential signal is greater than the second potential signal.

3. The latching circuit according to claim 2, characterized in that, It also includes a first output control switch and a second output control switch. The second power supply terminal of the second inverter is electrically connected to the reference potential signal through the first output control switch, and the second power supply terminal of the fourth inverter is electrically connected to the reference potential signal through the second output control switch. The first output control switch is used to connect the second power supply terminal of the second inverter to the reference potential signal when the potential signal input to the first inverter is of the same type as the reference potential signal, and to disconnect the second power supply terminal of the second inverter from the reference potential signal when the potential signal input to the first inverter is of a different type from the reference potential signal and the second inverter does not output the first potential signal. The second output control switch is used to connect the second power supply terminal of the fourth inverter to the reference potential signal when the potential signal input to the third inverter is of the same type as the reference potential signal, and to disconnect the second power supply terminal of the fourth inverter from the reference potential signal when the potential signal input to the third inverter is of a different type than the reference potential signal and the fourth inverter does not output the second potential signal.

4. The latching circuit according to claim 3, characterized in that, The control terminals of the first output control switch and the second output control switch are connected to external control signals.

5. The latching circuit according to claim 3, characterized in that, The first output control switch includes a fifth PMOS transistor, the control terminal of which is connected to the output terminal of the third inverter. The second output control switch includes a fifth NMOS transistor, the control terminal of which is connected to the output terminal of the first inverter.

6. The latching circuit according to claim 1, characterized in that, The latching circuit further includes a first pixel switch and a first latching switch, wherein the on / off states of the first pixel switch and the first latching switch are opposite. The gate of the first pixel switch is connected to the gate of the first latch switch. The first terminal of the first pixel switch is connected to the input terminal of the first inverter and the input terminal of the third inverter, respectively. The output terminal of the second inverter is electrically connected to the input terminal of the first inverter through the first latch switch. The output terminal of the fourth inverter is electrically connected to the input terminal of the third inverter through the first latch switch.

7. The latching circuit according to claim 1, characterized in that, The latching circuit further includes a first pixel switch, a second pixel switch, a first latching switch, a second latching switch, a first gating unit, a second gating unit, and a third gating unit. The first pixel switch and the second pixel switch have the same on / off state, the first pixel switch and the first latching switch have opposite on / off states, and the second pixel switch and the second latching switch have opposite on / off states. The gates of the first pixel switch, the second pixel switch, the first latch switch, and the second latch switch are interconnected. The first terminal of the first pixel switch is connected to the input terminal of the first inverter. The first terminal of the second pixel switch is connected to the input terminal of the third inverter. The output terminal of the second inverter is electrically connected to the input terminal of the first inverter through the first latch switch. The output terminal of the fourth inverter is electrically connected to the input terminal of the third inverter through the second latch switch. The input terminal of the first gating unit is connected to a first level signal, the input terminal of the second gating unit is connected to a second level signal, and the input terminal of the third gating unit is connected to a third level signal. The output terminals of the first gating unit, the second gating unit, and the third gating unit are interconnected. The first gating unit is controlled by the output signals of the first inverter and the second inverter to turn on or off the connection between its input terminal and output terminal. The second gating unit is controlled by the output signals of the first inverter and the third inverter to turn on or off the connection between its input terminal and output terminal. The third gating unit is controlled by the output signals of the third inverter and the fourth inverter to turn on or off the connection between its input terminal and output terminal. At any given time, only one of the first gating unit, the second gating unit, and the third gating unit is active.

8. The latching circuit according to claim 7, characterized in that, The first gating unit includes a sixth PMOS transistor and a sixth NMOS transistor. The gate of the sixth PMOS transistor is connected to the output terminal of the first inverter, and the gate of the sixth NMOS transistor is connected to the output terminal of the second inverter. The first terminals of the sixth PMOS transistor and the sixth NMOS transistor are both connected to a first level signal. The second gating unit includes a seventh PMOS transistor and a seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the output terminal of the first inverter, the gate of the seventh PMOS transistor is connected to the output terminal of the third inverter, the first terminal of the seventh PMOS transistor is connected to a second level signal, and the second terminal of the seventh PMOS transistor is connected to the first terminal of the seventh NMOS transistor. The third gating unit includes an eighth PMOS transistor and an eighth NMOS transistor. The gate of the eighth PMOS transistor is connected to the output terminal of the fourth inverter, and the gate of the eighth NMOS transistor is connected to the output terminal of the third inverter. The first terminals of the eighth PMOS transistor and the eighth NMOS transistor are both connected to a third-level signal. The second terminals of the sixth PMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth PMOS transistor, and the eighth NMOS transistor are interconnected.

9. A latching circuit, characterized in that, include: First inverter, second inverter, third inverter, and fourth inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is electrically connected to the input terminal of the first inverter, the input terminal of the first inverter is connected to the input terminal of the third inverter, and the first power supply terminal of the first inverter and the first power supply terminal of the second inverter are both connected to the first potential signal. The output terminal of the third inverter is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the second power supply terminal of the first inverter and the second power supply terminal of the second inverter, respectively. The first power supply terminals of the third inverter and the fourth inverter are both connected to a second potential signal. The second power supply terminals of the third inverter and the fourth inverter are both connected to a reference potential signal. The first potential signal and the second potential signal are opposite in sign to the reference potential signal.

10. The latching circuit according to claim 9, characterized in that, The latching circuit further includes a first pixel switch and a first latching switch, wherein the on / off states of the first pixel switch and the first latching switch are opposite. The gate of the first pixel switch is connected to the gate of the first latch switch, the first terminal of the first pixel switch is connected to the input terminal of the first inverter, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter through the first latch switch.

11. An array substrate, characterized in that, The device includes a substrate and a plurality of pixel units located on one side of the substrate. The pixel units include a latching circuit as described in any one of claims 1-10 and a pixel electrode located on the side of the latching circuit away from the substrate. The output terminal of the latching circuit is electrically connected to the pixel electrode.

12. The array substrate according to claim 11, characterized in that, The output terminals of the second inverter and the fourth inverter serve as the output terminals of the latch circuit. The pixel unit further includes a first via located at the output terminal of the second inverter and a second via located at the output terminal of the fourth inverter. The output terminal of the second inverter is electrically connected to the pixel electrode through the first via, and the output terminal of the fourth inverter is electrically connected to the pixel electrode through the second via.

13. The array substrate according to claim 12, characterized in that, The latching circuit further includes a first pixel switch and a first latching switch. The pixel unit further includes a third via located at the first electrode of the first latching switch. The first electrode of the first latching switch is electrically connected to the pixel electrode through the third via.

14. The array substrate according to claim 13, characterized in that, The multiple pixel units are arranged in multiple rows and columns. The array substrate also includes multiple scan lines extending in the row direction and arranged in the column direction, as well as multiple data lines, multiple first potential signal lines, multiple second potential signal lines and multiple reference potential signal lines extending in the column direction and arranged in the row direction. In the same row of pixel units, the gate of the first pixel switch and the gate of the first latch switch are both connected to the same scan line; in the same column of pixel units, the second terminal of the first pixel switch is connected to the same data line, the first power supply terminal of the first inverter and the first power supply terminal of the second inverter are both connected to the same first potential signal line, the second power supply terminal of the first inverter and the second power supply terminal of the third inverter are both connected to the same reference potential signal line, the second power supply terminal of the second inverter and the second power supply terminal of the fourth inverter are both electrically connected to the same reference potential signal line, and the first power supply terminal of the third inverter and the first power supply terminal of the fourth inverter are both connected to the same second potential signal line. In a direction perpendicular to the plane of the substrate, the pixel electrode overlaps with the first potential signal line, the second potential signal line, and the reference potential signal line, respectively.

15. The array substrate according to claim 11, characterized in that, The output terminals of the first gating unit, the second gating unit, and the third gating unit serve as the output terminals of the latching circuit. The pixel unit further includes a first via located at the output terminal of the first gating unit, a second via located at the output terminal of the second gating unit, and a third via located at the output terminal of the third gating unit. The output terminal of the first gating unit is electrically connected to the pixel electrode through the first via, the output terminal of the second gating unit is electrically connected to the pixel electrode through the second via, and the output terminal of the third gating unit is electrically connected to the pixel electrode through the third via.

16. The array substrate according to claim 11, characterized in that, The output of the second inverter serves as the output of the latch circuit. The latching circuit further includes a first pixel switch and a first latching switch. The pixel unit further includes a first via located at the output terminal of the second inverter and a second via located at the first electrode of the first latching switch. The output terminal of the second inverter is electrically connected to the pixel electrode through the first via, and the first electrode of the first latching switch is electrically connected to the pixel electrode through the second via.

17. An electrophoretic display device, characterized in that, It includes the array substrate, the common electrode layer, and the electrophoretic membrane located between the array substrate and the common electrode layer as described in any one of claims 11-16.

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