Delta-sigma modulator

Abstract

A delta-sigma modulator includes a multiplexer, a modulation circuit, and a demultiplexer. The multiplexer is configured to receive a first analog signal and a second analog signal and output an input signal. The first analog signal and the second analog signal are of different electrical forms, and the multiplexer is configured to output the input signal by selecting the first analog signal or the second analog signal as the input signal in a time-division manner. The modulation circuit is configured to modulate the input signal into a digital signal. The demultiplexer has a first output terminal and a second output terminal, and is configured to output the digital signal by selecting the first output terminal or the second output terminal in a time-division manner.

Description

Technical Field

[0001] This invention relates to a trigonometric integral modulator, and more particularly to a trigonometric integral modulator capable of processing analog signals of different electrical forms. Background Technology

[0002] Sigma-integral modulators (or integral-triangular modulators) are commonly used to achieve high-resolution analog-to-digital conversion, but currently there is no single Sigma-integral modulator that can handle analog signals of different electrical forms, such as DC and AC signals. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a trigonometric integral modulator that can process analog signals of different electrical forms.

[0004] To achieve the above objectives, embodiments of the present invention provide a trigonometric integral modulator, including a multiplexer, a modulation circuit, and a demultiplexer. The multiplexer receives a first analog signal and a second analog signal, and outputs an input signal. The first analog signal and the second analog signal are of different electrical forms, and the multiplexer selects either the first analog signal or the second analog signal as the input signal in a time-division multiplexing manner for output. The modulation circuit is coupled to the multiplexer and modulates the input signal into a digital signal. The demultiplexer is coupled to the modulation circuit and has a first output terminal and a second output terminal, used to receive the digital signal and select either the first output terminal or the second output terminal in a time-division multiplexing manner to output the digital signal.

[0005] To further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0006] Figure 1 This is a functional block diagram of the triangular integral modulator according to an embodiment of the present invention.

[0007] Figure 2 This is a circuit diagram of the continuous-time integrator according to the first embodiment of the present invention.

[0008] Figure 3 This is a circuit diagram of a continuous-time integrator according to a second embodiment of the present invention.

[0009] Figure 4 This is a circuit diagram of a continuous-time integrator according to the third embodiment of the present invention.

[0010] Figure 5 This is a circuit diagram of the discrete-time integrator according to the first embodiment of the present invention.

[0011] Figure 6 This is a circuit diagram of the discrete-time integrator according to the second embodiment of the present invention.

[0012] Symbol Explanation

[0013] 1: Trigonometric Integral Modulator

[0014] 10: Multiplexer

[0015] 12: Modulation circuit

[0016] 122: Arithmetic Unit

[0017] 124: Loop Filter

[0018] 126: Quantizer

[0019] 128: Digital-to-Analog Converter

[0020] 14: Demultiplexer

[0021] 16: Decimation Filter

[0022] 18: Counter

[0023] A1: First analog signal

[0024] A2: Second analog signal

[0025] SIN: Input signal

[0026] D: Digital signal

[0027] O1: First output terminal

[0028] O2: Second output terminal

[0029] D1: First output signal

[0030] D2: Second output signal

[0031] AF: Analog feedback signal

[0032] E: Difference signal

[0033] F: Filtered signal

[0034] RST: Reset signal

[0035] 1242: Continuous-time integrator

[0036] 1244: Discrete-time integrator

[0037] 201,501: Differential Amplifier

[0038] R21, R22: Resistors

[0039] C21~C22, C51~C54: Capacitors

[0040] S21~S22, S31, S41~S44, S51~S59, S61~S64: Switches

[0041] P31~P32, P41~P42, P51~P56, P61~P62: Nodes

[0042] GND: Grounding voltage Detailed Implementation

[0043] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content provided in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the content provided is not intended to limit the scope of protection of the present invention.

[0044] Please see Figure 1 , Figure 1 This is a functional block diagram of a triangular integral modulator according to an embodiment of the present invention. Figure 1 As shown, the trigonometric integral modulator 1 includes a multiplexer 10, a modulation circuit 12, and a demultiplexer 14. The multiplexer 10 receives a first analog signal A1 and a second analog signal A2, and outputs an input signal SIN. The first analog signal A1 and the second analog signal A2 are of different electrical forms, and the multiplexer 10 selects either the first analog signal A1 or the second analog signal A2 as the input signal SIN in a time-division multiplexing manner. In other words, the signal processing time of the trigonometric integral modulator 1 can be divided into multiple time periods, and the multiplexer 10 selects either the first analog signal A1 or the second analog signal A2 as the input signal SIN in each time period. However, this invention does not limit the length of these time periods to be the same, nor does it limit the specific implementation of the multiplexer 10 selecting the first analog signal A1 or the second analog signal A2 as the input signal SIN, as long as the multiplexer 10 can alternately select the first analog signal A1 and the second analog signal A2 as the input signal SIN for output.

[0045] Modulation circuit 12 is coupled to multiplexer 10 and is used to modulate the input signal SIN into a digital signal D. Details regarding modulation circuit 12 will be explained in other paragraphs, and will not be elaborated upon here. It is important to understand that regardless of whether the input signal SIN is the first analog signal A1 or the second analog signal A2, modulation circuit 12 can modulate it to generate the corresponding digital signal D. Furthermore, demultiplexer 14 is coupled to modulation circuit 12 and has a first output terminal O1 and a second output terminal O2, used to receive the digital signal D and to select either the first output terminal O1 or the second output terminal O2 to output the digital signal D in a time-division multiplexing manner. This invention does not limit the specific implementation of the demultiplexer 14 in selecting the first output terminal O1 or the second output terminal O2 to output the digital signal D. As long as the modulation circuit 12 modulates the first analog signal A1, which is the input signal SIN, to output the corresponding digital signal D, the demultiplexer 14 selects the first output terminal O1 to output the digital signal D, and the modulation circuit 12 modulates the second analog signal A2, which is the input signal SIN, to output the corresponding digital signal D, the demultiplexer 14 selects the second output terminal O2 to output the digital signal D.

[0046] Specifically, the modulation circuit 12 includes an arithmetic unit 122, a loop filter 124, a quantizer 126, and a digital-to-analog converter 128. The arithmetic unit 122 receives the input signal SIN and the analog feedback signal AF, and calculates the difference between them to output a difference signal E. The loop filter 124 is coupled to the arithmetic unit 122 and processes the difference signal E to generate a filtered signal F. For example, if the input signal SIN and the analog feedback signal AF are DC voltages of 0.2 volts and 1 volt respectively, the difference signal E is 0.2 volts minus 1 volt (i.e., -0.8 volts) of DC voltage, and this difference signal E is further processed by the loop filter 124 into the filtered signal F. Details regarding the loop filter 124 will be explained in other paragraphs, and will not be elaborated upon here.

[0047] Quantizer 126 is coupled to loop filter 124 and is used to quantize the filtered signal F into a digital signal D. Quantization refers to the process of approximating the continuous values ​​of the filtered signal F into multiple discrete values. Quantizer 126 can be implemented using a multi-order comparator, but this invention does not limit the specific implementation of quantizer 126. Additionally, digital-to-analog converter 128 is coupled to quantizer 126 and arithmetic unit 122 and is used to perform digital-to-analog conversion on the digital signal D to generate an analog feedback signal AF. Since the operating principle of digital-to-analog converter 128 is well known to those skilled in the art, its details will not be elaborated here. It should be noted that the first analog signal A1 can be a DC signal, and the second analog signal A2 can be an AC signal. For example, the DC signal can be the DC voltage output by a temperature sensor, gravity sensor, or triaxial sensor, and the AC signal can be an audio signal output by a microphone or audio device, but this invention is not limited thereto. In other embodiments, the first analog signal A1 can also be an analog signal close to a DC voltage (nearly DC signal), but this invention is not limited thereto.

[0048] However, because the DC signal (i.e., the first analog signal A1) is too small, it can cause periodic tone. Therefore, the loop filter 124 of the modulation circuit 12 can also avoid periodic tone by using a periodic reset mechanism. In other words, when the modulation circuit 12 modulates the first analog signal A1 as the input signal SIN, the loop filter 124 is reset according to a reset signal RST. For example, when a high-level reset signal RST is received, the loop filter 124 is reset, but the present invention does not limit the specific implementation of generating the reset signal RST. Conceptually, trigonometric integral modulation is an oversampling technique that can reduce noise in the operating frequency band. Therefore, in this embodiment, the oversampling rate can also be used as the period of the reset signal RST from low level to high level.

[0049] Furthermore, in order to convert the digital signal D after modulating the AC signal (i.e., the second analog signal A2) into a higher resolution digital signal, the trigonometric integral modulator 1 may also include a decimation filter 16. The decimation filter 16 is coupled to the second output terminal O2 of the demultiplexer 14 and is used to decimate the digital signal D output from the second output terminal O2 to generate a second output signal D2. The decimation filter is used to reduce the signal sampling frequency and achieve low-pass filtering. In addition, the decimation filter 16 in this embodiment can not only reduce the sampling frequency of the digital signal D output from the second output terminal O2, but also filter out high-frequency noise to generate a higher resolution second output signal D2.

[0050] On the other hand, besides the decimation filter 16, the simplest decimation structure conceptually is a counter. Therefore, in order to convert the digital signal D after modulating the DC signal (i.e., the first analog signal A1) into a higher resolution digital signal, the trigonometric modulator 1 may also include a counter 18. The counter 18 is coupled to the first output terminal O1 of the demultiplexer 14 and is used to count the digital signal D output from the first output terminal O1 to generate a first output signal D1. Similarly, the counter 18 can also avoid periodic tones by using a periodic reset mechanism. For example, the counter 18 can be reset to zero at the beginning of each predetermined period according to the reset signal RST and the number of pulses occurring within the predetermined period can be added. Since the operating principle of the counter 18 is well known to those skilled in the art, its details will not be elaborated here.

[0051] Furthermore, the loop filter 124 may include at least a continuous-time integrator 1242 or a discrete-time integrator 1244 for integrating the difference signal E, and the filtered signal F is generated based on the integration result output by the continuous-time integrator 1242 or the discrete-time integrator 1244. Since the operating principle of generating the filtered signal F based on the integration result of the integrator is well known to those skilled in the art, its details will not be elaborated here. The following is through... Figures 2 to 6 This will illustrate various implementations of the continuous-time integrator 1242 or the discrete-time integrator 1244.

[0052] Please see Figure 2 , Figure 2 This is a circuit diagram of a continuous-time integrator according to a first embodiment of the present invention. In the first embodiment, the continuous-time integrator 1242 may include a differential amplifier 201, resistors R21 and R22, capacitor C21, and capacitor C22. Resistor R21 is coupled to the arithmetic unit 122. Figure 2 The continuous-time integrator 1242 is connected between the inverting input terminal of the differential amplifier 201 (not shown) and the non-inverting input terminal of the differential amplifier 201, and resistor R22 is coupled between the operational unit 122 and the non-inverting input terminal of the differential amplifier 201. Additionally, capacitor C21 is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier 201, and capacitor C22 is coupled between the non-inverting input terminal and the inverting output terminal of the differential amplifier 201. Therefore, the continuous-time integrator 1242 can be used to integrate the difference signal E output by the operational unit 122. However, since the operating principles of the differential amplifier 201, resistors R21 and R22, capacitors C21 and C22 are well known to those skilled in the art, the details of the integration of the difference signal E by the continuous-time integrator 1242 will not be elaborated further.

[0053] As previously mentioned, the loop filter 124 is further reset according to the reset signal RST to avoid idle tone in the DC signal. Therefore, the continuous-time integrator 1242 of the first embodiment may also include a reset switch S21 and a reset switch S22. The reset switch S21 is connected in parallel with the capacitor C21 between the inverting input and the non-inverting output of the differential amplifier 201, and the reset switch S22 is connected in parallel with the capacitor C22 between the non-inverting input and the inverting output of the differential amplifier 201. In addition, the reset signal RST is used to control the reset switches S21 and S22. For example, when a high-level reset signal RST is received, the reset switches S21 and S22 are turned on to reset the loop filter 124 to restore it to its initial state.

[0054] Please see Figure 3 , Figure 3 This is a circuit diagram of a continuous-time integrator according to a second embodiment of the present invention. Since the continuous-time integrator 1242 of the second embodiment is similar to that of the continuous-time integrator 1242 of the first embodiment, the similarities between the two embodiments will not be described again. It should be noted that, unlike the reset switches S21 and S22 of the first embodiment, the continuous-time integrator 1242 of the second embodiment includes a reset switch S31. For example... Figure 3 As shown, the first terminal of capacitor C21 is coupled to the non-inverting output terminal of differential amplifier 201 through node P31, and the first terminal of capacitor C22 is coupled to the inverting output terminal of differential amplifier 201 through node P32. Additionally, reset switch S31 is coupled between nodes P31 and P32, and the reset signal RST is used to control reset switch S31. For example, when a high-level reset signal RST is received, reset switch S31 is turned on to reset loop filter 124.

[0055] Please see Figure 4 , Figure 4 This is a circuit diagram of a continuous-time integrator according to a third embodiment of the present invention. Since the continuous-time integrator 1242 of the third embodiment is similar to that of the continuous-time integrator 1242 of the second embodiment, the similarities between the two embodiments will not be described again. It should be noted that, unlike the reset switch S31 of the second embodiment, the continuous-time integrator 1242 of the third embodiment includes a setting switch S41, a reset switch S42, a setting switch S43, and a reset switch S44. The setting switch S41 is coupled between node P31 and node P41, and the inverted reset signal RST*( Figure 4(Not shown) is used to control the setting switch S41. The reset switch S42 is coupled between node P31 and node P42, and the reset signal RST is used to control the reset switch S42. Conversely, the setting switch S43 is coupled between node P32 and node P42, and the inverted reset signal RST* is used to control the setting switch S43. The reset switch S44 is coupled between node P32 and node P41, and the reset signal RST is used to control the reset switch S44. Operationally, when the loop filter 124 is not reset, setting switches S41 and S43 are turned on; therefore, setting switch S41 is controlled to couple node P41 to node P31, and setting switch S43 is controlled to couple node P42 to node P32. When the loop filter 124 is reset, reset switch S42 and reset switch S44 are turned on. Therefore, reset switch S42 is controlled to couple node P42 to node P31, and reset switch S44 is controlled to couple node P41 to node P32.

[0056] On the other hand, please see Figure 5 , Figure 5 This is a circuit diagram of a discrete-time integrator according to a first embodiment of the present invention. In the first embodiment, the discrete-time integrator 1244 may include a differential amplifier 501, capacitors C51 to C54, and switches S51 to S58. Capacitor C51 is coupled to the arithmetic unit 122 (…). Figure 5 (Not shown) and the inverting input terminal of differential amplifier 501, and capacitor C52 is coupled between operational unit 122 and the non-inverting input terminal of differential amplifier 501. In addition, capacitor C53 is coupled between the inverting input terminal and the non-inverting output terminal of differential amplifier 501, and capacitor C54 is coupled between the non-inverting input terminal and the inverting output terminal of differential amplifier 501.

[0057] Switch S51 is coupled between capacitor C51 and operational unit 122, and switch S52 is coupled between capacitor C52 and operational unit 122. Additionally, switch S53 is coupled between capacitor C51 and the inverting input of differential amplifier 501, and switch S54 is coupled between capacitor C52 and the non-inverting input of differential amplifier 501. Switch S55 is coupled between ground voltage GND and relay node P51, and relay node P51 is between capacitor C51 and switch S53. Switch S56 is coupled between ground voltage GND and relay node P52, and relay node P52 is between capacitor C52 and switch S54. Furthermore, switch S57 is coupled between ground voltage GND and relay node P53, and relay node P53 is between switch S51 and capacitor C51. Switch S58 is coupled between ground voltage GND and relay node P54, and relay node P54 is between switch S52 and capacitor C52. Operationally, switches S51, S55, S52, and S56 are turned on at the first time, and switches S53, S57, S54, and S58 are turned on at a second time, different from the first time. Since the operating principles of differential amplifier 501, capacitors C51 to C54, and switches S51 to S58 are well known to those skilled in the art, the details of the discrete-time integrator 1244 integrating the differential signal E will not be elaborated further.

[0058] As previously mentioned, the loop filter 124 is further reset according to the reset signal RST to avoid periodic tones in the DC signal. Therefore, the discrete-time integrator 1244 of the first embodiment may also include a reset switch S59. Figure 5 As shown, the first terminal of capacitor C53 is coupled to the non-inverting output terminal of differential amplifier 501 via node P55, and the first terminal of capacitor C54 is coupled to the inverting output terminal of differential amplifier 501 via node P56. Additionally, reset switch S59 is coupled between nodes P55 and P56, and the reset signal RST controls reset switch S59. For example, when a high-level reset signal RST is received, reset switch S59 is turned on to reset loop filter 124.

[0059] Please see Figure 6 , Figure 6This is a circuit diagram of a discrete-time integrator according to a second embodiment of the present invention. Since the discrete-time integrator 1244 of the second embodiment is similar to that of the discrete-time integrator 1244 of the first embodiment, the similarities between the two embodiments will not be described again. It should be noted that, unlike the reset switch S59 of the first embodiment, the discrete-time integrator 1244 of the second embodiment includes a setting switch S61, a reset switch S62, a setting switch S63, and a reset switch S64. The setting switch S61 is coupled between node P55 and node P61, and the inverted reset signal RST*( Figure 6 (Not shown) is used to control the setting switch S61. The reset switch S62 is coupled between node P55 and node P62, and the reset signal RST is used to control the reset switch S62. Conversely, the setting switch S63 is coupled between node P56 and node P62, and the inverted reset signal RST* is used to control the setting switch S63. The reset switch S64 is coupled between node P56 and node P61, and the reset signal RST is used to control the reset switch S64. Operationally, when the loop filter 124 is not reset, setting switches S61 and S63 are turned on; therefore, setting switch S61 is controlled to couple node P61 to node P55, and setting switch S63 is controlled to couple node P62 to node P56. When the loop filter 124 is reset, reset switches S62 and S64 are turned on. Therefore, reset switch S62 is controlled to couple node P62 to node P55, and reset switch S64 is controlled to couple node P61 to node P56.

[0060] In summary, one of the beneficial effects of this invention is that the trigonometric integral modulator provided by this invention can process analog signals of different electrical forms through a multiplexer, a modulation circuit, and a demultiplexer. Furthermore, the loop filter of the modulation circuit can avoid periodic tones by using a periodic reset mechanism.

[0061] The above-described content is merely a preferred embodiment of the present invention and is not intended to limit the scope of the claims of the present invention. Therefore, any equivalent technical changes made based on the description and drawings of the present invention are included within the scope of the claims of the present invention.

Claims

1. A trigonometric integral modulator, comprising: A multiplexer is used to receive a first analog signal and a second analog signal, and output an input signal, wherein the first analog signal and the second analog signal are of different electrical forms, and the multiplexer selects the first analog signal or the second analog signal as the input signal for output in a time-division manner; A modulation circuit, coupled to the multiplexer, is used to modulate the input signal into a digital signal; as well as A demultiplexer, coupled to the modulation circuit, has a first output terminal and a second output terminal for receiving the digital signal and for selecting the first output terminal or the second output terminal to output the digital signal in the time-division manner. In response to the input signal being a DC signal, the loop filter of the modulation circuit is reset according to the high-level reset signal, and the oversampling rate is used as the period during which the reset signal changes from the low level to the high level.

2. The trigonometric integrator as claimed in claim 1, wherein the modulation circuit comprises: An arithmetic unit is configured to receive the input signal and an analog feedback signal, and calculate the difference between the input signal and the analog feedback signal to output a difference signal. The loop filter is coupled to the arithmetic unit and is used to process the difference signal to generate a filtered signal; A quantizer, coupled to the loop filter, is used to quantize the filtered signal into the digital signal; as well as A digital-to-analog converter, coupled to the quantizer and the arithmetic unit, is used to perform digital-to-analog conversion on the digital signal to generate the analog feedback signal.

3. The trigonometric integrator as claimed in claim 2, wherein the first analog signal is the DC signal and the second analog signal is an AC signal.

4. The trigonometric integral modulator as described in claim 1, further comprising: A counter, coupled to the first output terminal of the demultiplexer, is used to count the digital signal output from the first output terminal to generate a first output signal; as well as A decimation filter, coupled to the second output terminal of the demultiplexer, is used to decimate the digital signal output from the second output terminal to generate a second output signal.

5. The trigonometric integral modulator as claimed in claim 2, wherein the loop filter includes at least a continuous-time integrator or a discrete-time integrator for integrating the difference signal, and the filtered signal is generated based on the integration result output by the continuous-time integrator or the discrete-time integrator.

6. The triangular integral modulator of claim 5, wherein the continuous-time integrator comprises: A differential amplifier; A first resistor is coupled between the operational unit and an inverting input terminal of the differential amplifier; A second resistor is coupled between the operational unit and a non-inverting input terminal of the differential amplifier; A first capacitor is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier; and A second capacitor is coupled between the non-inverting input terminal and the inverting output terminal of the differential amplifier.

7. The triangular integral modulator of claim 6, wherein the continuous-time integrator further comprises: A first reset switch is connected in parallel with the first capacitor between the inverting input terminal and the non-inverting output terminal of the differential amplifier; as well as A second reset switch is connected in parallel with the second capacitor between the non-inverting input terminal and the inverting output terminal of the differential amplifier; The reset signal is used to control the first reset switch and the second reset switch.

8. The triangular integral modulator of claim 6, wherein the continuous-time integrator further comprises: A first reset switch is coupled between a first node and a second node, and the reset signal is used to control the first reset switch. A first terminal of the first capacitor is coupled to the non-inverting output terminal of the differential amplifier through the first node, and a first terminal of the second capacitor is coupled to the inverting output terminal of the differential amplifier through the second node.

9. The trigonometric integral modulator of claim 5, wherein the discrete-time integrator comprises: A differential amplifier; A first capacitor is coupled between the operational unit and an inverting input terminal of the differential amplifier; A second capacitor is coupled between the operational unit and a non-inverting input terminal of the differential amplifier; A third capacitor is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier; A fourth capacitor is coupled between the non-inverting input terminal and the inverting output terminal of the differential amplifier; A first switch is coupled between the first capacitor and the arithmetic unit; A second switch is coupled between the second capacitor and the arithmetic unit; A third switch is coupled between the first capacitor and the inverting input terminal of the differential amplifier; as well as A fourth switch is coupled between the second capacitor and the non-inverting input terminal of the differential amplifier, wherein the first switch and the second switch are turned on at a first time, and the third switch and the fourth switch are turned on at a second time, different from the first time.

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