A polar code decoding method and decoder based on special nodes

Abstract

This invention discloses a Polar code decoding method and decoder based on special nodes. The S-CASCL decoding algorithm of this invention divides the decoded bit combination into multiple special nodes of Rate-0, Rate-1, Rep, and SPC. It calculates the LLR value corresponding to each special node, adds the LLR value to the PM value to obtain the PM value of the new path after splitting, sorts the PM values ​​of the new paths, updates the paths according to the sorting results, and performs a CRC check on the remaining paths after all nodes have been processed. The path that passes the CRC check is output as the optimal path, and the decoded bits corresponding to this path are the result of the S-CASCL decoding algorithm. The Polar code decoder based on this algorithm reduces decoder resource overhead by designing a semi-parallel structure, adding an address mapping storage module, modifying the storage and calculation method of the LLR value (i.e., separating the sign bit and numerical value processing), and using a special PM sorting circuit. This results in a low-latency, high-performance, and low-resource-overhead decoder that can be truly applied to practical communication systems.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a Polar code decoding method and decoder based on special nodes. Background Technology

[0002] Various interferences and fading phenomena are common in communication systems, leading to numerous bit errors during digital signal transmission. Channel coding is a relatively mature method for reducing the system's bit error rate. Essentially, it adds correlated redundant symbols to the user information symbols, using these correlated symbols to enhance the anti-interference capability of transmitted information and thus improve system reliability. Several high-performance channel codes have emerged, such as Turbo codes and Low Density Parity Check Code (LDPC). Polar codes are a novel coding scheme, first proposed by Arikan in 2009. While Turbo codes and LDPC codes are currently the most widely used and mature coding techniques, their performance is only "close" to, not "reaches," the Shannon limit. Polar codes are currently the only channel coding technique that has been rigorously proven to truly achieve the desired channel capacity, and thus possess significant development potential.

[0003] However, at present, Polar codes are relatively mature, and the decoding algorithms with good decoding performance are a series of improved algorithms based on Successive Cancellation (SC). These are serial decoding algorithms, which usually have a large delay. Therefore, the current research focus is on how to reduce the decoding delay while ensuring excellent decoding performance, and to ensure that this new algorithm can be truly implemented in hardware and applied to actual projects.

[0004] Research on low-latency Polar code decoding algorithms has led some scholars to propose decoding algorithms based on various fast nodes, including Rate-0, Rate-1, SPC, REP, Type-I, Type-II, Type-III, Type-IV, and Type-V, which significantly improve the parallelism of decoding and thus reduce decoding latency. However, the sheer number of node types and their different processing methods, especially in hardware implementation, requires substantial resource overhead to meet the computational demands of all nodes. Currently, most node implementations are still in the algorithm research stage. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned shortcomings in the prior art and provide a Polar code decoder based on special nodes.

[0006] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0007] A Polar code decoding method based on special nodes, characterized by comprising:

[0008] S1. Based on the code structure characteristics of Polar codes, the decoding bit combinations are divided into four types of decoding nodes: Rate-0, Rate-1, Rep, and SPC.

[0009] S2. Calculate the log-likelihood ratio (LLR) of the four decoding nodes: Rate-0, Rate-1, Rep, and SPC.

[0010] S3. The S-CASCL decoding algorithm is used to process Rate-0, Rate-1, Rep and SPC respectively to obtain List of decoding paths;

[0011] S4. Perform CRC check on the decoding paths of the List, select the optimal decoding path for decoding, and output the result;

[0012] The S-CASCL decoding algorithm, based on the code structure characteristics of Polar codes, divides the decoding bit combination into multiple special nodes of Rate-0, Rate-1, Rep, and SPC. During decoding, the LLR value corresponding to the special node is calculated, and the PM value corresponding to the split new path is obtained by adding the LLR value and the PM value. The PM values ​​of the new paths are sorted, and the paths are updated according to the sorting results. The processing order between nodes is serial. After all nodes have completed decoding, a CRC check is performed on the multiple retained paths, and the path that passes the CRC check or has the smallest PM value is output as the optimal path. The corresponding decoding bits on this path are then output as the result.

[0013] Preferably, the processing of the Rate-0 node includes:

[0014] Summing the LLR values ​​less than 0 within the Rate-0 node, adding the summation result to the original PM value, and obtaining the PM value corresponding to the new split path are then written into the PM register; for a path of length N... v The Rate-0 node has no information bits and does not require path splitting. The node's bits are simply set to all zeros, and the PM value of the path is updated accordingly.

[0015]

[0016] In the formula, 1≤l≤List represents the path number, and L v (j)[l] represents the LLR value corresponding to the j-th bit among the bits contained in the node on the l-th path.

[0017] Preferably, the processing method for the Rep node includes:

[0018] Summing the LLR values ​​of the greater than 0 and less than 0 portions within the Rep node, and adding the two sums to the original PM value, yields the PM value corresponding to the new split path; for a path of length N... v The Rep node contains only one information bit. It only needs to split the path once. The two split paths will determine the node bits as all 0 and all 1 respectively. The PM values ​​of all new paths will be sorted, and the List items with smaller PM values ​​will be selected accordingly.

[0019] For the all-zero path, simultaneously update the PM value of the path:

[0020]

[0021] For the all-1 path, simultaneously update the PM value of the path as follows:

[0022]

[0023] In the formula, 1≤l≤List represents the path number, and L v (j) [l] represents the LLR value corresponding to the j-th bit among the bits contained in the node on the l-th path.

[0024] Preferably, all LLR values ​​of the Rate-1 node are sorted by absolute value, and processed bit by bit in ascending order. The processing method includes:

[0025] S201. Assign an initial value to all bits of the node for decision. The decision formula for each bit is as follows:

[0026]

[0027] In the formula, L v (i) [l] represents the LLR corresponding to the i-th bit in the bits contained in the node on the l-th path, 1≤l≤List represents the path number, and the bit result of the decision is denoted as B;

[0028] S202. Process each bit individually, that is, sort all LLR values ​​of the node by absolute value and process them in ascending order:

[0029] Two paths are split: one is the original path that retains the previous bit decision value, and the corresponding PM value of this path remains unchanged; the other is the flipped path that flips the corresponding bit decision value, and the List items with smaller PM values ​​are selected and retained accordingly. The PM value of this path is updated as follows:

[0030]

[0031] In the formula, L v (i) [l] represents the LLR value corresponding to the i-th bit among the bits contained in the node on the l-th path.

[0032] Preferably, the processing method for the SPC node includes:

[0033] S301. Assign an initial value to all bits of the node for the decision, including:

[0034] Determine the initial value of the SPC node:

[0035] The parity check bit, which corresponds to the bit with the smallest LLR value, is calculated using the following formula:

[0036]

[0037] Solve for the parity check result of this SPC node, that is, for the N of the node. v The decision values ​​are XORed using the following formula:

[0038]

[0039] HD v (i) This is called the hard decision value, and its decision formula is:

[0040]

[0041] L v (i) [l] represents the LLR value corresponding to the i-th bit in the bits contained in the node on the l-th path.

[0042] The bit decision value corresponding to the SPC node is obtained as follows:

[0043]

[0044] S302. Process each bit individually. For a flipped path, both the corresponding bit and the parity check bit's decision value need to be flipped simultaneously. PM is updated as follows:

[0045]

[0046] Where j represents the parity bit and i represents the bit currently being processed.

[0047] A Polar code decoder for a special node, characterized in that the decoder comprises: an intermediate LLR layer memory, a channel layer LLR memory, a selection module, a computational core module, a feedback bit memory, a path splitting module, a PM sorting module, a path selection module, a PM memory, a fast node index memory, a CRC check unit, and a decoding result memory.

[0048] The LLR data received from the channel is placed in the channel layer LLR memory. During decoding, the LLR data is sent to the computation core module for processing. Using a traditional unit factor calculation structure, the LLR values ​​corresponding to the four special nodes and other data required for processing by the special nodes are calculated. The data generated during the calculation process is stored in the intermediate LLR memory and read from it when needed. The feedback bit memory stores hard bit decision values. When the computation core works to the decision layer or processes the four special nodes, that is, after all the data required for node decoding is ready, the path splitting module and the P... In the M sorting and path selection module, corresponding processing is performed according to the special node's Rate-0, Rate-1, Rep, and SPC to complete path splitting and path updating operations. After decoding a node, the decision bit value is stored in the decoding result memory. This calculation process is continuously repeated until all nodes have been decoded and decided. Then, in the CRC check unit, a CRC check is performed on the multiple retained paths, and the path that passes the CRC check or has the smallest PM value is output as the optimal path. The corresponding decoding bits on this path are the decoding results of the S-CASCL algorithm.

[0049] Preferably, when the code length is very long, the resource consumption is also very large. The semi-parallel decoder sets an upper limit P on the number of PEs, called the parallelism P. Thus, for certain layers near the channel, multiple clock cycles are required to complete the entire update. In the computational core module, a semi-parallel computing core is used, and an upper limit P is set on the number of computational units PEs in the decoder, with a value of 2p.

[0050] The speed factor reflects the effect of parallelism P. The speed factor is the ratio of the decoding time overhead of the semi-parallel structure to that of the traditional structure, i.e., the speed factor ζ. half-paral The following formula describes the time loss caused by the semi-parallel structure:

[0051]

[0052] In the formula, T FFT and T half-paralThe numbers represent the number of clock cycles required for decoding the traditional FFT decoding structure and the semi-parallel decoding structure, respectively. N is the code length, and P is the set parallelism. It can be seen that even when P is small, there is a speed factor close to 1. This means that even with a very small parallelism, a throughput close to that of an FFT-type SC decoder can be achieved. A small parallelism means a significant reduction in resource overhead and an improvement in resource utilization.

[0053] Resource utilization α of a semi-parallel SC decoder half-paral for:

[0054]

[0055] In the formula, N is the code length and P is the set parallelism.

[0056] Preferably, the mapping matrix memory includes an address mapping storage unit, which uses an address mapping matrix to store the mapping relationship between each physical path and logical path. For a code length of N=2... n The Polar code uses an address mapping matrix memory containing List × (n-1) elements, storing path numbers of [log2List] bits. Different rows correspond to different paths, and different columns correspond to different layers. During decoder operation, the data read from the intermediate LLR memory and feedback bit memory is controlled by this address mapping matrix memory. When path splitting and filtering are required, the path filtering process can be completed simply by copying and modifying the contents of the address mapping matrix memory. This avoids the need for a large List × List × (N-1)Q fully connected circuit, requiring only a List × List × (n-1) [log2List] storage unit, thus reducing the overhead of logic interconnection.

[0057] Preferably, in the core calculation module, the storage and calculation method of LLR is modified. When storing LLR, the form of sign bit + absolute value is used instead of two's complement. L1 to L4 on the unit factor represent the log-likelihood ratio soft information LLR value. By converting the calculation formulas of L3 and L4 in the unit factor, the calculation transfer formula for processing the sign bit and data bit separately can be obtained:

[0058]

[0059] amp(L3)=min(amp(L1),amp(L2))

[0060]

[0061]

[0062] γ = if(amp(L1) > amp(L2)),

[0063] In the formula, `sgn()` represents taking the sign bit of the content within the parentheses, and `amp` represents taking the amplitude value, which is the absolute value. By storing the sign bit separately from the numerical bits, the absolute value operation is eliminated. While this adds a few XOR gates, the resource overhead is reduced. Furthermore, for parts involving absolute value operations, such as special node sorting, this storage method can directly retrieve the absolute value without further conversion.

[0064] Preferably, in the PM sorting module, among the 2 List paths to be sorted, the PM values ​​of the List paths already exist and have been sorted during the decoding of the previous bit or node. The remaining PM values ​​are obtained by adding a positive number to the known List paths. The positive number is the absolute value of the soft information value of the current decoded bit. Therefore, using the known List, the PM sorting task can be represented as:

[0065] Given an ordered sequence of length List: μ0 ≤ μ1 ≤ μ List-1 A new sequence m = [m0, m1, ..., mn] of length 2List. 2List-1 Constructed by the following formula, where l = 0, ..., List-1, and α l ≥0.

[0066] m l =μ l m List+l =μ l +α l

[0067] It can be seen that sequence m has the following properties:

[0068] m l ≤m List+l m l ≤m l+1

[0069] Therefore, we can know any two m l There's no need to compare elements within an (l×List) because the order is known, and the last element m... 2List-1 It doesn't need to be compared with other elements; it's definitely not in the smallest list path and will be discarded.

[0070] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0071] 1. A Polar code decoding method based on special nodes. This invention introduces four special node S-CASCL decoding algorithms: Rate-0, Rate-1, Rep, and SPC. By merging Polar code bits, the decoding process avoids having to run the operation on each bit to the decision layer, thus avoiding redundant calculations for decoding frozen bits, reducing computational load, and achieving the goal of reducing latency and increasing throughput. Furthermore, compared to the current best-performing Polar decoding algorithm CASCL, this improved algorithm does not incur significant performance loss while reducing decoding latency.

[0072] 2. A Polar code decoder based on special nodes. The hardware implementation of the Polar code decoder based on the S-CASCL decoding algorithm has several special designs, including a parallel half-row structure, an added address mapping storage module, a modified storage and operation method for LLR values ​​to separate the sign bit and the numerical value, and a special PM sorting circuit, which reduces the decoder's resource consumption.

[0073] 3. It has been proven that a low-latency, high-performance, and low-resource-overhead decoder can be truly applied to practical communication systems. Attached Figure Description

[0074] Figure 1 This embodiment presents a Polar decoding method based on special nodes.

[0075] Figure 2 This is a tree-structured SC decoding diagram with N=8 in this embodiment;

[0076] Figure 3 It is the pruned tree-like SC decoding structure;

[0077] Figure 4 This is a flowchart of the special node Rate1 and SPC processing in this embodiment 1;

[0078] Figure 5 This is the overall hardware implementation architecture of the S-CASCL decoder in Embodiment 2.

[0079] Figure 6 This is a schematic diagram illustrating the relationship between the velocity factor and the number of PEs in Example 2 of this embodiment;

[0080] Figure 7 This is the structure of the address mapping matrix memory in Embodiment 2;

[0081] Figure 8 This is the implementation structure of the unit factor when storing data in two's complement form in this embodiment 2;

[0082] Figure 9This is the electrical structure for implementing the unit factor when the sign bit data value is stored separately in Embodiment 2;

[0083] Figure 10 This is the scoring and sorting circuit after pruning in Embodiment 2;

[0084] Figure 11 This is the state transition diagram of the state machine in Embodiment 2;

[0085] Figure 12 This is the hardware simulation platform for testing the bit error rate in Example 4 of this embodiment;

[0086] Figure 13 This is the hardware simulation result in Example 4 of this embodiment;

[0087] Figure 14 This is the hardware simulation performance curve in Example 4 of this embodiment;

[0088] Figure 15 This is the hardware board-based test simulation platform in embodiment 4;

[0089] Figure 16 This refers to the capture of measured data from the upper board in Example 4 of this embodiment;

[0090] Figure 17 This is the SC decoding diagram for N=8 in Example 4 of this embodiment;

[0091] Figure 18 This is the unit factor graph in the SC decoding structure of this embodiment 4.

[0092] The diagram is labeled as follows: 21-Rate-0, 22-Rate-1, 23-Rep, 24-SPC, 51-Intermediate LLR layer memory, 52-Channel layer LLR memory, 53-Selection module, 54-Computation core module, 55-Feedback bit memory, 56-Path splitting module, 57-PM sorting module, 58-Path selection module, 59-PM memory, 510-Fast node index memory, 511-CRC check unit, 512-Decoding result memory, 513-Mapping matrix memory, 514-State machine. Detailed Implementation

[0093] The present invention will be further described in detail below with reference to experimental examples and specific embodiments. However, this should not be construed as limiting the scope of the above-mentioned subject matter of the present invention to the following embodiments; all technologies implemented based on the content of the present invention fall within the scope of the present invention.

[0094] The S-CASCL decoding algorithm, based on the code structure characteristics of Polar codes, divides the decoding bit combination into multiple special nodes of Rate-021, Rate-122, Rep23, and SPC24. During decoding, the LLR value corresponding to the special node is calculated, and the PM value corresponding to the split new path is obtained by adding the LLR value and the PM value. The PM values ​​of the new path are sorted, and the path is updated according to the sorting result. The processing order between nodes is serial. After all nodes have completed decoding, a CRC check is performed on the multiple retained paths. The path that passes the CRC check or has the smallest PM value is output as the optimal path, along with the corresponding decoding bits on that path, and the result is output.

[0095] Example 1

[0096] like Figure 1 As shown, a Polar code decoding method based on special nodes has the following steps:

[0097] S1, such as Figure 2 As shown, based on the code structure characteristics of Polar codes, the decoding bit combinations are divided into four types of decoding nodes: Rate-021, Rate-122, Rep23, and SPC24.

[0098] Rate-021: Nodes where all leaf nodes are frozen;

[0099] Rep23: Except for the last leaf node which is an information bit, all other leaf nodes are frozen bits.

[0100] Rate-122: Nodes where all leaf nodes are information bits;

[0101] SPC24: Except for the first leaf node which is a frozen bit, all other leaf nodes are information bits.

[0102] Fast nodes have their own decoding method. Fast nodes are used to prune the decoding tree, such as... Figure 3 As shown, only the λ=2 layer needs to be processed, avoiding many unnecessary calculations and thus reducing latency.

[0103] S2. Calculate the log-likelihood ratio (LLR) values ​​of the four decoding nodes, namely Rate-021, Rate-122, Rep23, and SPC24;

[0104] The LLR value corresponding to a specific node is calculated using a traditional unit factor calculation structure.

[0105] S3. The S-CASCL decoding algorithm is used to process Rate-021, Rate-122, Rep23 and SPC24 respectively to obtain the List of decoding paths;

[0106] The processing of the Rate-021 node includes:

[0107] Summing the LLR values ​​less than 0 within the Rate-021 node, adding the summation result to the original PM value, and obtaining the PM value corresponding to the new split path, which is then written into the PM register; for a path of length N... v The Rate-021 node has no information bits and does not need to split the path. The node's bits are simply set to all zeros, and the PM value of the path is updated accordingly.

[0108]

[0109] In the formula, 1≤l≤List represents the path number, and L v (j) This represents the LLR value corresponding to the j-th bit in the node.

[0110] The processing method for the Rep23 node includes:

[0111] Summing the LLR values ​​of the portions greater than 0 and less than 0 within the Rep23 node, and adding the two sums to the original PM value, yields the PM value corresponding to the new split path; for a path of length N... v The Rep23 node contains only one information bit. It only needs to split the path once. The two split paths will determine the node bits as all 0 and all 1 respectively. The PM values ​​of all new paths will be sorted, and the List items with smaller PM values ​​will be selected accordingly.

[0112] For the all-zero path, simultaneously update the PM value of the path:

[0113]

[0114] For the all-1 path, simultaneously update the PM value of the path as follows:

[0115]

[0116] In the formula, 1≤l≤List represents the path number, and L v (j) This represents the LLR value corresponding to the j-th bit in the node.

[0117] like Figure 4As shown, all LLR values ​​of the Rate-122 node are sorted by absolute value, and processed bit by bit in ascending order. The processing method includes:

[0118] S201. Assign an initial value to all bits of the node for decision. The decision formula for each bit is as follows:

[0119]

[0120] Among them, L v (i) [l] represents the LLR value corresponding to the i-th bit in the bits contained in the node on the l-th path, 1≤l≤List represents the path number, and the bit result of the decision is denoted as B;

[0121] S202. Process each bit individually, that is, sort all LLR values ​​of the node by absolute value and process them in ascending order:

[0122] Two paths are split: one is the original path that retains the previous bit decision value, and the corresponding PM value of this path remains unchanged; the other is the flipped path that flips the corresponding bit decision value, and the List items with smaller PM values ​​are selected and retained accordingly. The PM value of this path is updated as follows:

[0123]

[0124] In the formula, 1≤l≤List represents the path number, and L v (i) [l] represents the LLR value corresponding to the i-th bit among the bits contained in the node on the l-th path.

[0125] like Figure 7 As shown, the processing method for the SPC24 node includes:

[0126] S301. All bits of the SPC24 node are assigned an initial value, including:

[0127] Determine the initial values ​​of the SPC24 nodes:

[0128] The parity check bit, which corresponds to the bit with the smallest LLR value, is calculated using the following formula:

[0129]

[0130] Solve for the parity check result of this SPC24 node, that is, for the N of the node v The decision values ​​are XORed using the following formula:

[0131]

[0132] HDv (i) This is called the hard decision value, and its decision formula is:

[0133]

[0134] In the formula, L v (i) [l] represents the LLR value corresponding to the i-th bit in the bits contained in the node on the l-th path.

[0135] The bit decision value corresponding to the SPC24 node is obtained as follows:

[0136]

[0137] S302. Process each bit individually. For a flipped path, both the corresponding bit and the parity check bit's decision value need to be flipped simultaneously. PM is updated as follows:

[0138]

[0139] Where j represents the parity bit and i represents the bit currently being processed.

[0140] S4. Perform CRC check on the decoding paths of the List, select the optimal decoding path for decoding, and output the result;

[0141] After all nodes have completed the decoding and decision, a CRC check is performed on the multiple retained paths in the CRC check unit 511. The path that passes the CRC check or has the smallest PM value is output as the optimal path. The corresponding decoded bits on this path are the decoding results of the S-CASCL algorithm.

[0142] Example 2

[0143] like Figure 5 As shown, a Polar code decoder for a special node is described. The decoder 5 includes: an intermediate LLR layer memory 51, a channel layer LLR memory 52, a selection module 53, a calculation core module 54, a feedback bit memory 55, a path splitting module 56, a PM sorting module 57, a path selection module 58, a PM memory 59, a fast node index memory 510, a CRC check unit 511, a decoding result memory 512, and a mapping matrix memory 513.

[0144] The channel layer LLR memory 52 is used to store LLR data received from the channel; during decoding, the intermediate LLR memory is used to store data generated during the operation of the computation core module 54; the computation core module 54 is used to implement unit factor data transmission and computation preprocessing of four fast nodes; the feedback bit memory 55 is used to store 0 / 1 bit decision values; the path splitting module 56 is used to split the decoding path; the PM sorting module 57 is used to sort the 2List of PM values ​​after path splitting; the path selection module 58 is used to select the decoding path; the decoding result memory 512 is used to store the decision bit value; and the CRC check unit 511 is used for path result verification.

[0145] The data path describes the overall data flow direction during the decoder's operation. First, the LLR data received from the channel is placed in the channel layer LLR memory 52. ​​Then, decoding begins, and this data is sent to the computation core for processing. That is, using the traditional unit factor calculation structure, the LLR value corresponding to the special node is calculated, as well as the data required for processing other special nodes. The data generated in this calculation process is stored in the intermediate LLR memory and read from it when needed. When the computation core works to the decision layer or processes the four types of special nodes, that is, after all the data required for node decoding is prepared, the path splitting, PM sorting and path selection module 58 completes the path splitting and path updating operations according to the corresponding processing rules of the special nodes. The hard bit decision value is stored in the feedback bit memory 55. After the decoding of a node is completed, the decision bit value is stored in the decoding result memory 512. This calculation process is continuously looped until all nodes have been decoded and decided. Then, the CRC check unit 511 performs a CRC check on the multiple reserved paths and outputs the path that passes the CRC check or has the smallest PM value as the optimal path. The corresponding decoding bits on this path are the decoding results of the S-CASCL algorithm.

[0146] When the code length is very long, the resource consumption is also very large. The semi-parallel decoder sets an upper limit P on the number of PEs (Programmers), called the parallelism P. This means that for certain layers close to the channel, multiple clock cycles are needed to complete the entire update. In the computational core module 54, a semi-parallel processing core is used, setting an upper limit P on the number of computational units (PEs) in the decoder, with a value of 2. p .

[0147] like Figure 6 As shown, the effect of parallelism P is reflected by the speed factor. The speed factor is the ratio of the decoding time overhead of the semi-parallel structure to that of the traditional structure, i.e., the speed factor ζ. half-paral The following formula describes the time loss caused by the semi-parallel structure:

[0148]

[0149] In the formula, T FFT and T half-paral The numbers represent the number of clock cycles required for decoding the traditional FFT decoding structure and the semi-parallel decoding structure, respectively. N is the code length, and P is the set parallelism. It can be seen that even when P is small, there is a speed factor close to 1. This means that even with a very small parallelism, a throughput close to that of an FFT-type SC decoder can be achieved. A small parallelism means a significant reduction in resource overhead and an improvement in resource utilization.

[0150] Resource utilization α of a semi-parallel SC decoder half-paral for:

[0151]

[0152] Where N is the code length and P is the set parallelism. For example, for a Polar code with N=1024 and P=64, the decoding delay of the semi-parallel decoder is only 34 clock cycles longer than that of the linear decoder, but the resource utilization is improved by nearly 8 times.

[0153] The mapping matrix memory 513 includes an address mapping memory unit, such as... Figure 7 As shown, an address mapping matrix is ​​used to store the mapping relationship between each physical path and logical path. For a code length of N=2... n The Polar code is represented by an address mapping matrix memory 513 containing List×(n-1) elements, storing path numbers of [log2List] bits. Different rows correspond to different paths, and different columns correspond to different layers. During decoder operation, the data read from the intermediate LLR memory and feedback bit memory 55 is controlled by this address mapping matrix memory 513. When path splitting and filtering are required, the path filtering process can be completed simply by copying and modifying the contents of the address mapping matrix memory 513. This avoids the need for a large List×List×(N-1)Q fully connected circuit, requiring only the addition of List×List×(n-1)[log2List] storage units, thus reducing the overhead of logic wiring interconnection.

[0154] In the core computation module 54, the storage and operation method of LLR are modified. When storing LLR, the form of sign bit + absolute value is used instead of two's complement. Taking N=8 as an example, the decoding structure of the SC algorithm is as follows: Figure 17 As shown, it consists of multiple Figure 18 The unit factors shown represent the log-likelihood ratio (LLR) soft information values ​​(L1-L4). By converting the calculation formulas for L3 and L4 in the unit factors, we can obtain the calculation transfer formulas that process the sign bit and data bit separately:

[0155]

[0156] amp(L3)=min(amp(L1),amp(L2))

[0157]

[0158]

[0159] γ = if(amp(L1) > amp(L2)),

[0160] In the formula, sgn() means taking the sign bit of the content in parentheses, and amp means taking the amplitude value, which is the absolute value.

[0161] like Figure 8 and 9 The diagram shows PE calculation circuits using two's complement and separate sign and value storage, respectively. The method of storing the sign and value separately eliminates the absolute value operation, adds several XOR gates, resulting in lower resource overhead. Furthermore, for parts involving absolute value operations, such as special node sorting, this storage method can directly retrieve the absolute value without further conversion. Figure 8 In this context, MSB represents the most significant bit.

[0162] In the PM sorting module 57, among the 2 List paths that need to be sorted, the PM values ​​of the List paths already exist and have been sorted during the decoding of the previous bit or node. The remaining PM values ​​are obtained by adding a positive number to the known List paths. The positive number is the absolute value of the soft information value of the current decoded bit. Therefore, using the known List, the PM sorting task can be represented as:

[0163] Given an ordered sequence of length List: μ0 ≤ μ1 ≤ μ List-1 A new sequence m = [m0, m1, ..., mn] of length 2List. 2List-1 Constructed by the following formula, where l = 0, ..., List-1, and α l ≥0.

[0164] m l =μ l m List+l =μ l +α l

[0165] It can be seen that sequence m has the following properties:

[0166] m l ≤m List+l m l≤m l+1

[0167] Therefore, we can know any two m l There's no need to compare elements within an (l×List) because the order is known, and the last element m... 2List-1 It doesn't need to be compared with other elements; it's definitely not in the smallest list path and will be discarded.

[0168] like Figure 10 As shown, based on the above properties, the scoring and sorting circuit is pruned. After pruning, the number of comparators required to sort a sequence of length n is (n / 2-1). 2 .

[0169] Finally, the control module is responsible for the normal scheduling of each module. The entire decoder operates under the control of a state machine 514, such as... Figure 11 The diagram shows the state transition of state machine 514. The control module has 11 states, operating throughout the decoding process. In different states, it issues different operation instructions to each memory unit and arithmetic unit. For example, in the channel layer arithmetic state, it pulls high the read enable of the channel layer LLR memory 52, alternately pulls high the write enable of the intermediate LLR layer memory 51, controls the output of the write address of the intermediate LLR layer memory 51, outputs signals to control the operation of the computational core module 54, and so on. The entire control state machine 514 is quite complex and contains many elements, so they will not be listed here. In short, the purpose of state machine 514 is to ensure that the decoder's timing conforms to the S-CASCL algorithm principle; its existence is essential for the smooth operation of the decoding process.

[0170] Example 3

[0171] This invention uses the Xilinx ZYNQ7000 series xc7z100ffg900 board as the Field Programmable Gate Array (FPGA) test system chip, and Verilog as the development language to implement the proposed Polar decoder based on the S-CASCL algorithm. The decoder implementation was simulated using QuestaSim, and the back-end synthesis, placement and routing, and on-board verification were performed using Xilinx's Vivado tool.

[0172] The hardware parameters are set as follows: where N and K are the code length and information bit length, respectively.

[0173] (N,K) (64,30)(128,30)(128,60) CRC length 4 Parallelism P 16 List 8 Maximum length of special nodes 16 Quantification method Q7

[0174] The decoder designed in this invention supports three code lengths and code rates, and can be dynamically switched. In order to reduce the complexity of the decoder's control state machine 514, the maximum length of special nodes is limited to the same as the parallelism P, which is 16 in this paper.

[0175] Q7 indicates that the demodulated LLR data is quantized by 7 bits, and the quantization mechanism is (1,2,4), that is, 1 bit sign bit, 2 bits integer bits and 4 bits fractional bits, and the data and value are stored separately.

[0176] The Polar code S-CASCL decoder implemented in this invention is based on the Xilinx ZYNQ7000 xc7z100ffg900 board, and its resource overhead and proportion are shown in the table below:

[0177]

[0178] Define the decoder throughput as:

[0179]

[0180] The throughput of the decoders with three code lengths and code rates designed in this invention at a working frequency of 100MHz is shown in the table below.

[0181]

[0182]

[0183] According to data, Polar code decoders based on special nodes can achieve the same performance as CASCL, with lower resource overhead and higher throughput.

[0184] Example 4

[0185] By testing the correctness of single-frame decoding, analyzing decoding performance curves, and completing a test project for a baseband communication system based on a Xilinx board, we can verify whether a Polar code decoder based on special nodes can be applied in practical engineering.

[0186] 1. Set up a test platform to test whether single-frame decoding is correct:

[0187] This invention establishes a testing platform integrated with Matlab. For example... Figure 12 As shown, the modulation and demodulation, Polar coding, and over-channel noise addition in the baseband communication system are all implemented in Matlab.

[0188] Both the source data and the quantized demodulated data are stored in txt files. Simulations are performed in QuestaSim using these data sources. The quantized LLR data is fed into the Polar code decoder of the S-CASCL algorithm, and the output decoding result is compared with the source data in real time.

[0189] like Figure 13 As shown, the decoding result of (N,K)=(128,60) is displayed. The content stored in source_bit_mem in the figure is the source sequence, and decode_out is the output parallel decoding sequence. decode_out_vld is used as the valid indicator signal. It can be seen that the two are consistent, which proves that the hardware implementation of the decoder of the present invention is correct.

[0190] 2. Input multiple frames of LLR information and test the decoding performance curve:

[0191] like Figure 14 The figure shows a performance simulation diagram of the decoder hardware implementation with code length N=128. Compared with floating-point simulation, performing 7-bit fixed-point quantization on the demodulated data causes a certain performance loss. As can be seen from the figure, at a bit error rate of 10... -4 At that time, 7-bit quantization caused a performance loss of 0.2dB, which is close to that of floating point.

[0192] 3. Complete the test project for a baseband communication system based on Xilinx boards to verify whether the decoder can be applied in actual engineering:

[0193] This invention also establishes a baseband communication platform based on a Xilinx FPGA, such as... Figure 15 As shown, the entire baseband processing flow is implemented in Verilog. The source is replaced by a pseudo-random sequence m-sequence. After bpsk modulation, the data is fixed at 16 bits and then sent to the channel for noise addition. Before decoding, the 16-bit wide data is truncated to 7 bits and then sent to the decoder for decoding. ILA is used to capture and compare whether the two are consistent.

[0194] like Figure 16 The figure shows the hexadecimal representation of the captured result when (N,K)=(128,60). Here, source_crc_data is the source sequence, and decoder_out outputs the decoded sequence and an additional CRC checksum sequence, both read from the least significant bit. As can be seen from the figure, after the source is generated, it undergoes modulation, noise addition, and decoding, and the decoded sequence is output after a period of time, as indicated by the boxes in the figure. The consistent pairwise data proves that the decoder is functioning correctly.

[0195] Verification has shown that a low-latency, high-performance, and low-resource-overhead Polar code decoder based on special nodes can be truly applied to practical communication systems.

[0196] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A Polar code decoding method based on special nodes, characterized in that, include: S1. Based on the code structure characteristics of Polar codes, the decoding bit combinations are divided into four types of decoding nodes: Rate-0 (21), Rate-1 (22), Rep (23), and SPC (24). Rate-0 (21): All leaf nodes are frozen nodes; Rep(23): Except for the last leaf node which is an information bit, all other leaf nodes are frozen bits; Rate-1 (22): Nodes whose leaf nodes are all information bits; SPC(24): Except for the first leaf node which is a frozen bit, all other leaf nodes are information bits; S2. Calculate the log-likelihood ratio (LLR) of the four decoding nodes: Rate-0 (21), Rate-1 (22), Rep (23), and SPC (24); S3. The S-CASCL decoding algorithm is used to process the Rate-0 (21), Rate-1 (22), Rep (23) and SPC (24) respectively to obtain the List decoding path; S4. Perform CRC check on the decoding paths of the List, select the optimal decoding path for decoding, and output the result; The S-CASCL decoding algorithm divides the decoding bit combination into multiple special nodes of Rate-0 (21), Rate-1 (22), Rep (23), and SPC (24), calculates the LLR value corresponding to the special node, and obtains the PM value corresponding to the split new path by adding the LLR value and the PM value. The PM values ​​of the new path are sorted, the path is updated according to the sorting result, and after all nodes are processed, a CRC check is performed on the multiple remaining paths to select the optimal decoding path for decoding and output the result. The processing of the Rate-0 (21) node includes: Summing the LLR values ​​less than 0 within the Rate-0 (21) node, adding the summation result to the original PM value, obtaining the PM value corresponding to the new split path, writing it into the PM register, setting the node bits to all 0, and simultaneously updating the PM value of the path: In the formula, 1≤l≤List represents the path number, and L v (j) [l] represents the LLR value corresponding to the j-th bit among the bits contained in the node on the l-th path; The processing method for the Rep(23) node includes: The LLR values ​​of the greater than 0 and less than 0 parts in the Rep (23) node are summed respectively. The two summation results are added to the original PM value to obtain the PM value corresponding to the split new path. The node bit decision value corresponding to the new path is all 1 and all 0. The PM values ​​of all the new paths are sorted and the List of smaller PM values ​​are selected accordingly. For the all-zero path, simultaneously update the PM value of the path: For the all-1 path, simultaneously update the PM value of the path as follows: In the formula, 1≤l≤List represents the path number, and L v (j) [l] indicates the first The LLR value corresponding to the j-th bit among the bits contained in the nodes on the path; The processing method for the Rate-1 (22) node includes: S201. Assign an initial value to all bit decisions of the Rate-1 (22) node. The bit decision formula is as follows: In the formula, L v (i) [l] represents the LLR corresponding to the i-th bit in the bits contained in the node on the l-th path, 1≤l≤List represents the path number, and the bit result of the decision is denoted as B; S202. Process each bit individually, that is, sort all LLR values ​​of the Rate-1 (22) node by absolute value and process them in ascending order: Two paths are generated: one is the original path that retains the previous bit decision value, and the corresponding PM value remains unchanged; the other is the flipped path that flips the corresponding bit decision value, and the corresponding PM value is updated as follows: ， In the formula, L v (i) [l] represents the LLR value corresponding to the i-th bit in the nodes on the l-th path; The processing method for the SPC (24) nodes includes: S201. Assign an initial value to all bits of the node, including: Determine the initial values ​​of the SPC(24) nodes: The parity check bit, which corresponds to the bit with the smallest LLR value, is calculated using the following formula: Solve for the parity check result of the SPC(24) nodes, that is, for the N nodes v The decision values ​​are XORed using the following formula: HD v (i) This is called the hard decision value, and its decision formula is: ， L v (i) [l] represents the LLR value corresponding to the i-th bit in the bits contained in the node on the l-th path; The bit decision value corresponding to the SPC(24) node is obtained as follows: S202. Process each bit individually. For the flipped path, the corresponding bit and the parity check bit's decision value need to be flipped simultaneously. PM is updated as follows: Where j represents the parity bit and i represents the bit currently being processed.

2. A Polar code decoder based on special nodes, characterized in that, According to the Polar code decoding method based on special nodes as described in claim 1, the decoder (5) includes: intermediate LLR layer memory (51), channel layer LLR memory (52), selection module (53), calculation core module (54), feedback bit memory (55), path splitting module (56), PM sorting module (57), path selection module (58), PM memory (59), fast node index memory (510), CRC check unit (511), decoding result memory (512), and mapping matrix memory (513). The LLR data received from the channel is placed in the channel layer LLR memory (52). During decoding, the LLR data is sent to the computing core module (54) for calculation. By using the traditional unit factor calculation structure, the LLR values ​​corresponding to the four special nodes and the data required for processing other special nodes are calculated. The data generated during the calculation process is stored in the intermediate LLR memory (51) and read from it when needed. The feedback bit memory (55) stores hard bit decision values. When the computing core works to the decision layer or processes the four special nodes, that is, after all the data required for node decoding is prepared, the path splitting module (56), the PM sorting module (57) and the path selection module are used. (58) According to the special node’s Rate-0 (21), Rate-1 (22), Rep (23) and SPC (24), the corresponding processing is performed to complete the path splitting and path update operation; after a node is decoded, the bit value of the decision is stored in the decoding result memory (512), and this calculation process is continuously repeated until all nodes are decoded and decided. Then, a CRC check is performed on the multiple paths that are retained in the CRC check unit (511), the decoding result memory (512) stores the decoding result, and outputs the path that passes the CRC check or has the smallest PM value as the optimal path. The corresponding decoding bits on this path are the decoding result of the S-CASCL algorithm.

3. A Polar code decoder based on special nodes according to claim 2, characterized in that, In the core computing module (54), a semi-parallel computing core is used, and an upper limit parallelism P is set for the number of computing units PE in the decoder, with a value of 2. p .

4. A Polar code decoder based on special nodes according to claim 2, characterized in that, The mapping matrix memory (513) includes an address mapping storage unit, which uses an address mapping matrix to store the mapping relationship between each physical path and logical path. For a code length of N=2, n The Polar code, the address mapping matrix memory (513) contains List×(n-1) elements, the content of which is the path number of [log2List] bits. Different rows correspond to different paths, and different columns correspond to different layers. When the path is split and filtered, it is only necessary to copy and modify the content of the address mapping matrix memory (513) to complete the path filtering process, and add List×List×(n-1)[log2List] storage units.

5. A Polar code decoder based on special nodes according to claim 2, characterized in that, In the core calculation module (54), the storage and operation method of LLR is modified. When storing LLR, the form of sign bit + absolute value is used instead of complement. L1~L4 on the unit factor represent the log-likelihood ratio soft information LLR value. By converting the calculation formula of L3 and L4 in the unit factor, the calculation transfer formula of processing sign bit and data bit separately can be obtained: ， In the formula, sgn() means taking the sign bit of the content in parentheses, and amp means taking the amplitude value, which is the absolute value.

6. A Polar code decoder based on special nodes according to claim 2, characterized in that, In the PM sorting module (57), among the 2 List paths that need to be sorted, the PM values ​​of the List paths already exist and have been sorted during the decoding of the previous bit or node. The remaining PM values ​​are obtained by adding a positive number to the known List paths. The positive number is the absolute value of the soft information value of the current decoded bit. Therefore, using the known List, the PM sorting task can be represented as: Given an ordered sequence of length List: μ0 ≤ μ1 ≤ μ List-1 A new sequence m = [m0, m1, ..., mn] of length 2List. 2List-1 Constructed by the following formula, where l=0,...List-1, and α l ≥0; ， It can be seen that sequence m has the following properties: ， Therefore, we can know any two m l There is no need to compare the items (l≤List) with each other, because the size order is known.

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