Multi-node message reception dynamic release systems, methods, and media

Abstract

The application discloses a kind of multi-node message receiving dynamic release system, method and medium, belong to spaceflight TT&C technical field, including steps: RapidIO switching network in system, first end is interconnected with multiple sending nodes by RapidIO port;Second end is interconnected with FPGA receiving node by RapidIO port.RapidIO message ID pre-processing and parallel message ID receiving processing two-stage processing mode are used in FPGA receiving node, and according to the message receiving completion instruction signal fed back by parallel message ID receiving processing module, message ID in pre-processing module is initialized in real time, to reach the ability of dynamic release message receiving processing.The application provides a kind of multi-node RapidIO message receiving design scheme with simple software implementation and strong expansibility.

Description

Technical Field

[0001] This invention relates to the field of aerospace telemetry and control technology, and more specifically, to a multi-node message receiving and dynamic release system, method, and medium. Background Technology

[0002] With the development of manned spaceflight technology, the requirements for computational load and real-time performance in aerospace telemetry and control systems are becoming increasingly demanding. Relying solely on improved single-chip processing power is no longer sufficient to meet the rapidly evolving needs of telemetry and control systems. The combination of FPGA+DSP+PPC heterogeneous chip architecture has gradually become the mainstream hardware configuration in telemetry and control systems. FPGA chips are characterized by high programmability, short development cycles, and powerful parallel processing capabilities, facilitating the integration of multiple peripheral devices. Preprocessing of acquired data is performed within the FPGA chip, and the preprocessed data is then sent to the DSP processor. The powerful computing capabilities of the DSP processor enable high-speed algorithms and data analysis. The PPC processor typically serves as the system's management unit, responsible for the overall system management and scheduling. In the aforementioned FPGA+DSP+PPC heterogeneous platform, traditional parallel buses are no longer sufficient. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a multi-node message receiving and dynamic release system, method, and medium. Without increasing software complexity, this invention solves the problem of excessive resource consumption when using FPGA nodes as receivers to receive message data from multiple RapidIO nodes in existing systems. It reduces software resource overhead, design complexity, and power consumption, effectively improving system reliability.

[0004] The objective of this invention is achieved through the following solution:

[0005] A multi-node message receiving and dynamic release system includes a sending node, a RapidIO switching network, and a receiving node. The sending node is connected to the RapidIO switching network, and the receiving node is connected to the RapidIO switching network.

[0006] The sending node sends data to the receiving node using RapidIO message communication.

[0007] The receiving node adopts a two-level processing method: a message ID preprocessing module and a parallel message ID receiving and processing module.

[0008] Furthermore, the number of transmitting nodes is N, where N is an integer greater than or equal to 1, and the transmitting nodes include any one or more of the following types: FPGA, DSP, and PPC; the receiving nodes include FPGA receiving nodes.

[0009] Furthermore, each of the sending nodes 1 to N is connected to the RapidIO switching network through one 4X or 1X RapidIO port; the FPGA receiving node is connected to the RapidIO switching network through one 4X or 1X RapidIO port; the chips in the RapidIO switching network include those using the CPS1848 chip.

[0010] Furthermore, the total number of nodes sent by the sending node is less than or equal to 4, and the total number of nodes not sent simultaneously exceeds 10.

[0011] A method for dynamic release of multi-node message reception, based on the multi-node dynamic release system described above, wherein the receiving node employs a two-level processing approach consisting of a message ID preprocessing module and a parallel message ID reception processing module, specifically includes the following steps:

[0012] When the receiving node is an FPGA receiving node, the RapidIO message preprocessing module first pre-initializes multiple message IDs, pre-setting them according to the different received RapidIO message IDs, and then passes the pre-processed data and ID information to multiple subsequent parallel message ID receiving and processing modules. When any one of the multiple receiving and processing modules finishes receiving and processing message data, it feeds back the corresponding information to the RapidIO message ID preprocessing module to initialize the corresponding message ID, thereby dynamically releasing the resources of the message ID receiving and processing module corresponding to the corresponding message ID.

[0013] Furthermore, the FPGA receiving node is internally implemented using a software architecture consisting of a RapidIO IP core, a RapidIO message ID preprocessing module, and four parallel message ID receiving and processing modules. The FPGA receiving node receives serial RapidIO data packets from the RapidIO switching network by calling the RapidIO IP core, and converts the serial RapidIO data packets into parallel data RapidIO_Data at the logic layer. After the parallel data RapidIO_Data is processed by the RapidIO message ID preprocessing module, message data Data + message ID1 to ID4 are output. The preprocessed message data Data and message ID1 to ID4 are simultaneously sent to the four parallel message ID receiving and processing modules. The four parallel message ID receiving and processing modules adapt the message IDs to match the set message IDs, and after processing, form the corresponding channel data Ch1_Data to Ch4_Data and channel Ch1_ID to Ch4_ID.

[0014] Once any one of the four parallel message ID receiving and processing modules has finished receiving and processing message data, it feeds back the corresponding reception completion information indication signal ID1_Recv_Done~ID4_Recv_Done to the aforementioned RapidIO message ID preprocessing module. The RapidIO message ID preprocessing module initializes the corresponding message ID to 0xFF so that the resources of the message ID receiving and processing module corresponding to the corresponding message ID can be released.

[0015] Furthermore, the RapidIO message preprocessing process in the FPGA receiving node enters the initial state after power-on reset; it monitors whether the message reception completion indication signal ID_Recv_Done input from the four parallel message ID receiving and processing modules is valid. If it is, it enters the message ID initialization process and initializes the corresponding message ID to 0xFF; otherwise, it switches to monitoring the status of the received RapidIO data packet; if the received RapidIO data packet is a message, it enters the message ID occupancy status determination; otherwise, it returns to the initial state.

[0016] Furthermore, when monitoring whether a message ID is occupied, if it is occupied, it means that the message ID data received this time was previously being processed and subsequent processing resources have not been released, so it is directly sent to the subsequent message ID receiving and processing module for processing; otherwise, it means that the message received this time is new message ID data, so it is switched to the message ID setting state, updated and sent to the corresponding subsequent message ID receiving and processing module for processing, and then returned to the initial state.

[0017] Furthermore, the number of message IDs is 4, and the initialization is 0xFF.

[0018] A computer-readable storage medium storing a computer program therein, the computer program being loaded by a processor and executing the method as described in any of the preceding claims.

[0019] The beneficial effects of this invention include:

[0020] (1) This invention improves the scalability of the FPGA receiving node in the system. Specifically, by using a message receiving dynamic release method, the FPGA node can receive RapidIO message data sent by any number of nodes without increasing software resource overhead.

[0021] (2) This invention can effectively reduce the complexity of FPGA design, facilitate timing convergence, and reduce system power consumption. Specifically, it replaces the resource stacking method used in the original design with a message reception and dynamic release method. As the number of nodes increases linearly, the FPGA resource usage can remain constant. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a multi-node message receiving and dynamic release method according to an embodiment of the present invention;

[0024] Figure 2 For is Figure 1 The implementation principle diagram;

[0025] Figure 3 for Figure 2 A flowchart of RapidIO message ID preprocessing. Detailed Implementation

[0026] All features disclosed in all embodiments of this specification, or steps in all methods or processes implied in the disclosure, may be combined and / or extended or replaced in any way, except for mutually exclusive features and / or steps.

[0027] In view of the problems in the background, the inventors of this invention, after creative analysis and thinking, discovered that the high-speed serial RapidIO bus based on the packet switching architecture, with its high bandwidth, low latency, and high reliability, provides a good solution for high-speed interconnection between multiple heterogeneous chips in aerospace telemetry and control systems.

[0028] Data communication using the RapidIO protocol generally falls into two categories: memory-mapped communication and message-based communication. Memory-mapped communication is often used in situations requiring large amounts of data to be transmitted at once and high real-time performance. Because memory-mapped transmissions do not return values ​​(memory-mapped writes), the reliability of data transmission cannot be guaranteed. Message-based communication is often used in situations requiring small amounts of data to be transmitted at once (4KB or less) and high reliability, although its speed is slightly lower than memory-mapped communication. In existing aerospace telemetry and control systems, short data transmissions and command transmissions primarily utilize message-based communication.

[0029] In traditional telemetry and control systems, the number of devices is relatively small, and communication is generally one-to-one or one-to-many (usually less than four devices). With the development of aerospace integrated technology, the number of devices in telemetry and control systems is becoming increasingly large, and the number of one-to-many communication devices is increasing to 10 or even more. Handling one-to-many communication in an FPGA is significantly more difficult. Generally, once FPGA resources are occupied, they cannot be released immediately. As the receiving node, the number of message receiving nodes determines the amount of internal FPGA resources used. If we calculate the resource usage of receiving information from a single node on the FPGA as 'a%', then receiving from 10 nodes would require 10*a% of the FPGA resources, increasing linearly with the number of receiving nodes. Increased internal FPGA resource usage leads to increased compilation time, increased power consumption, and timing convergence difficulties.

[0030] To address the aforementioned technical problems, this invention provides a dynamic release method for multi-node message reception. This method aims to solve the problem of excessive resource consumption when FPGA nodes are used as receivers to receive messages from multiple RapidIO nodes in existing systems, without increasing software complexity. It reduces software resource overhead, design complexity, and power consumption, effectively improving system reliability.

[0031] In a specific embodiment, such as Figure 1 As shown in the figure, a multi-node message receiving and dynamic release method according to an embodiment of the present invention comprises: sending nodes (1 to N) + a RapidIO switching network + an FPGA receiving node. Each sending node (1 to N) in the system is connected to the RapidIO switching network through one 4X RapidIO port; the FPGA receiving node is connected to the RapidIO switching network through one 4X RapidIO port; the chip in the RapidIO switching network uses CPS1848 or a corresponding domestically produced switching device. Sending nodes 1 to N send data to the FPGA receiving node using RapidIO message communication.

[0032] like Figure 2 As shown, the FPGA receiving node is implemented using a software architecture consisting of a RapidIO IP core, a RapidIO message ID preprocessing module, and four parallel message ID receiving and processing modules. The following example illustrates this with four message nodes receiving messages simultaneously.

[0033] Figure 2In this process, on one hand, the FPGA receiving node receives serial RapidIO data packets from the RapidIO switching network by calling the RapidIO IP core, and converts the serial RapidIO data packets into logic layer parallel data RapidIO_Data. After processing by the RapidIO message ID preprocessing module, the parallel data RapidIO_Data outputs message data Data + message ID1 to ID4. The preprocessed message data Data + message ID1 to ID4 are simultaneously sent to four parallel message ID receiving and processing modules. These four modules adapt the message IDs to match the set message IDs, forming corresponding channel data Ch1_Data to Ch4_Data + channel Ch1_ID to Ch4_ID. On the other hand, when any one of the four parallel message ID receiving and processing modules finishes receiving and processing the message data, it feeds back the corresponding reception completion information indication signals ID1_Recv_Done to ID4_Recv_Done to the aforementioned RapidIO message ID preprocessing module. The RapidIO message ID preprocessing module initializes the corresponding message ID to 0xFF to release the resources of the corresponding message ID receiving and processing module. This allows the FPGA receiving node to simultaneously receive four RapidIO messages from the sending node, or to receive RapidIO messages from any number of sending nodes (not simultaneously, but more than four).

[0034] like Figure 3 As shown, the RapidIO message preprocessing flow in the FPGA receiving node enters the initial state after power-on reset. It monitors the validity of the message reception completion indication signal ID_Recv_Done input from the four parallel message ID receiving and processing modules. If valid, it enters the message ID initialization process, initializing the corresponding message ID to 0xFF; otherwise, it switches to monitoring the status of the received RapidIO data packets. If the received RapidIO data packet is a message, it enters the message ID occupancy status determination; otherwise, it returns to the initial state. While monitoring message ID occupancy, if it is occupied, it means the received message ID data was previously being processed and subsequent processing resources have not been released, so it can be directly sent to the subsequent message ID receiving and processing module for processing; otherwise, it means the received message is new message ID data, so it switches to the message ID setting state, updates the ID, sends it to the corresponding subsequent message ID receiving and processing module for processing, and returns to the initial state.

[0035] It should be noted that, within the scope of protection defined in the claims of this invention, the following embodiments can be combined and / or extended or replaced in any logical manner from the above specific embodiments, such as the disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0036] Example 1

[0037] A multi-node message receiving and dynamic release system includes a sending node, a RapidIO switching network, and a receiving node. The sending node is connected to the RapidIO switching network, and the receiving node is connected to the RapidIO switching network.

[0038] The sending node sends data to the receiving node using RapidIO message communication.

[0039] The receiving node adopts a two-level processing method: a message ID preprocessing module and a parallel message ID receiving and processing module.

[0040] Example 2

[0041] Based on Example 1, the number of transmitting nodes is N, where N is an integer greater than or equal to 1, and the transmitting nodes include any one or more of FPGA, DSP, and PPC types; the receiving nodes include FPGA receiving nodes.

[0042] Example 3

[0043] Based on Example 2, each of the sending nodes 1 to N is connected to the RapidIO switching network through one 4X or 1X RapidIO port; the FPGA receiving node is connected to the RapidIO switching network through one 4X or 1X RapidIO port; the chips in the RapidIO switching network include those using CPS1848 chips.

[0044] Example 4

[0045] Based on Example 1, the total number of nodes sent by the sending node is less than or equal to 4, and the total number of nodes not sent simultaneously exceeds 10.

[0046] Example 5

[0047] A method for dynamic release of multi-node message reception, based on the multi-node message reception and dynamic release system described in Embodiment 1, wherein the receiving node adopts a two-level processing approach of a message ID preprocessing module and a parallel message ID reception and processing module, specifically includes the following steps:

[0048] When the receiving node is an FPGA receiving node, the RapidIO message preprocessing module first pre-initializes multiple message IDs, pre-setting them according to the different received RapidIO message IDs, and then passes the pre-processed data and ID information to multiple subsequent parallel message ID receiving and processing modules. When any one of the multiple receiving and processing modules finishes receiving and processing message data, it feeds back the corresponding information to the RapidIO message ID preprocessing module to initialize the corresponding message ID, thereby dynamically releasing the resources of the message ID receiving and processing module corresponding to the corresponding message ID.

[0049] Example 6

[0050] Based on Example 5, the FPGA receiving node is implemented using a software architecture consisting of a RapidIO IP core, a RapidIO message ID preprocessing module, and four parallel message ID receiving and processing modules. The FPGA receiving node receives serial RapidIO data packets from the RapidIO switching network by calling the RapidIO IP core and converts the serial RapidIO data packets into parallel data RapidIO_Data at the logic layer. After the parallel data RapidIO_Data is processed by the RapidIO message ID preprocessing module, message data Data + message ID1 to ID4 are output. The preprocessed message data Data and message ID1 to ID4 are simultaneously sent to the four parallel message ID receiving and processing modules. The four parallel message ID receiving and processing modules adapt the message IDs to match the set message IDs, and after processing, form the corresponding channel data Ch1_Data to Ch4_Data and channel Ch1_ID to Ch4_ID.

[0051] Once any one of the four parallel message ID receiving and processing modules has finished receiving and processing message data, it feeds back the corresponding reception completion information indication signal ID1_Recv_Done~ID4_Recv_Done to the aforementioned RapidIO message ID preprocessing module. The RapidIO message ID preprocessing module initializes the corresponding message ID to 0xFF so that the resources of the message ID receiving and processing module corresponding to the corresponding message ID can be released.

[0052] Example 7

[0053] Based on Example 5, the RapidIO message preprocessing process in the FPGA receiving node enters the initial state after power-on reset; it monitors whether the message reception completion indication signal ID_Recv_Done input by the four parallel message ID receiving and processing modules is valid. If it is, it enters the message ID initialization process and initializes the corresponding message ID to 0xFF; otherwise, it switches to monitoring the status of the received RapidIO data packet; if the received RapidIO data packet is a message, it enters the message ID occupancy status determination; otherwise, it returns to the initial state.

[0054] Example 8

[0055] Based on Example 8, when monitoring whether the message ID is occupied, if it is occupied, it means that the message ID data received this time is the one that was previously being processed and subsequent processing resources have not been released, so it is directly sent to the subsequent message ID receiving and processing module for processing; otherwise, it means that the message received this time is new message ID data, so it is switched to the message ID setting state, updated and sent to the corresponding subsequent message ID receiving and processing module for processing, and then returned to the initial state.

[0056] Example 9

[0057] Based on Example 5, the number of message IDs is 4, and the initialization is 0xFF.

[0058] Example 10

[0059] A computer-readable storage medium storing a computer program, the computer program being loaded by a processor and executed as described in any one of Examples 5 to 9.

[0060] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0061] According to one aspect of the present invention, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0062] In another aspect, embodiments of the present invention also provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods described in the above embodiments.

[0063] In addition to the examples above, other embodiments may be obtained by those skilled in the art based on the above disclosure or by making modifications using knowledge or technology in related fields. The features of each embodiment may be interchanged or replaced. Modifications and changes made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for dynamic release of multi-node message reception, characterized in that, Based on a multi-node message receiving and dynamic release system, the system includes a sending node, a RapidIO switching network, and a receiving node. The sending node and the receiving node are connected to the RapidIO switching network. The sending node sends data to the receiving node using RapidIO message communication. The receiving node employs a two-level processing approach: a message ID preprocessing module and a parallel message ID receiving and processing module. Specifically, the two-level processing approach includes the following steps: When the receiving node is an FPGA receiving node, the RapidIO message preprocessing module first pre-initializes multiple message IDs, pre-setting them according to the different received RapidIO message IDs, and then passes the pre-processed data and ID information to multiple subsequent parallel message ID receiving and processing modules. When any one of the multiple receiving and processing modules finishes receiving and processing message data, it feeds back the corresponding information to the RapidIO message ID preprocessing module to initialize the corresponding message ID, thereby dynamically releasing the resources of the message ID receiving and processing module corresponding to the corresponding message ID.

2. The multi-node message receiving and dynamic release method according to claim 1, characterized in that, The number of transmitting nodes is N, where N is an integer greater than or equal to 1, and the transmitting nodes include any one or more of the following types: FPGA, DSP, and PPC; the receiving nodes include FPGA receiving nodes.

3. The multi-node message receiving and dynamic release method according to claim 1, characterized in that, Each of the sending nodes 1 to N is connected to the RapidIO switching network through one 4X or 1X RapidIO port; the FPGA receiving node is connected to the RapidIO switching network through one 4X or 1X RapidIO port; the chips in the RapidIO switching network include CPS1848 chips.

4. The multi-node message receiving and dynamic release method according to claim 1, characterized in that, The total number of nodes sent by the sending node is less than or equal to 4, and the total number of nodes not sent simultaneously exceeds 10.

5. The multi-node message receiving and dynamic release method according to claim 1, characterized in that, The FPGA receiving node is implemented using a software architecture consisting of a RapidIO IP core, a RapidIO message ID preprocessing module, and four parallel message ID receiving and processing modules. The FPGA receiving node receives serial RapidIO data packets from the RapidIO switching network by calling the RapidIO IP core, and converts these serial RapidIO data packets into parallel logic layer data RapidIO_Data. After processing by the RapidIO message ID preprocessing module, the parallel data RapidIO_Data outputs message data Data + message ID1~ID4. The preprocessed message data Data and message IDs1~ID4 are simultaneously sent to the four parallel message ID receiving and processing modules. These modules adapt the message IDs to match the set message IDs, forming corresponding channel data Ch1_Data~Ch4_Data and channel Ch1_ID~Ch4_ID. Once any one of the four parallel message ID receiving and processing modules has finished receiving and processing message data, it feeds back the corresponding reception completion information indication signal ID1_Recv_Done~ID4_Recv_Done to the aforementioned RapidIO message ID preprocessing module. The RapidIO message ID preprocessing module initializes the corresponding message ID to 0xFF so that the resources of the message ID receiving and processing module corresponding to the corresponding message ID can be released.

6. The multi-node message receiving and dynamic release method according to claim 1, characterized in that, The RapidIO message preprocessing process in the FPGA receiving node enters the initial state after power-on reset; it monitors whether the message reception completion indication signal ID_Recv_Done input from the four parallel message ID receiving and processing modules is valid. If it is, it enters the message ID initialization process and initializes the corresponding message ID to 0xFF; otherwise, it switches to monitoring the status of the received RapidIO data packet; if the received RapidIO data packet is a message, it enters the message ID occupancy status determination; otherwise, it returns to the initial state.

7. The multi-node message receiving and dynamic release method according to claim 1, characterized in that, If the message ID is occupied while monitoring whether the message ID is in use, it means that the message ID data received this time was previously being processed and subsequent processing resources have not been released. In this case, it is directly sent to the subsequent message ID receiving and processing module for processing. Otherwise, it means that the message received this time is new message ID data. In this case, the process is switched to the message ID setting state, updated, and then sent to the corresponding subsequent message ID receiving and processing module for processing, and then returned to the initial state.

8. The multi-node message receiving and dynamic release method according to claim 1, characterized in that, The number of message IDs is 4, and the initialization is 0xFF.

9. A computer-readable storage medium, characterized in that, A computer program is stored in a readable storage medium, the computer program being loaded by a processor and executing the method as described in any one of claims 1 to 8.

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