Semiconductor structure, method of manufacturing the same, and semiconductor device

Abstract

The application relates to a semiconductor structure, a preparation method thereof and a semiconductor device. The semiconductor structure comprises a substrate, a bit line structure and a dielectric layer. The substrate comprises active regions and isolation structures arranged at intervals. The bit line structure is arranged on the substrate in parallel at intervals. The bit line structure comprises a first part and a second part. The dielectric layer covers the upper surface and the side surface of the bit line structure and covers the upper surface of the substrate. The top surface of the dielectric layer near the bottom of the first part is higher than or flush with the top surface of the dielectric layer near the bottom of the second part. In the semiconductor structure, the top surface of the dielectric layer near the bottom of the first part is higher than or flush with the top surface of the dielectric layer near the bottom of the second part. When a node contact hole is formed, the etching process will not be inclined to the two sides of the first part, so that the node contact hole cannot expose the active region. The semiconductor structure provides greater controllability and a process window for the etching process of the node contact hole and solves the problem that the node contact hole cannot be opened.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure, its preparation method, and a semiconductor device. Background Technology

[0002] With advancements in semiconductor technology, device dimensions are becoming smaller and smaller, and the node contact structures between bit lines are also becoming smaller and smaller.

[0003] In traditional bitline structure fabrication processes, the portion of the bitline structure that does not contact the active region is located above the substrate, and its bottom is relatively wide, encroaching on the space of the memory node contact structure. Such a structural morphology is prone to causing residual silicon nitride to sink into the bitline contact trench after acid washing. As a result, during the formation of the node contact hole, the plasma cannot accumulate towards the active region side, causing the node contact hole to fail to open. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure, its fabrication method, and a semiconductor device to address the problems in the background art.

[0005] One embodiment of this application discloses a semiconductor structure, including: a substrate, a bit line structure, and a dielectric layer. The substrate includes active regions and isolation structures arranged at intervals. The bit line structures are arranged in parallel intervals on the substrate, and the bit line structures include a first part and a second part. The dielectric layer covers the upper surface and side surface of the bit line structures and covers the upper surface of the substrate, wherein the top surface of the dielectric layer on the substrate near the bottom of the first part is higher than or flush with the top surface of the dielectric layer on the substrate near the bottom of the second part.

[0006] In the above semiconductor structure, the top surface of the dielectric layer near the bottom of the first part is higher than or flush with the top surface of the dielectric layer near the bottom of the second part. This ensures that when forming node contact holes in subsequent processes, the etching process will not be biased towards the sides of the first part, thus preventing the node contact holes from exposing the active area. This provides greater controllability and process window for the etching process of node contact holes, solving the problem of node contact holes not being able to open.

[0007] In one embodiment, the first portion is located above and electrically connected to the active region, and the second portion is located above the isolation structure.

[0008] In one embodiment, the semiconductor structure further includes a node contact structure located between two adjacent bit line structures, penetrating a dielectric layer on the substrate, and electrically connected to an active region located below the node contact structure.

[0009] In one embodiment, the node contact structure includes a conductive layer and the dielectric layer includes a silicon nitride layer.

[0010] One embodiment of this application discloses a semiconductor device including the semiconductor structure in any of the foregoing embodiments.

[0011] One embodiment of this application discloses a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an active region and an isolation structure arranged at intervals; forming a plurality of parallel spaced bit line structures on the substrate, the bit line structures including a first part and a second part; forming a dielectric layer, the dielectric layer covering the surface of the bit line structures and covering the upper surface of the substrate; forming a protective layer, the protective layer covering the surface of the dielectric layer; removing a portion of the dielectric layer located on the sidewalls of the bit line structures; removing a portion of the dielectric layer on the substrate such that the top surface of the dielectric layer remaining on both sides of the bottom of the first part is higher than or flush with the top surface of the dielectric layer remaining on both sides of the bottom of the second part.

[0012] The above-mentioned semiconductor structure fabrication method can perform step-by-step thinning of the dielectric layer by forming a protective layer on the surface of the dielectric layer. In particular, when thinning the dielectric layer on both sides of the bottom of the bit line structure, the top surface of the dielectric layer remaining on both sides of the bottom of the first part is controlled to be higher than or flush with the top surface of the dielectric layer remaining on both sides of the bottom of the second part. This makes it easier to open the node contact hole when forming the node contact hole, expose the active region in the substrate, and improve the situation where the node contact hole is difficult to open.

[0013] In one embodiment, the first portion is located above the active region and electrically connected to the active region, and the second portion is located above the isolation structure.

[0014] In one embodiment, removing a portion of the dielectric layer located on the sidewall of the bit line structure includes: removing the protective layer located on the sidewall of the bit line structure; removing a portion of the dielectric layer located on the sidewall of the bit line structure using a trimming etching process; and introducing a cleaning gas to clean the resulting structure.

[0015] In one embodiment, the purging gas includes an inert gas.

[0016] In one embodiment, removing the protective layer and a portion of the dielectric layer on the substrate includes: removing the protective layer above the substrate; etching the dielectric layer on the substrate using a directional etching process to remove a portion of the dielectric layer, such that the top surface of the dielectric layer remaining on both sides of the first portion is higher than or flush with the top surface of the dielectric layer remaining on both sides of the second portion.

[0017] In one embodiment, the directional etching process includes a plasma directional etching process.

[0018] In one embodiment, the dielectric layer includes a silicon nitride layer and the protective layer includes a photoresist layer.

[0019] In one embodiment, after removing the protective layer and part of the dielectric layer on the substrate, the method further includes: forming node contact holes between adjacent bit line structures, the node contact holes exposing the active region.

[0020] In one embodiment, forming a node contact hole between adjacent bit line structures includes: forming a fill layer that fills the gap between adjacent bit line structures and the top surface of the fill layer is flush with the top surface of the bit line structure; forming an opening in the fill layer that penetrates the fill layer and exposes the upper surface of the substrate; and forming a node contact hole to expose the active region.

[0021] In one embodiment, after forming the node contact hole, the method further includes: forming a node contact structure in the node contact hole, the node contact structure being electrically connected to the active region. Attached Figure Description

[0022] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment of this application;

[0023] Figure 2 for Figure 1 Top view of the semiconductor structure shown;

[0024] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure in another embodiment of this application;

[0025] Figure 4 This is a schematic cross-sectional view of the semiconductor structure in another embodiment of this application;

[0026] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0027] Figure 6 This is a schematic cross-sectional view of a semiconductor structure formed on a substrate according to an embodiment of this application;

[0028] Figure 7 This is a schematic cross-sectional view of the semiconductor structure after the dielectric layer is formed in one embodiment of this application;

[0029] Figure 8 This is a schematic cross-sectional view of the semiconductor structure after the protective layer has been formed in one embodiment of this application;

[0030] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after removing part of the dielectric layer on the sidewall of the bit line structure in one embodiment of this application;

[0031] Figure 10a This is a schematic cross-sectional view of a semiconductor structure after directional etching of the dielectric layer on the substrate in one embodiment of this application;

[0032] Figure 10b This is a schematic cross-sectional view of a semiconductor structure after directional etching of the dielectric layer on the substrate, as shown in another embodiment of this application.

[0033] Figure 11 This is a schematic cross-sectional view of the semiconductor structure after removing the protective layer on top of the bit line structure in one embodiment of this application;

[0034] Figure 12 This is a schematic cross-sectional view of the semiconductor structure after the sidewall structure is formed in one embodiment of this application;

[0035] Figure 13 This is a schematic cross-sectional view of the semiconductor structure after the filling layer is formed in one embodiment of this application;

[0036] Figure 14 This is a schematic cross-sectional view of a semiconductor structure after an opening is formed in the filler layer according to an embodiment of this application;

[0037] Figure 15 This is a schematic cross-sectional view of the semiconductor structure after the node contact hole is formed in one embodiment of this application;

[0038] Figure 16 This is a schematic cross-sectional view of the semiconductor structure after the node contact structure is formed in one embodiment of this application.

[0039] Explanation of icon numbers:

[0040] 10. Substrate; 11. Active region; 12. Isolation structure; 121. Horizontal portion; 20. Bit line structure; 21. First portion; 22. Second portion; 23. Bit line contact trench; 30. Dielectric layer; 40. Node contact structure; 41. Node contact hole; 50. Protective layer; 60. Sidewall structure; 61. First insulating layer; 62. Second insulating layer; 70. Filler layer; 71. Opening. Detailed Implementation

[0041] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0044] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0045] With advancements in semiconductor technology, device sizes are shrinking. In the array region of DRAM memory devices, the portion of the bit line structure not electrically connected to the active region is located above the substrate, with a wider bottom that encroaches on the space of the memory node contact structure. This structural morphology makes it easy for residual silicon nitride to recess into the bit line contact trench after acid etching. Consequently, during the formation of the node contact hole, plasma cannot accumulate towards the active region side, preventing the node contact hole from opening. Ultimately, the formed node contact structure cannot be electrically connected to the active region.

[0046] To address the aforementioned problems, one embodiment of this application discloses a semiconductor structure, such as... Figure 1 As shown, the substrate includes a substrate 10, a bit line structure 20, and a dielectric layer 30. The substrate 10 includes active regions 11 and isolation structures 12 arranged at intervals. The bit line structure 20 is arranged in parallel at intervals on the substrate 10 and includes a first part 21 and a second part 22. The dielectric layer 30 covers the upper surface and side surface of the bit line structure 20 and covers the upper surface of the substrate 10. The top surface of the dielectric layer 30 on the substrate 10 near the bottom of the first part 21 is higher than or flush with the top surface of the dielectric layer 30 on the substrate 10 near the bottom of the second part 22.

[0047] In the above semiconductor structure, the top surface of the dielectric layer 30 near the bottom of the first part 21 is higher than or flush with the top surface of the dielectric layer 30 near the bottom of the second part 22. This can prevent the etching process from biasing to both sides of the first part 21 when forming node contact holes in subsequent processes, thus preventing the node contact holes from failing to expose the active region 11. This provides greater controllability and process window for the etching process of node contact holes and solves the problem of node contact holes being unable to open.

[0048] For example, such as Figure 1 As shown, the substrate 10 includes an array of active regions 11 and isolation structures 12, with the active regions 11 located between adjacent isolation structures 12. The isolation structure 12 includes a horizontal portion 121 that covers the upper surface of the active regions 11.

[0049] Figure 2 for Figure 1 A top view of the semiconductor structure shown. Combined with... Figure 1 and Figure 2 It can be seen that the bit line structures 20 are arranged in parallel on the substrate 10, including a first portion 21 and a second portion 22. The first portion 21 is located in the bit line contact trench 23, which exposes the upper surface of the active region 11, making the first portion 21 electrically connected to the active region 11. The second portion 22 is located above the horizontal portion 121 of the isolation structure 12, which isolates the second portion 22 of the bit line structure 20 from the active region 11. For example, the first bit line structure and the second bit line structure are two adjacent bit line structures 20, arranged along... Figure 2 The AA' direction can be used to extract the first part 21 of the first bit line structure and the second part 22 of the second bit line structure, resulting in the following: Figure 1 The diagram shows a cross-sectional structure.

[0050] In some embodiments, the bitline structure 20 may include a bitline conductive layer (not shown) and a bitline insulating layer (not shown) stacked sequentially from bottom to top. The bitline conductive layer includes a polysilicon layer, a barrier metal layer, and a conductor metal layer stacked sequentially from bottom to top. Optionally, in some other embodiments, the bitline conductive layer includes a conductor metal layer and a barrier metal layer surrounding the bottom and sides of the conductor metal layer. As an example, the conductor metal layer may be, for example, a tungsten layer or a copper layer; the barrier metal layer may be, for example, a titanium layer or a titanium nitride layer. The bitline insulating layer may be a nitride layer, such as a silicon nitride layer.

[0051] The dielectric layer 30 covers the upper surface of the substrate 10 and the upper surface and sides of the bit line structure 20, and fills the bit line contact trench 23. For example, the dielectric layer 30 may include, but is not limited to, a silicon nitride layer.

[0052] In some embodiments, such as Figure 1As shown, the dielectric layers 30 on the substrate 10 near the bottom sides of the first part 21 are flush with the top surfaces of the dielectric layers 30 near the bottom sides of the second part 22. When forming node contact holes in subsequent processes, it is easier to etch through the dielectric layers 30 and the top of the substrate 10 to expose the active region 11 near the second part 22, so as to fully open the node contact holes and improve the controllability and process window of the etching process.

[0053] Alternatively, in some embodiments, such as Figure 3 As shown, the top surface of the dielectric layer 30 on the substrate 10 near the bottom sides of the first portion 21 can be higher than the top surface of the dielectric layer 30 on the substrate 10 near the bottom sides of the second portion 22. In subsequent processes, when forming node contact holes, the plasma can concentrate more towards the bottom sides of the second portion 22, accelerating the etching rate of the dielectric layers 30 on the bottom sides of the second portion 22, thus making it easier to open the node contact holes and expose the active region 11 beneath the second portion 22.

[0054] In some embodiments, such as Figure 4 As shown, the semiconductor structure also includes a node contact structure 40 located between two adjacent bit line structures 20. The node contact structure 40 extends through the dielectric layer 30 on the substrate 10 and the top of the substrate 10, and is electrically connected to the active region 11 located below the node contact structure 40.

[0055] For example, the node contact structure 40 may include a material layer with good conductivity, such as a polysilicon layer or a metal layer. Optionally, in some embodiments, to better separate the bit line structure 20 from the node contact structure 40, sidewall structures 60 are also provided on both sides of the bit line structure 20, such as... Figure 4 As shown. For example, the sidewall structure 60 may include a first insulating layer 61 and a second insulating layer 62, wherein the first insulating layer 61 is located on opposite sides of the bit line structure 20, and the second insulating layer covers the bit line structure 20 and the first insulating layer 61. For example, the first insulating layer 61 may be a high-dielectric material layer, such as a silicon dioxide layer, and the second insulating layer 62 may be a high-hardness insulating protective layer 50, such as a silicon nitride layer.

[0056] An embodiment of this application also discloses a semiconductor device, including the semiconductor structure in any of the foregoing embodiments.

[0057] For example, the semiconductor device can be a DRAM memory, or any other semiconductor device including the node contact structure 40. By applying the semiconductor structure in any of the above embodiments to the DRAM memory, the situation where the node contact hole cannot be opened can be greatly improved, so that the node contact structure 40 of the array region has a good electrical connection with the active region 11, thereby improving the product yield.

[0058] like Figure 5 As shown, one embodiment of this application also discloses a method for fabricating a semiconductor structure, comprising:

[0059] S10: A substrate 10 is provided, which includes active regions 11 and isolation structures 12 arranged at intervals. A plurality of parallel and spaced bit line structures 20 are formed on the substrate 10, and the bit line structures 20 include a first part 21 and a second part 22.

[0060] S20: Forming a dielectric layer 30, which covers the surface of the bit line structure 20 and the upper surface of the substrate 10;

[0061] S30: A protective layer 50 is formed, which covers the surface of the dielectric layer 30;

[0062] S40: Remove part of the dielectric layer 30 located on the sidewall of bitline structure 20;

[0063] S50: Remove part of the dielectric layer 30 on the substrate 10, such that the top surface of the dielectric layer 30 remaining on both sides of the bottom of the first part 21 is higher than or flush with the top surface of the dielectric layer 30 remaining on both sides of the bottom of the second part 22.

[0064] The above-described semiconductor structure fabrication method allows for the step-by-step thinning of the dielectric layer 30 by forming a protective layer 50 on the surface of the dielectric layer 30. Specifically, when thinning the dielectric layer 30 on both sides of the bottom of the bit line structure 20, the top surface of the dielectric layer 30 remaining on both sides of the bottom of the first part 21 is controlled to be higher than or flush with the top surface of the dielectric layer 30 remaining on both sides of the bottom of the second part 22. This makes it easier to open the node contact hole and expose the active region 11 in the substrate 10, thus improving the situation where the node contact hole is difficult to open.

[0065] For example, such as Figure 6 As shown, the substrate 10 in step S10 includes an isolation structure 12 and an active region 11 arranged at intervals. As an example, the material of the isolation structure 12 may include, but is not limited to, silicon oxide, silicon nitride, etc., and the substrate 10 may include, but is not limited to, a silicon substrate 10. The isolation structure 12 also includes a horizontal portion 121 located above the active region 11, covering the upper surface of the active region 11.

[0066] For example, at least one bit line contact groove 23 is formed within the horizontal portion 121 of the isolation structure 12, and the bit line contact groove 23 exposes the upper surface of the active region 11. The first portion 21 of the bit line structure 20 is located in the bit line contact groove 23 and is electrically connected to the active region 11; the second portion 22 of the bit line structure 20 is located outside the bit line contact groove 23 and is located on the horizontal portion 121 of the isolation structure 12.

[0067] As an example, the bitline structure 20 may include a bitline conductive layer and a bitline insulating layer stacked sequentially from bottom to top. The bitline conductive layer may include a conductor metal layer and a barrier metal layer surrounding the bottom and sides of the conductor metal layer. The conductor metal layer may be made of a low-resistivity conductive metal material, such as W (tungsten), molybdenum (Mo), Ti (titanium), Cu (copper), or Au (gold). As an example, a chemical vapor deposition process can be used to form the bitline conductive layer. The barrier metal layer may be made of a material layer that provides good barrier properties against both metal and semiconductor materials, such as a titanium nitride layer, a cobalt layer, a platinum layer, or a titanium-tungsten layer. The barrier metal layer also needs to have high conductivity and good adhesion between the semiconductor and the metal. As an example, a chemical vapor deposition process, an atomic layer deposition process, a plasma vapor deposition process, or a rapid thermal oxidation process can be used to form the barrier metal layer. The bitline insulating layer may be a nitride layer, such as silicon nitride. The materials used for each of the above layers may also be selected according to the actual situation, and this disclosure does not limit them.

[0068] In step S20, as Figure 7 As shown, a dielectric layer 30 is formed to cover the surface of the bit line structure 20 and the upper surface of the substrate 10. In some embodiments, the dielectric layer 30 fills the bit line contact trench 23.

[0069] For example, the material of the dielectric layer 30 may include, but is not limited to, a nitride layer, such as a silicon nitride layer. The dielectric layer 30 may be formed on the surface of the bit line structure 20 and the upper surface of the substrate 10 using chemical vapor deposition, atomic layer deposition, or plasma vapor deposition processes.

[0070] In step S30, as Figure 8 As shown, a protective layer 50 is formed on the surface of the dielectric layer 30. The protective layer 50 can be used to protect the dielectric layer 30 in a specific area from etching.

[0071] For example, the protective layer 50 may be a photoresist layer. The step of forming a photoresist layer on the surface of the dielectric layer 30 may include: placing a wafer with a semiconductor structure on a heating plate and baking it at 180 to 250°C for 30 to 80 seconds; buffer cooling the wafer at 50 to 120°C for 15 to 60 seconds; placing the wafer on a rapid cooling plate for rapid cooling; and forming a photoresist layer on the wafer.

[0072] By forming a protective layer 50 on the surface of the dielectric layer 30, the dielectric layer 30 can be thinned in stages and regions. For example, the area to be etched can be etched and removed simply by removing the protective layer 50 on the surface of the area to be etched. For example, the protective layer 50 can be a photoresist layer.

[0073] In step S40, a portion of the dielectric layer 30 located on the sidewall of the bit line structure 20 is removed to obtain... Figure 9 The structure is shown. For example, the specific steps include:

[0074] S41: Remove the protective layer 50 located on the sidewall of bit line structure 20.

[0075] S42: Use a trimming etching process to remove part of the dielectric layer 30 located on the sidewall of bit line structure 20.

[0076] S43: Introduce cleaning gas to clean the resulting structure.

[0077] For example, the protective layer 50 is a photoresist layer and the dielectric layer 30 is a silicon nitride layer. First, the photoresist layer located on the sidewalls of the bit line structure 20 can be removed to expose the silicon nitride layer located on the sidewalls of the bit line structure 20. Then, a trim etch process is used to etch the silicon nitride layer to reduce its thickness. Since the top of the bit line structure 20 and the top of the dielectric layer 30 on the substrate 10 are still covered by the photoresist layer, the trim etch process does not affect the thickness of the silicon nitride layer at these two locations. Finally, a purge gas is introduced to remove the byproducts of the trim etch process. For example, the surface of the semiconductor structure can be cleaned using a cleaning device. The cleaning device may include, for example, a gas purging unit and a gas removal unit. The cleaning device is installed outside the process chamber. A cleaning gas is introduced into the process chamber via a gas purging unit to purge residual byproducts from the semiconductor structure surface. Simultaneously, a gas removal unit is activated to initiate suction and exhaust, removing particles suspended in the process chamber. The cleaning gas includes, but is not limited to, inert gases. For example, the cleaning gas can be at least one of nitrogen, helium (He), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe).

[0078] By forming a protective layer 50, the dielectric layer 30 on the upper surface of the substrate 10 can be protected from the trimming etching process. Furthermore, after the dielectric layer 30 on the sidewall of the bit line structure 20 is thinned by the trimming etching process, a cleaning gas is introduced to remove the byproducts generated by the trimming etching process, which can prevent the residues from affecting the subsequent etching process.

[0079] In step S50, the step of removing a portion of the dielectric layer 30 on the substrate 10 includes:

[0080] S51: Remove the protective layer 50 above the substrate 10;

[0081] S52: The dielectric layer 30 on the substrate 10 is etched using a directional etching process to remove a portion of the dielectric layer 30, so that the top surface of the dielectric layer 30 remaining on both sides of the first portion 21 is higher than or flush with the top surface of the dielectric layer 30 remaining on both sides of the second portion 22, such as... Figure 10a or Figure 10b As shown.

[0082] For example, the directional etching process may include, but is not limited to, plasma-directional etching. After removing the protective layer 50, a plasma-directional etching process is used to control the directional plasma bombardment of the dielectric layer 30 on the upper surface of the substrate 10, thereby thinning the dielectric layer 30. Compared to the non-directional acid etching process, the plasma-directional etching process can directionally adjust the etching degree of different areas of the dielectric layer 30 and adjust the height of different positions of the dielectric layer 30.

[0083] The description uses a silicon nitride layer as the dielectric layer 30. In some embodiments, the silicon nitride layers on both sides of the bottom of the first portion 21 and the silicon nitride layers on both sides of the second portion 22 can be etched to the same degree, so that the thinned silicon nitride layer has a flat surface, such as... Figure 10a As shown, the top surface of the dielectric layer 30 near the bottom of the first part 21 is flush with the top surface of the dielectric layer 30 near the bottom of the second part 22. Since the dielectric layer between two adjacent bit line structures 20 has a flat top surface, the etching process will not be biased towards the sides of the bottom of the first part 21 when forming the node contact hole, so that the formed node contact hole can smoothly expose the active region 11 below the second part.

[0084] Optionally, in some embodiments, the silicon nitride layers on both sides of the bottom of the second portion 22 can be etched to a greater extent, while the silicon nitride layers on both sides of the bottom of the first portion 21 can be etched to a lesser extent, so that the top surface of the silicon nitride layers on both sides of the bottom of the first portion 21 is higher than the top surface of the silicon nitride layers on both sides of the bottom of the second portion 22, such as... Figure 10b As shown. When forming the node contact hole, the etching process can be biased towards the dielectric layer 30 on both sides of the bottom of the second part 22, making it easier for the formed node contact hole to expose the active region 11 below the second part 22.

[0085] In the above semiconductor structure fabrication method, by adopting a directional etching process, the dielectric layer 30 on both sides of the bottom of the bit line structure 20 can be directionally corrected, so that when the node contact hole is etched in the subsequent process, the plasma can be directed more towards the active region 11, ensuring that the node contact hole can be opened, and increasing the controllability and process window of the etching process.

[0086] In some embodiments, after removing the protective layer 50 and part of the dielectric layer 30 on the substrate 10, the method further includes:

[0087] S60: A node contact hole is formed between adjacent bit line structures 20, exposing the active region 11. Optionally, before forming the node contact hole, the following steps are also included:

[0088] S61: Remove the protective layer 50 at the top of the bit line structure 20, such as Figure 11 As shown.

[0089] S62: Side wall structures 60 are formed on both sides opposite to the position line structure 20, such as Figure 12 As shown.

[0090] For example, the sidewall structure 60 may include a first insulating layer 61 and a second insulating layer 62, wherein the first insulating layer 61 is located on opposite sides of the bit line structure 20, and the second insulating layer covers the bit line structure 20 and the first insulating layer 61.

[0091] In some embodiments, the process steps for forming the sidewall structure 60 include:

[0092] S621: A first insulating layer 61 is formed on both sides opposite to the bit line structure 20.

[0093] For example, since the upper surface of the substrate 10, the top of the bit line structure 20, and the sidewalls are covered by the residual dielectric layer 30, a first insulating material layer can be formed on the surface of the residual dielectric layer 30 firstly. The first insulating material layer can be a high-dielectric material layer, such as a silicon dioxide layer. Then, the first insulating material layer located on the upper surface of the dielectric layer 30 is removed to obtain the first insulating layers 61 located on opposite sides of the bit line structure. For example, the process for forming the first insulating material layer can include, but is not limited to, chemical vapor deposition, atomic layer deposition, plasma vapor deposition, or rapid thermal oxidation.

[0094] S622: Form a second insulating layer 62 to cover the top surface of the bit line structure 20 and the first insulating layer 61.

[0095] For example, a second insulating material layer can be formed first on the surface of the resulting structure to cover the upper surfaces of the first insulating layer 61 and the dielectric layer 30. Then, the second insulating material layer above the dielectric layer 30 on the surface of the substrate 10 is removed to form a second insulating layer 62 covering the bit line structure 20 and the first insulating layer 61. The second insulating material layer can be a high-hardness insulating protective layer, such as a silicon nitride layer.

[0096] In some embodiments, such as Figures 13-15 The step of forming a node contact hole 41 between adjacent bit line structures 20 includes:

[0097] S63: A filler layer 70 is formed, which fills the gap between adjacent bit line structures 20, and the top surface of the filler layer 70 is flush with the top surface of the bit line structure 20, such as... Figure 13 As shown.

[0098] For example, the filling layer 70 may include, but is not limited to, a silicon dioxide layer. A silicon dioxide layer may be formed in the gaps between the bit line structures 20 using a deposition process, filling the gaps and covering the upper surface of the bit line structures 20. The upper surface of the silicon dioxide layer is then polished using a chemical mechanical polishing process until the top of the bit line structures 20 is exposed, resulting in the filling layer 70. Optionally, the filling layer 70 may also be a layer of a different material than the second insulating layer 62.

[0099] S64: An opening 71 is formed in the filler layer 70, the opening 71 penetrating the filler layer 70 and exposing part of the upper surface of the dielectric layer 30, such as... Figure 14 As shown.

[0100] For example, a patterned photoresist layer can be formed on the top surface of the resulting structure first, with the pattern in the patterned photoresist layer defining the position and size of each opening 71. Then, an etching process is used to etch the filling layer 70 based on the patterned photoresist layer, forming the openings 71 in the filling layer 70 and exposing part of the upper surface of the dielectric layer 30.

[0101] S65: Form node contact hole 41 to expose active region 11, such as Figure 15 As shown.

[0102] As an example, dielectric layer 30 is a silicon nitride layer. Etching gas for silicon nitride can be added during the etching process to ensure that the silicon nitride layer can be opened. After opening dielectric layer 30, etching continues downwards to expose the active region 11.

[0103] Before forming the node contact hole 41, the dielectric layers 30 on both sides of the bottom of the first part 21 and the dielectric layers 30 on both sides of the second part 22 are etched in a directional manner. While reducing the thickness of the dielectric layers 30, the height of the dielectric layers 30 on both sides of the bottom of the first part 21 is controlled to be equal to or greater than the height of the dielectric layers 30 on both sides of the second part 22. This makes it easier to open the node contact hole 41 and expose the active region 11 when forming the node contact hole 41, thus solving the problem that the node contact hole 41 cannot be opened due to the space occupied by the bit line structure 20.

[0104] In some embodiments, after forming the node contact hole 41, the method further includes: forming a node contact structure 40 in the node contact hole 41, the node contact structure 40 being electrically connected to the active region 11, such as... Figure 16 As shown.

[0105] For example, the node contact structure 40 may include a material layer with good conductivity, such as a polysilicon layer. As an example, a polysilicon layer may be deposited within the node contact hole 41 using chemical vapor deposition, atomic layer deposition, plasma vapor deposition, or rapid thermal oxidation processes to serve as the node contact structure 40. Optionally, the upper surface of the polysilicon layer may be lower than or flush with the upper surface of the bit line structure 20.

[0106] In the above semiconductor structure fabrication method, the surface of the dielectric layer 30 on both sides of the bottom of the bit line structure 20 is modified by directional etching process, making the node contact hole 41 easier to open. The prepared node contact structure 40 maintains good electrical connection with the active region 11, effectively solving the problem of product failure caused by the node contact hole 41 not being opened, and improving the product yield.

[0107] It should be understood that, although Figure 5 The steps in the flowchart shown are displayed sequentially as indicated by the arrows; however, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. For example, step S40 may include steps S41, S42, and S43. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0108] This application also discloses a method for fabricating a semiconductor device, including the method for fabricating the semiconductor structure in any of the above embodiments.

[0109] For example, the semiconductor device can be a DRAM memory, or any other semiconductor device containing a node contact structure. During the fabrication of the semiconductor device, by employing the above-described semiconductor structure fabrication method, the node contact holes can still be kept open even as the device size continues to decrease, ensuring that the node contact structure can be electrically connected to the active region.

[0110] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.

[0111] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, wherein the substrate includes spaced-apart active regions and isolation structures; Bit line structures are arranged in parallel at intervals on the substrate. The bit line structures include a first part and a second part. The first part is located above the active region and is electrically connected to the active region. The second part is located above the isolation structure. A dielectric layer covers the upper surface and side surface of the bit line structure and the upper surface of the substrate, wherein the top surface of the dielectric layer near the bottom of the first portion on the substrate is higher than the top surface of the dielectric layer near the bottom of the second portion on the substrate, and the thickness of the dielectric layer located on the sidewall of the bit line structure is less than the thickness of the dielectric layer located on the top of the bit line structure and on the substrate.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A node contact structure is located between two adjacent bit line structures, penetrates the dielectric layer on the substrate, and is electrically connected to the active region located below the node contact structure.

3. The semiconductor structure according to claim 2, characterized in that, The node contact structure includes a conductive layer, and the dielectric layer includes a silicon nitride layer.

4. A semiconductor device, characterized in that, Including the semiconductor structure as described in any one of claims 1-3.

5. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate includes spaced-apart active regions and isolation structures; A plurality of parallel spaced bit line structures are formed on the substrate. The bit line structures include a first part and a second part. The first part is located above the active region and is electrically connected to the active region. The second part is located above the isolation structure. A dielectric layer is formed, which covers the surface of the bit line structure and the upper surface of the substrate; A protective layer is formed, which covers the surface of the dielectric layer; Remove a portion of the dielectric layer located on the sidewall of the bit line structure, such that the thickness of the dielectric layer located on the sidewall of the bit line structure is less than the thickness of the dielectric layer located on the top of the bit line structure and on the substrate; A portion of the dielectric layer on the substrate is removed such that the top surface of the dielectric layer remaining on both sides of the bottom of the first portion is higher than the top surface of the dielectric layer remaining on both sides of the bottom of the second portion.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The first part is located above the active region and is electrically connected to the active region, and the second part is located above the isolation structure.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, The removal of the portion of the dielectric layer located on the sidewall of the bit line structure includes: Remove the protective layer located on the sidewall of the bit line structure; A trimming etching process is used to remove a portion of the dielectric layer located on the sidewall of the bit line structure. A cleaning gas is introduced to clean the resulting structure.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The cleaning gas includes an inert gas.

9. The method for preparing a semiconductor structure according to claim 5, characterized in that, The removal of the protective layer and part of the dielectric layer on the substrate includes: Remove the protective layer above the substrate; The dielectric layer on the substrate is etched using a directional etching process to remove a portion of the dielectric layer, such that the top surface of the dielectric layer remaining on both sides of the first portion is higher than the top surface of the dielectric layer remaining on both sides of the second portion, and the thickness of the dielectric layer on the substrate is greater than the thickness of the dielectric layer located on the sidewall of the bit line structure.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The directional etching process includes plasma directional etching.

11. The method for preparing a semiconductor structure according to claim 5, characterized in that, The dielectric layer includes a silicon nitride layer, and the protective layer includes a photoresist layer.

12. The method for preparing a semiconductor structure according to any one of claims 5-11, characterized in that, After removing the protective layer and part of the dielectric layer on the substrate, the method further includes: A node contact hole is formed between adjacent bit line structures, and the node contact hole exposes the active region.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, Before forming the node contact hole, the method further includes: Remove the protective layer on top of the bit line structure; Sidewall structures are formed on both sides opposite to the bit line structure.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The process of forming node contact holes between adjacent bit line structures includes: A filling layer is formed, which fills the gap between adjacent bit line structures, and the top surface of the filling layer is flush with the top surface of the bit line structure; An opening is formed in the filling layer, the opening penetrating the filling layer and exposing a portion of the upper surface of the dielectric layer; The node contact hole is formed to expose the active region.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, After forming the node contact hole, the method further includes: A node contact structure is formed in the node contact hole, and the node contact structure is electrically connected to the active region.

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