Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a substrate, a gate oxide layer on the surface of the substrate, a gate stack layer on the surface of the gate oxide layer, an isolation layer covering at least a first sidewall of the gate stack layer, a contact structure on at least the surface of the substrate, and a dielectric layer between the contact structure and a second sidewall of the gate stack layer, the first sidewall and the second sidewall are oppositely arranged, and the thickness of the dielectric layer is less than the thickness of the isolation layer. The difficulty of breakdown of the fuse structure can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] In the field of integrated circuit manufacturing, an electric fuse is a connecting wire in an integrated circuit whose resistance can change significantly (from a low resistance state to a high resistance state) or can be melted.

[0003] The main uses of electric fuses include: (1) to activate redundant circuits to replace defective circuits on the same wafer, thereby effectively improving process yield. In this application, the electric fuse connects the redundant circuits in the integrated circuit. Once a defect is detected in the integrated circuit, the electric fuse is used to repair or replace the defective circuit; (2) for integrated circuit programming functions. To achieve this function, the metal interconnects, device arrays, and programming circuits (including electric fuse devices) are first fabricated on the chip, and then data is input from the outside. That is, the standard chip is made into unique chips through the programming circuit. Electric fuses can greatly save chip research and development and manufacturing costs in integrated circuit programming functions, and are therefore widely used in programmable read-only memory (PROM). In the integrated circuit programming process, the information "1" is written by blowing the electric fuse with a higher voltage to create an open circuit, while the unbroken electric fuse remains connected, which is the state "0".

[0004] Currently, there is a problem with the electric fuse being difficult to melt. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and its fabrication method, which can at least reduce the difficulty of melting an electric fuse.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate, and a gate oxide layer located on the surface of the substrate; a gate stack layer located on the surface of the gate oxide layer; an isolation layer, the isolation layer at least covering a first sidewall of the gate stack layer; a contact structure, the contact structure at least located on the surface of the substrate; and a dielectric layer, the dielectric layer at least located between the contact structure and a second sidewall of the gate stack layer, the first sidewall and the second sidewall being disposed opposite to each other, and the thickness of the dielectric layer being less than the thickness of the isolation layer.

[0007] In some embodiments, the isolation layer is also located on a portion of the top surface of the gate stack layer; a portion of the contact structure is located above the gate stack layer.

[0008] In some embodiments, the contact structure overlaps with the projection of the gate stack on the substrate surface, and the width of the overlapping portion is less than or equal to 0.1 to 0.5 of the width of the gate stack.

[0009] In some embodiments, the thickness of the dielectric layer is less than the thickness of the gate oxide layer.

[0010] In some embodiments, a portion of the contact structure is located within the active region of the substrate.

[0011] In some embodiments, the contact structure includes a contact layer, a barrier layer, and a conductive layer, wherein the barrier layer is located between the contact layer and the conductive layer, and the contact layer is located within the active region.

[0012] In some embodiments, the thickness of the dielectric layer is less than or equal to 3 nm.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, forming a gate oxide layer on the surface of the substrate, forming a gate stack layer on the gate oxide layer; forming an isolation layer, the isolation layer at least covering a first sidewall of the gate stack layer; forming a dielectric layer, the dielectric layer at least covering a second sidewall of the gate stack layer, the first sidewall and the second sidewall being disposed opposite to each other, the thickness of the dielectric layer being less than the thickness of the isolation layer; and forming a contact structure, the contact structure being at least located on the surface of the substrate, and the contact structure being in contact with the surface of the dielectric layer.

[0014] In some embodiments, the method of forming the isolation layer includes: forming an initial isolation layer covering the sidewalls and top surface of the gate stack layer and the surface of the substrate; patterning the initial isolation layer; removing the initial isolation layer located on the second sidewall surface of the gate stack layer; and using the remaining initial isolation layer located on the first sidewall surface and top surface of the gate stack layer as the isolation layer.

[0015] In some embodiments, graphically representing the initial isolation layer includes forming a recess that exposes at least a second sidewall and a portion of the top surface of the gate stack layer, and the recess also exposes the substrate.

[0016] In some embodiments, forming the dielectric layer includes: depositing dielectric material on the sidewalls and bottom of the groove, removing the dielectric material located at the bottom of the groove, and forming a dielectric layer covering the second sidewall of the gate stack layer.

[0017] In some embodiments, before removing the dielectric material located at the bottom of the groove, the method further includes ion implantation of the substrate at the bottom of the groove.

[0018] In some embodiments, forming the contact structure includes: forming a contact layer at the bottom of the groove, the contact layer being electrically connected to the substrate; forming a barrier layer located on the surface of the dielectric layer and the top surface of the contact layer; and forming a conductive layer that fills the groove.

[0019] In some embodiments, the method of forming the dielectric layer includes controlling the thickness of the dielectric layer to be less than the thickness of the gate oxide layer.

[0020] In some embodiments, the contact structure overlaps with the projection of the gate stack on the substrate surface, and the width of the overlapping portion is less than or equal to 0.1 to 0.5 of the width of the gate stack.

[0021] The technical solution provided in this disclosure has at least the following advantages: the electric fuse is formed by a substrate, a gate oxide layer, a gate stack layer, a contact structure, and a dielectric layer. By setting the contact structure close to the gate stack layer, when the voltage on the gate stack layer is large enough, the breakdown path of the electric fuse becomes from the gate stack layer through the dielectric layer to the contact structure, thereby reducing the breakdown difficulty of the entire semiconductor structure. By setting the thickness of the dielectric layer to be smaller than the thickness of the isolation layer, the contact path between the gate stack layer and the contact structure can be reduced, thereby reducing the breakdown difficulty of the entire semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure;

[0024] Figure 2 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure;

[0025] Figures 3 to 7 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0026] As the background technology shows, the current breakdown path of semiconductor structures is from the gate stack layer to the gate oxide layer and then to the substrate, and then to the contact structure through the substrate to connect the electrical signals of the gate stack layer and the contact structure. However, the breakdown of the gate oxide layer is quite difficult.

[0027] This disclosure provides a semiconductor structure that, by placing the contact structure adjacent to the gate stack layer and reducing the thickness of the dielectric layer between the gate stack layer and the contact structure, changes the breakdown path of the semiconductor structure from the gate stack layer through the gate oxide layer and the substrate to the contact structure to the gate stack layer through the dielectric layer to the contact structure. By changing the semiconductor structure breakdown caused by the breakdown of the gate oxide layer to the breakdown of the dielectric layer, the breakdown difficulty of the entire semiconductor structure can be reduced, and the transmission path of the entire electrical signal can be shortened, thereby reducing the electrical signal loss during the transmission process and improving the sensitivity of the semiconductor structure.

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] refer to Figure 1 and Figure 2 , Figure 1 This is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 This is a cross-sectional view of another semiconductor structure provided by way of an embodiment of this disclosure.

[0030] For details, please refer to Figure 1 and Figure 2 The semiconductor structure includes: a substrate 100, and a gate oxide layer 110 located on the surface of the substrate 100; a gate stack layer 120 located on the surface of the gate oxide layer 110; an isolation layer 130 covering at least a first sidewall of the gate stack layer 120; a contact structure 140 located at least on the surface of the substrate 100; and a dielectric layer 150 located at least between the contact structure 140 and a second sidewall of the gate stack layer 120, wherein the first sidewall and the second sidewall are disposed opposite to each other, and the thickness of the dielectric layer 150 is less than the thickness of the isolation layer 130.

[0031] An electric fuse is formed by a substrate 100, a gate oxide layer 110, a gate stack layer 120, a contact structure 140, and a dielectric layer 150. By providing sufficient voltage to the gate stack layer 120, the dielectric layer 150 between the gate stack layer 120 and the contact structure 140 can be broken down, thereby forming a conductive path in the dielectric layer 150 to electrically connect the gate stack layer 120 and the contact structure 140. The signal of the semiconductor structure is then extracted through the contact structure 140. By setting the breakdown path of the semiconductor structure from the gate stack layer 120 through the dielectric layer 150 to the contact structure 140, the breakdown difficulty of the entire semiconductor and structure can be reduced, and the transmission path of the entire electrical signal can be shortened, thereby reducing the electrical signal loss during the transmission process and improving the sensitivity of the semiconductor structure.

[0032] In some embodiments, the material of the substrate 100 may be silicon, germanium, or silicon germanide, and the material of the substrate 100 may also be doped. Taking silicon as an example, a trace amount of trivalent elements, such as boron, indium, gallium, or aluminum, may be doped into the substrate 100 to form a P-type substrate. Similarly, a trace amount of pentavalent elements, such as phosphorus, antimony, or arsenic, may be doped into the substrate 100 to form an N-type substrate. The selection of doping elements for the substrate 100 may be considered based on actual needs and product performance. This disclosure does not limit the material of the substrate 100 or the doped elements.

[0033] In some embodiments, the gate oxide layer 110 is used to prevent direct contact between the gate stack layer 120 and the substrate 100. The principle of gate oxide layer 110 breakdown is as follows: When a high voltage is applied between the upper and lower interfaces of the gate oxide layer 110, defects in the gate oxide layer 110 form individual electron traps, randomly distributed in the middle of the gate oxide layer 110. Under the action of the electric field of the gate oxide layer 110, each electron trap has the ability to trap electrons. Under the action of a high electric field, the regions where electrons are trapped by the electron traps may overlap, forming a current channel in the gate oxide layer 110. This channel then becomes a potential breakdown channel. As the current in the gate stack layer 120 continuously increases, the gate oxide layer 110 forms a current channel, and the performance of the gate oxide layer 110 slowly decreases. When the current further discharges through the current channel, the gate oxide layer 110 is broken down. Since the distribution of electron traps in the gate oxide layer 110 is random, the thinner the gate oxide layer 110, the fewer electron traps are needed to form a path. Therefore, a thin gate oxide layer 110 is more prone to breakdown than a thick gate oxide layer 110.

[0034] In some embodiments, the gate stack 120 may be a four-layer structure, including a first conductive layer 121, an intermediate layer 122, a second conductive layer 123, and a protective layer 124. The first conductive layer 121 is located on the top surface of the gate oxide layer 110, the intermediate layer 122 is located between the first conductive layer 121 and the second conductive layer 123, and the protective layer 124 is located at least on the top surface of the second conductive layer 123. In other embodiments, the gate stack 120 may be a single-layer structure. In other embodiments, the gate stack may be formed by stacking other numbers of layers. The embodiments disclosed herein do not limit the number of layers in the gate stack 120.

[0035] Taking the gate stack 120 as a four-layer structure as an example, the material of the first conductive layer 121 can be a semiconductor material, such as polysilicon; the material of the intermediate layer 122 can be titanium nitride or gallium nitride, etc.; the material of the second conductive layer 123 can be a metal material with good conductivity, such as tungsten metal; and the material of the protective layer 124 can be a hard insulating material, such as silicon nitride.

[0036] Taking polysilicon as an example, by setting the material of the first conductive layer 121 to be polysilicon, during the process of electrical signal transmission between the gate stack layer 120 and the substrate 100, the electrical signal can be transmitted from semiconductor material to semiconductor material, thereby avoiding the abnormality of the electrical signal transmission process caused by the direct transmission of electrical signal from semiconductor material to other materials, thereby improving the stability of signal transmission in the semiconductor structure and improving the reliability of the semiconductor structure.

[0037] Taking titanium nitride as an example, the intermediate layer 122 isolates the first conductive layer 121 from the second conductive layer 123, thereby preventing metal ions from the second conductive layer 123 from diffusing into the first conductive layer 121 during ion diffusion. The intermediate layer 122 prevents ion diffusion from the second conductive layer 123 from contaminating the first conductive layer 121, thereby improving the stability of the first conductive layer 121 and thus improving the reliability of the semiconductor structure.

[0038] Taking tungsten metal as an example, the conductivity of tungsten metal is higher than that of semiconductor materials such as polycrystalline silicon. By setting the material of the second conductive layer 123 to be a metal material, the conductivity of the gate stack layer 120 can be improved, the transmission speed of the electrical signal of the gate stack layer 120 can be increased, and thus the performance of the semiconductor structure can be improved.

[0039] Taking silicon nitride as an example, in some embodiments, the protective layer 124 covers the top surface of the second conductive layer 123. By setting the protective layer 124, the stress of the first conductive layer 121, the intermediate layer 122 and the second conductive layer 123 can be shared when the semiconductor structure is subjected to external pressure, thereby reducing the stress on the first conductive layer 121, the intermediate layer 122 and the second conductive layer 123, thereby protecting the first conductive layer 121, the intermediate layer 122 and the second conductive layer 123, and thus improving the reliability of the semiconductor structure.

[0040] In some embodiments, the isolation layer 130 may be a multi-layer structure stacked together. The isolation layer 130 may include a first isolation layer 131, a second isolation layer 132 and a third isolation layer 133. The first isolation layer 131 covers at least the first sidewall of the gate stack layer 120, and the second isolation layer 132 is located between the first isolation layer 131 and the third isolation layer 133. In other embodiments, the isolation layer may also be a single-layer structure. The embodiments of this disclosure do not limit the number of isolation layers.

[0041] Taking the isolation layer 130 as an example of a three-layer structure, the first isolation layer 131 and the third isolation layer 133 can be made of the same material, which can both be silicon nitride, while the second isolation layer 132 can be made of silicon oxide.

[0042] In some embodiments, the insulating layer 130 is a NON (Nitride-Oxide-Nitride) structure, i.e., a nitride-oxide-nitride structure. By providing the second insulating layer 132, the insulation performance between the first insulating layer 131 and the third insulating layer 133 can be improved. Since the material of the second insulating layer 132 is relatively soft, the morphology formed is poor. Therefore, the morphology of the second insulating layer 132 is improved by forming the first insulating layer 131 and the third insulating layer 133, which are made of nitride layers.

[0043] In other embodiments, after the isolation layer 130 is formed, the substrate 100 is lightly doped and heavily doped. Since a certain space difference needs to be maintained between light doping and heavy doping, the first isolation layer 131 can be used as a mask for light doping, and the third isolation layer 133 can be used as a mask for heavy doping, thereby facilitating subsequent doping processes on the substrate 100.

[0044] In some embodiments, the contact structure 140 may be formed by stacking multiple layers. The contact structure 140 may include a contact layer 141, a barrier layer 142, and a conductive layer 143. The contact layer 141 is located on the surface of the substrate 100, and the barrier layer 142 is located between the contact layer 141 and the conductive layer 143. In other embodiments, the contact structure may also be a single-layer structure. The embodiments of this disclosure do not limit the number of layers of the contact structure 140.

[0045] Taking the three-layer structure of contact structure 140 as an example, the material of contact layer 141 can be a compound of metal and semiconductor material or a semiconductor material doped with metal, such as cobalt silicide; the material of barrier layer 142 can be titanium nitride or gallium nitride; and the material of conductive layer 143 can be a metal material, such as tungsten metal.

[0046] By providing contact layer 141, the Schottky barrier between contact structure 140 and substrate 100 can be reduced, thereby reducing the contact resistance between contact structure 140 and substrate 100, which can improve the response speed of semiconductor structure.

[0047] Taking cobalt silicide as an example, the crystal lattice of cobalt silicide matches well with the silicon crystal lattice, thereby reducing defects between the contact layer 141 and the substrate 100. Compared to directly forming a metal as a contact structure on the surface of the substrate 100, forming the contact layer 141 first can reduce the contact resistance between the contact structure 140 and the substrate 100, as well as the defects between them, thereby improving the performance of the semiconductor structure. In other embodiments, the material of the contact layer 141 can also be a metal silicide such as nickel silicide.

[0048] By forming a barrier layer 142, metal ions from the conductive layer 143 can be prevented from diffusing into the contact layer 141 during ion diffusion. The barrier layer 142 prevents ion diffusion from the conductive layer 143 from contaminating the contact layer 141, thereby improving the stability of the contact layer 141 and thus improving the reliability of the semiconductor structure. In some embodiments, the material of the barrier layer 142 may be at least one of titanium nitride, tantalum nitride, or tantalum silicide.

[0049] In some embodiments, the conductive layer 143 can be made of tungsten metal. Tungsten metal has higher conductivity than semiconductor materials such as polycrystalline silicon. By making the conductive layer 143 a metallic material, the conductivity of the contact structure 140 can be improved, increasing the transmission speed of electrical signals in the contact structure 140, thereby improving the performance of the semiconductor structure. In other embodiments, the conductive layer can also be made of metals such as molybdenum, or semiconductor materials such as polycrystalline silicon.

[0050] refer to Figure 2In some embodiments, the isolation layer 130 is located on a portion of the top surface of the gate stack 120; the partial contact structure 140 is located above the gate stack 120. By placing the isolation layer 130 on a portion of the top surface of the gate stack layer 120, space can be provided for the contact structure 140, thereby allowing a portion of the contact structure 140 to be located above the gate stack layer 120. This increases the breakable area between the gate stack layer 120 and the contact structure 140. The breakable area includes the area of ​​the sidewalls of the first conductive layer 121, the intermediate layer 122, and the second conductive layer 123 facing the contact structure 140, as well as the area of ​​the top surface of the second conductive layer 123 facing the contact structure 140. By increasing the size of the breakable area, the breakdown difficulty of the semiconductor structure is reduced. By making the breakdown path of the semiconductor structure from the gate stack layer 120 to the dielectric layer 150 and then to the contact structure 140, the breakdown difficulty of the semiconductor structure can be reduced. Furthermore, placing the contact structure 140 above the gate stack layer 120 can reduce the volume of the contact structure 140 located on the surface of the substrate 100, thereby reducing the overall volume of the semiconductor structure.

[0051] refer to Figure 2 In some embodiments, the contact structure 140 overlaps with the projection of the gate stack 120 onto the surface of the substrate 100, and the width of the overlapping portion is less than or equal to 0.1 to 0.5 of the width of the gate stack 120. It is understandable that the more overlapping the portion, the larger the area that can be broken down between the gate stack layer 120 and the contact structure 140. However, the more overlapping the portion, the fewer the protective layer 124 and the isolation layer 130 located on the second conductive layer 123. Consequently, the protective layer 124 and the isolation layer 130 can provide a worse protection effect for the first conductive layer 121, the intermediate layer 122, and the second conductive layer 123. The fewer overlapping the portion, the better the protection effect that the protective layer 124 and the isolation layer 130 can provide for the first conductive layer 121, the intermediate layer 122, and the second conductive layer 123. By setting the width of the overlapping portion to be less than or equal to 0.1 to 0.5 of the width of the gate stack layer 120, a certain protection effect is provided while increasing the area that can be broken down between the gate stack layer 120 and the contact structure 140.

[0052] In some embodiments, the partial contact structure 140 is located within the active region of the substrate 100. Specifically, by disposing the partial contact structure 140 within the substrate 100, an electrical connection between the contact structure 140 and the substrate 100 is ensured, thereby ensuring that electrical signals from the substrate 100 and the gate stack 120 are output through the contact structure 140.

[0053] In some embodiments, the contact layer 141 is located within the active region. Specifically, in some embodiments, the top surface of the contact layer 141 may be flush with the top surface of the substrate 100, or the top surface of the contact layer 141 may be higher than the top surface of the substrate 100, that is, the bottom surface of the barrier layer 142 is flush with the top surface of the substrate 100 or the bottom surface of the barrier layer 142 is higher than the top surface of the substrate 100; in other embodiments, the top surface of the contact layer 141 may be lower than the top surface of the substrate 100, that is, the bottom surface of the barrier layer 142 is lower than the top surface of the substrate 100. By setting the contact layer 141 within the substrate 100, the electrical connection between the contact structure 140 and the substrate 100 is ensured, thereby improving the stability of the semiconductor structure.

[0054] It should be noted that "flush" can mean that the top surface of the contact layer 141 is completely flush with the top surface of the substrate 100, or that the height difference between the top surface of the contact layer 141 and the top surface of the substrate 100 is within 1 nm. When the height difference between the top surface of the contact layer 141 and the top surface of the substrate 100 is within 1 nm, it can also be considered that the top surface of the contact layer 141 can be flush with the top surface of the substrate 100.

[0055] refer to Figure 1 In some embodiments, the isolation layer 130 may also cover the entire top surface of the gate stack layer 120. That is, the contact structure 140 is disposed opposite to the second sidewall of the gate stack layer 120, i.e., the projection of the gate stack layer 120 on the surface of the substrate 100 is adjacent to the projection of the contact structure 140 on the surface of the substrate 100.

[0056] The dielectric layer 150 has opposing sidewalls, wherein one sidewall of the dielectric layer 150 is in contact with the gate stack layer 120, and the opposing sidewall is in contact with the contact structure 140.

[0057] When sufficient voltage is supplied to the gate stack 120, the electric field between the gate stack 120 and the contact structure 140 enables the defects between the dielectric layers 150 to trap electrons. Under the action of a high electric field, the regions where electron traps trap electrons may overlap, thereby forming a current channel in the dielectric layer 150. As the current in the gate stack 120 increases, the current channel on the dielectric layer 150 becomes conductive, thereby forming a breakdown. This allows the electrical signal of the gate stack 120 to be conducted to the contact structure 140, and then the electrical signal of the semiconductor structure is extracted through the contact structure 140.

[0058] The dielectric layer 150 is used to isolate the contact structure 140 and the gate stack layer 120, thereby preventing the contact structure 140 and the gate stack layer 120 from directly contacting each other. By breaking down the dielectric layer 150, the gate stack layer 120 and the contact structure 140 can be made conductive, thereby reducing the difficulty of breaking down the electric fuse. By setting the thickness of the dielectric layer 150 to be less than the thickness of the isolation layer 130, the difficulty of breaking down the dielectric layer 150 can be reduced, thereby improving the breakdown sensitivity of the semiconductor structure. It should be noted that the breakdown sensitivity is the difficulty of breakdown. The higher the breakdown sensitivity, the lower the breakdown difficulty, and the lower the breakdown sensitivity, the higher the breakdown difficulty.

[0059] In some embodiments, the material of the dielectric layer 150 can be the same as that of the gate oxide layer 110, which can both be silicon oxide. In another embodiment, the material of the dielectric layer can also be different from that of the gate oxide layer. The material of the dielectric layer can also be other materials that are easier to break down, thereby reducing the breakdown difficulty of the semiconductor structure.

[0060] In some embodiments, the thickness of the dielectric layer 150 may be less than the thickness of the gate oxide layer 110. It is understood that the thinner the layer, the lower the difficulty of breakdown, that is, the easier it is for breakdown to occur at that location. Therefore, by setting the thickness of the dielectric layer 150 to be less than the thickness of the gate oxide layer 110, the probability of breakdown on the dielectric layer 150 can be increased, thereby making the breakdown path of the semiconductor structure from the gate stack layer 120 through the dielectric layer 150 to the contact structure 140, thereby reducing the breakdown difficulty of the semiconductor structure.

[0061] It should be noted that the reference Figure 1 The thickness of dielectric layer 150 is the dimension of dielectric layer 150 in the direction from gate stack 120 toward contact structure 140; Reference Figure 2 The thickness of the dielectric layer 150 located on the sidewalls of the first conductive layer 121, the intermediate layer 122 and the second conductive layer 123 is the dimension of the dielectric layer 150 in the direction perpendicular to the first conductive layer 121 toward the intermediate layer 122; the thickness of the dielectric layer 150 located above the second conductive layer 123 is the dimension of the dielectric layer 150 in the direction of the first conductive layer 121 toward the intermediate layer 122.

[0062] In some embodiments, the thickness of the dielectric layer 150 is less than or equal to 3 nm. It is understood that the smaller the thickness of the dielectric layer 150, the lower the difficulty of breakdown occurring on the dielectric layer 150, and the smaller the thickness of the dielectric layer 150, the lower the current required to break down the dielectric layer. By setting the thickness of the dielectric layer 150 to less than 3 nm, the probability of breakdown on the dielectric layer 150 can be increased. By breaking down the dielectric layer 150, the electrical signal of the gate stack layer 120 can be transmitted to the contact structure 140, which can reduce the breakdown difficulty of the semiconductor structure. In some embodiments, the semiconductor structure further includes a filler layer 180, which is used to fill the semiconductor structure. The filler layer 180 can be patterned to form other structures on the semiconductor structure. The material of the filler layer can be an oxide.

[0063] This embodiment of the disclosure provides a method in which the contact structure 140 is disposed adjacent to the gate stack layer 120, and the thickness of the dielectric layer 150 between the gate stack layer 120 and the contact structure 140 is reduced. This results in the breakdown path of the semiconductor structure being from the gate stack layer 120 through the dielectric layer 150 to the contact structure 140. By controlling the breakdown of the dielectric layer 150 to cause the semiconductor structure to break down, the breakdown difficulty of the entire semiconductor structure can be reduced, and the transmission path of the entire electrical signal can be shortened, thereby reducing the electrical signal loss during the transmission process and improving the performance of the semiconductor structure.

[0064] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. This method can be used to form the semiconductor structure of the foregoing embodiments. The same or corresponding parts can be referred to... Figure 1 and Figure 2 The embodiments described above will not be repeated hereafter. The following will describe in detail another embodiment of the semiconductor structure fabrication method provided in this disclosure, with reference to the accompanying drawings. Figures 3 to 7 This is a schematic diagram of the steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0065] refer to Figure 3 and Figure 4 A substrate 100 is provided, a gate oxide layer 110 is formed on the surface of the substrate 100, a gate stack layer 120 is formed on the gate oxide layer 110, and an isolation layer 130 is formed, the isolation layer 130 at least covering the first sidewall of the gate stack layer 120.

[0066] Specifically, in some embodiments, the gate stack 120 may be a four-layer structure, including a first conductive layer 121, an intermediate layer 122, a second conductive layer 123, and a protective layer 124. The first conductive layer 121 is located on the top surface of the gate oxide layer 110, the intermediate layer 122 is located between the first conductive layer 121 and the second conductive layer 123, and the protective layer 124 is located on the top surface of the second conductive layer 123. In other embodiments, the gate stack 120 may be a single-layer structure. In other embodiments, the gate stack may be formed by stacking other numbers of layers.

[0067] In some embodiments, the isolation layer 130 may include a first isolation layer 131, a second isolation layer 132 and a third isolation layer 133, wherein the first isolation layer 131 covers at least the first sidewall of the gate stack layer 120, and the second isolation layer 132 is located between the first isolation layer 131 and the third isolation layer 133; in other embodiments, the isolation layer may also be a single-layer structure.

[0068] In some embodiments, the method of forming the isolation layer 130 includes: forming an initial isolation layer 160, the initial isolation layer 160 covering the sidewalls and top surface of the gate stack layer 120 and the surface of the substrate 100; patterning the initial isolation layer 160; removing the initial isolation layer 160 located on the second sidewall surface of the gate stack layer 120; and using the remaining initial isolation layer 160 located on the first sidewall surface and top surface of the gate stack layer 120 as the isolation layer 130.

[0069] refer to Figure 3 In some embodiments, the method of forming the initial isolation layer 160 includes: forming a first initial isolation layer 161, the first initial isolation layer 161 covering a first sidewall and a second sidewall of the gate stack layer 120; forming a second initial isolation layer 162, the second initial isolation layer 162 covering the sidewall of the first initial isolation layer 161 and the top surface of the gate stack layer 120; and forming a third initial isolation layer 163, the third initial isolation layer 163 covering the top surface of the second initial isolation layer 162.

[0070] In some embodiments, the material of the third initial insulating layer 163 can be the same as that of the first initial insulating layer 161, both being nitrides. The material of the second initial insulating layer 162 can be an oxide, thus forming a non-non structure. The second initial insulating layer 162 being an oxide layer can improve the insulation performance between the first initial insulating layer 162 and the third initial insulating layer 163. However, since the oxide layer material is relatively soft, the morphology of the formed second initial insulating layer 162 is poor. Therefore, the morphology of the formed second initial insulating layer 162 is improved by forming the first initial insulating layer 161 and the third initial insulating layer 163, which are made of nitride layers.

[0071] In other embodiments, the initial isolation layer 160 may also serve as a mask for the light and heavy doping processes of the substrate 100, thereby controlling the area of ​​the lightly doped and heavily doped regions.

[0072] refer to Figure 4 Graphical initial isolation layer 160 (reference) Figure 3 The initial isolation layer 160 located on the second sidewall surface of the gate stack 120 is removed, leaving the initial isolation layer 160 located on the first sidewall surface and top surface of the gate stack 120 as isolation layer 130. This initial isolation layer 160 is graphically represented as shown in the reference diagram. Figure 3 This provides process space for the subsequent formation of the dielectric layer and contact structure.

[0073] And by controlling the graphical initial isolation layer 160 (reference) Figure 3 The area and position of the protective layer 124 can control the total area and corresponding positions of the subsequently formed dielectric layer and contact structure. In some embodiments, the initial isolation layer 160 (see reference) is graphical. Figure 3 The portion includes the initial isolation layer 160 on the top surface of a portion of the gate stack 120 (reference). Figure 3 ) and the initial isolation layer 160 located on the second sidewall of the gate stack 120 (reference) Figure 3 In other embodiments, a graphical initial isolation layer 160 (see reference 160) is used. Figure 3 The portion includes only the initial isolation layer 160 located on the second sidewall of the gate stack 120 (reference). Figure 3 ).

[0074] In some embodiments, a graphical initial isolation layer 160 (reference) Figure 3 The process also includes a patterned protective layer 124 to expose a portion of the second conductive layer 123, thereby providing a process basis for the subsequent formation of the dielectric layer and contact structure portion located on the second conductive layer.

[0075] In some embodiments, a graphical initial isolation layer (reference) Figure 3 The method includes forming a recess 170, which exposes at least the second sidewall and a portion of the top surface of the gate stack 120, and also exposes the substrate 100. Forming the recess 170, which exposes the second sidewall and a portion of the top surface of the gate stack 120, provides a process basis for subsequently formed dielectric layers and contact structures to be located on the second conductive layer. The position and area of ​​the subsequently formed dielectric layers and contact structures can be controlled by controlling the position and area of ​​the recess 170.

[0076] In other embodiments, the groove may also expose only the second sidewall of the gate stack layer and part of the substrate.

[0077] refer to Figure 5 and Figure 6 A dielectric layer 150 is formed, which at least covers the second sidewall of the gate stack layer 120. The first sidewall and the second sidewall are disposed opposite to each other, and the thickness of the dielectric layer 150 is less than the thickness of the isolation layer 130.

[0078] In some embodiments, forming a dielectric layer 150 includes: depositing dielectric material on the sidewalls and bottom of a recess 170, removing the dielectric material at the bottom of the recess 170, and forming a dielectric layer 150 covering the second sidewall of the gate stack layer 120. By setting the thickness of the dielectric layer 150 to be less than the thickness of the isolation layer 130, and by configuring the dielectric layer 150 adjacent to the gate stack layer 120, the breakdown path of the semiconductor structure can be made to be from the gate stack layer 120 to the dielectric layer 150 and then to the contact structure, which can reduce the breakdown difficulty of the dielectric layer 150 and thus improve the performance of the semiconductor structure.

[0079] In some embodiments, a dielectric material is also deposited on the exposed top surface of the second conductive layer 123. By forming a dielectric layer 150 on the top surface of the second conductive layer 123, a process basis is provided for the subsequent formation of a contact structure above the gate stack layer 120, thereby avoiding direct contact between the contact structure formed on the top surface of the second conductive layer 123 and the second conductive layer 123.

[0080] In some embodiments, the method of forming the dielectric layer 150 may be to form the dielectric layer 150 on the sidewall of the groove 170 by means of atomic layer deposition technology. Atomic layer deposition technology has excellent thickness control performance and the formed dielectric layer 150 has a relatively uniform thickness.

[0081] In some embodiments, before removing the dielectric material located at the bottom of the recess 170, the method further includes: ion implantation of the substrate 100 at the bottom of the recess 170. Ion implantation of the substrate 100 at the bottom of the recess 170 forms the source and drain of the MOS transistor.

[0082] In some embodiments, when ion implantation is performed into the substrate 100, the type of implanted ions can be controlled according to the type of MOS transistor to be formed.

[0083] In some embodiments, the method of forming the dielectric layer 150 may include controlling the thickness of the dielectric layer 150 to be less than the thickness of the gate oxide layer 110. It is understood that the thinner the layer, the lower the difficulty of breakdown, meaning that breakdown is more likely to occur at that location. Therefore, by setting the thickness of the dielectric layer 150 to be less than the thickness of the gate oxide layer 110, the probability of breakdown on the dielectric layer 150 can be increased. By breaking down the dielectric layer 150 to allow the electrical signal of the gate stack layer 120 to be transmitted to the contact structure 140, the breakdown difficulty of the semiconductor structure can be reduced.

[0084] refer to Figure 7A contact structure 140 is formed, which is located at least on the surface of the substrate 100 and is in contact with the surface of the dielectric layer 150.

[0085] In some embodiments, forming the contact structure 140 may include: in the groove 170 (reference) Figure 6 A contact layer 141 is formed at the bottom, and the contact layer 141 is electrically connected to the substrate 100; a barrier layer 142 is formed, which is located on the surface of the dielectric layer 150 and the top surface of the contact layer 141; a conductive layer 143 is formed, which fills the groove 170.

[0086] By forming contact layer 141, the Schottky barrier between contact structure 140 and substrate 100 can be reduced, thereby reducing the contact resistance between contact structure 140 and substrate 100 and improving the response speed of semiconductor structure. Furthermore, the material of contact layer 141 is metal silicide, and the lattice of metal silicide can be well matched with the silicon lattice, thereby reducing defects between contact layer 141 and substrate 100. Compared with directly forming metal as contact structure on the surface of substrate 100, forming contact layer 141 first can reduce the contact resistance between contact structure 140 and substrate 100 and the defects between them, thereby improving the performance of semiconductor structure.

[0087] By forming a barrier layer 142, metal ions from the conductive layer 143 can be prevented from diffusing into the contact layer 141 during ion diffusion. The barrier layer 142 prevents ion diffusion from the conductive layer 143 from contaminating the contact layer 141, thereby improving the stability of the contact layer 141 and thus improving the reliability of the semiconductor structure.

[0088] By forming a conductive layer 143, the conductivity of the contact structure 140 can be improved, the transmission speed of electrical signals in the contact structure 140 can be increased, and thus the performance of the semiconductor structure can be improved.

[0089] In some embodiments, the contact structure 140 overlaps with the projection of the gate stack 120 onto the surface of the substrate 100, and the width of the overlapping portion is less than or equal to 0.1 to 0.5 of the width of the gate stack 120. The more overlapping portions there are, the larger the area that can be broken down between the gate stack 120 and the contact structure 140. However, the more overlapping portions there are, the fewer the protective layer 124 and the isolation layer 130 located on the second conductive layer 123. Consequently, the protective layer 124 and the isolation layer 130 can provide a worse protection effect for the first conductive layer 121, the intermediate layer 122, and the second conductive layer 123. The fewer overlapping portions there are, the better the protection effect that the protective layer 124 and the isolation layer 130 can provide for the first conductive layer 121, the intermediate layer 122, and the second conductive layer 123. By setting the width of the overlapping portion to be less than or equal to 0.1 to 0.5 of the width of the gate stack 120, a certain protection effect is provided while increasing the area that can be broken down between the gate stack 120 and the contact structure 140.

[0090] This disclosure provides a method for fabricating a semiconductor structure. A dielectric layer 150 is formed on the second sidewall of a gate stack layer 120, with the thickness of the dielectric layer 150 being less than the thickness of the isolation layer 130. A contact structure 140 is then formed that contacts the surface of the dielectric layer 150. By placing the contact structure 140 close to the gate stack layer 120 and reducing the thickness of the dielectric layer 150 between the gate stack layer 120 and the contact structure 140, the breakdown path of the semiconductor structure is from the gate stack layer 120 through the dielectric layer 150 to the contact structure 140. By controlling the breakdown of the dielectric layer 150 to cause semiconductor structure breakdown, the breakdown difficulty of the entire semiconductor structure can be reduced, and the transmission path of the entire electrical signal can be shortened, thereby reducing electrical signal loss during transmission and improving the sensitivity of the semiconductor structure.

[0091] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: The substrate, and the gate oxide layer located on the surface of the substrate; A gate stack layer, wherein the gate stack layer is located on the surface of the gate oxide layer; An isolation layer, the isolation layer at least covering a first sidewall of the gate stack layer; A contact structure, wherein the contact structure is located at least on the surface of the substrate; A dielectric layer is located at least between the contact structure and the second sidewall of the gate stack layer, the first sidewall and the second sidewall are disposed opposite to each other, and the thickness of the dielectric layer is less than the thickness of the isolation layer. The isolation layer is also located on a portion of the top surface of the gate stack layer; a portion of the contact structure is located above the gate stack layer.

2. The semiconductor structure according to claim 1, characterized in that, The contact structure overlaps with the projection of the gate stack layer onto the substrate surface, and the width of the overlapping portion is less than or equal to 0.1 to 0.5 of the width of the gate stack layer.

3. The semiconductor structure according to claim 1, characterized in that, The thickness of the dielectric layer is less than the thickness of the gate oxide layer.

4. The semiconductor structure according to claim 1, characterized in that, Part of the contact structure is located within the active region of the substrate.

5. The semiconductor structure according to claim 4, characterized in that, The contact structure includes a contact layer, a barrier layer, and a conductive layer, wherein the barrier layer is located between the contact layer and the conductive layer, and the contact layer is located within the active region.

6. The semiconductor structure according to claim 1, characterized in that, The thickness of the dielectric layer is less than or equal to 3 nm.

7. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, a gate oxide layer is formed on the surface of the substrate, and a gate stack layer is formed on the gate oxide layer; An isolation layer is formed, the isolation layer at least covering the first sidewall of the gate stack layer; A dielectric layer is formed, the dielectric layer at least covering the second sidewall of the gate stack layer, the first sidewall and the second sidewall are disposed opposite to each other, and the thickness of the dielectric layer is less than the thickness of the isolation layer; A contact structure is formed, wherein the contact structure is at least located on the surface of the substrate and is in contact with the surface of the dielectric layer; The method for forming the isolation layer includes: An initial isolation layer is formed, which covers the sidewalls and top surface of the gate stack layer and the surface of the substrate; The initial isolation layer is graphically represented by removing the initial isolation layer located on the second sidewall surface of the gate stack layer, and the remaining initial isolation layer located on the first sidewall surface and top surface of the gate stack layer is used as the isolation layer. The initial isolation layer is graphically represented as follows: A groove is formed, the groove exposing at least the second sidewall and a portion of the top surface of the gate stack layer, and the groove also exposing the substrate; The formation of the dielectric layer includes: depositing dielectric material on the sidewalls and bottom of the groove, removing the dielectric material located at the bottom of the groove, and forming a dielectric layer covering the second sidewall of the gate stack layer; The formation of the contact structure includes: A contact layer is formed at the bottom of the groove, and the contact layer is electrically connected to the substrate; A barrier layer is formed, the barrier layer being located on the surface of the dielectric layer and the top surface of the contact layer; A conductive layer is formed, which fills the groove.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, Before removing the dielectric material located at the bottom of the groove, the method further includes: ion implantation of the substrate at the bottom of the groove.

9. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The method of forming the dielectric layer includes controlling the thickness of the dielectric layer to be less than the thickness of the gate oxide layer.

10. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The contact structure overlaps with the projection of the gate stack layer onto the substrate surface, and the width of the overlapping portion is less than or equal to 0.1 to 0.5 of the width of the gate stack layer.

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