Semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device with high integration. The semiconductor memory device of the embodiments has a laminate, a plurality of bit lines, and a plurality of columnar bodies. The plurality of bit lines includes a first bit line, a second bit line, a third bit line, and a fourth bit line. The plurality of columnar bodies includes a first columnar body, a second columnar body, a third columnar body, a fourth columnar body, a fifth columnar body, a sixth columnar body, a seventh columnar body, and an eighth columnar body. The first columnar body is electrically connected to the first bit line. The second columnar body is electrically connected to the third bit line. The third columnar body is electrically connected to the second bit line. The fourth columnar body is electrically connected to the fourth bit line, and the fifth columnar body is electrically connected to the second bit line. The sixth columnar body is electrically connected to the fourth bit line. The seventh columnar body is electrically connected to the first bit line. The eighth columnar body is electrically connected to the third bit line.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2022-44896 (filed on March 22, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to semiconductor memory devices. Background Technology

[0003] NAND flash memory is known to be a type of flash memory in which memory cells are stacked in three dimensions. Summary of the Invention

[0004] This invention provides a highly integrated semiconductor memory device.

[0005] The semiconductor memory device of the embodiment includes a stack, multiple bit lines, at least one first insulator, at least one second insulator, multiple pillars, and multiple vias. The stack is formed by alternately stacking multiple conductive layers and multiple insulating layers in a first direction. The multiple bit lines extend above the stack along a second direction intersecting the first direction and are spaced apart from each other in a third direction intersecting both the first and second directions. The first insulator extends within the stack along the first and third directions, truncating multiple conductive layers in the second direction. The second insulator extends in both the first and second directions, truncating at least a portion of the uppermost conductive layer in the second direction. The multiple pillars extend in the first direction in adjacent first and second regions between the first and second insulators and between adjacent second insulators, each comprising a semiconductor body. Each of the multiple vias connects any one of the multiple pillars to any one of the multiple bit lines. Multiple bit lines include a first bit line, a second bit line, a third bit line, and a fourth bit line arranged sequentially in the third direction. Multiple pillars include a first pillar, a second pillar, a third pillar, a fourth pillar, a fifth pillar, a sixth pillar, a seventh pillar, and an eighth pillar arranged sequentially in the second direction. The first pillar is configured to overlap with the first bit line when viewed from the first direction. The second pillar is configured to overlap with the third bit line when viewed from the first direction. The third pillar is configured to overlap with the second bit line when viewed from the first direction. The fourth pillar is configured to overlap with the fourth bit line when viewed from the first direction. The fifth pillar is configured to overlap with the second bit line when viewed from the first direction. The sixth pillar is configured to overlap with the fourth bit line when viewed from the first direction. The seventh pillar is configured to overlap with the first bit line when viewed from the first direction. The 8th column is configured to overlap with the 3rd line when viewed from the 1st direction. The 1st column is electrically connected to the 1st line. The 2nd column is electrically connected to the 3rd line. The 3rd column is electrically connected to the 2nd line. The 4th column is electrically connected to the 4th line, and the 5th column is electrically connected to the 2nd line. The 6th column is electrically connected to the 4th line. The 7th column is electrically connected to the 1st line. The 8th column is electrically connected to the 3rd line.

[0006] Furthermore, it is preferable that the first region and the second region are alternately and repeatedly arranged between adjacent first insulators along the second direction.

[0007] Furthermore, it is preferable that the spacing in the second direction between the vias connected to the second and third columns respectively, and the spacing in the second direction between the vias connected to the sixth and seventh columns respectively, are larger than the spacing in the second direction between the vias connected to the first and second columns respectively, the spacing in the second direction between the vias connected to the third and fourth columns respectively, the spacing in the second direction between the vias connected to the fourth and fifth columns respectively, the spacing in the second direction between the vias connected to the fifth and sixth columns respectively, and the spacing in the second direction between the vias connected to the seventh and eighth columns respectively.

[0008] Furthermore, it is preferable that the vias connected to the first and second pillars respectively, the vias connected to the third and fourth pillars respectively, the vias connected to the fourth and fifth pillars respectively, the vias connected to the fifth and sixth pillars respectively, and the vias connected to the seventh and eighth pillars respectively are all of the same size in the second direction.

[0009] In addition, it is preferable that the multiple columnar bodies are arranged at approximately equal intervals when viewed from the first direction. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating the semiconductor memory device and memory controller according to the first embodiment.

[0011] Figure 2 This is a diagram showing an equivalent circuit of a portion of the memory cell array of the semiconductor memory device according to the first embodiment.

[0012] Figure 3 This is a top view showing a portion of the semiconductor memory device according to the first embodiment.

[0013] Figure 4 This is a cross-sectional view showing a portion of a semiconductor memory device according to a modified example of the first embodiment.

[0014] Figure 5 This is a cross-sectional view showing a portion of the semiconductor memory device according to the first embodiment.

[0015] Figure 6 This is a cross-sectional view obtained by magnifying the vicinity of the columnar body of the semiconductor memory device of the first embodiment.

[0016] Figure 7 This is a cross-sectional view obtained by magnifying the vicinity of the columnar body of the semiconductor memory device of the first embodiment and cutting along the conductive layer.

[0017] Label Explanation

[0018] 1. Semiconductor memory device; 2. Memory controller; 10. Memory cell array; 11. Row decoder; 12. Sensing amplifier; 13. Sequencer; 20. Stack-up; 21, 21A, 21B, 21C conductive layers; 22. Insulating layer; 30, 30A, 30B, 30C, 30D, 30E, 30F, 30G, 30H columnar structures; 32. Semiconductor body; 35. Charge storage film; 41. First insulator; 42. Second insulator; BL, BL1, B L2, BL3, BL4 bit lines; BLK block; CP contact; MH memory via; MT memory cell transistor; P1-P7 spacing; SGS select gate line (source side); SGD select gate line (drain side); SL ​​source line; STR string; STRa string (region 1); STRB string (region 2); ST slit; SHE slit; Sub substrate; V1 via; Y1 column 1; Y2 column 2 Detailed Implementation

[0019] Hereinafter, a semiconductor memory device according to an embodiment will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions are labeled with the same reference numerals. Furthermore, repeated descriptions of such components are sometimes omitted. Additionally, in the following description, constituent elements having substantially the same function and configuration are labeled with the same reference numerals. Numbers following the characters in the reference numerals are referenced by reference numerals including the same characters and are used to distinguish elements having the same configuration from each other. When it is not necessary to distinguish elements represented by reference numerals including the same characters from each other, these elements are each referenced by reference numerals including only the characters. The drawings are schematic or conceptual; the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., are not necessarily limited to being the same as in reality.

[0020] In this application, "connection" is not limited to physical connection, but also includes electrical connection. In this application, "parallel," "orthogonal," or "identical" also include cases of "substantially parallel," "substantially orthogonal," or "substantially identical," respectively. In this application, "extending in direction A" means, for example, that the dimension in direction A is larger than the smallest dimension among the dimensions in the X, Y, and Z directions described later. "Direction A" as used herein is any direction.

[0021] First, the X, Y, and Z directions are defined. The X and Y directions are directions that are approximately parallel to the surface of the substrate Sub, which will be described later. The X and Y directions are orthogonal to each other. The Z direction is orthogonal to both the X and Y directions and is a direction away from the substrate Sub. However, these expressions are used for ease of explanation and do not specify the direction of gravity. In this embodiment, the Z direction is an example of a "first direction," the Y direction is an example of a "second direction," and the X direction is an example of a "third direction."

[0022] In the accompanying drawings to be referenced below, for example, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction relative to the surface of the substrate Sub used in the formation of the semiconductor memory device 1. In the top view, some components are appropriately shaded to facilitate observation of the drawings. The shaded lines in the top view are not necessarily related to the material or properties of the components to which the shaded lines are attached. In both the top view and the cross-sectional view, some components such as wiring, contacts, and interlayer insulating films are appropriately omitted for ease of observation of the drawings.

[0023] <1> First Embodiment

[0024] Hereinafter, the semiconductor memory device 1 according to the first embodiment will be described.

[0025] <1-1> Overall Structure of Semiconductor Memory Device 1

[0026] Figure 1 This is a block diagram showing a semiconductor memory device 1 and a memory controller 2. The semiconductor memory device 1 is a non-volatile semiconductor memory device, such as a NAND flash memory. The semiconductor memory device 1 includes, for example, a memory cell array 10, a row decoder 11, a sense amplifier 12, and a sequencer 13.

[0027] The memory cell array 10 includes multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Each BLK block is a non-volatile memory cell transistor MT (refer to...). Figure 2 The memory cell array 10 is a collection of memory cells. It has multiple bit lines and multiple word lines. Each memory cell transistor MT is connected to one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0028] The row decoder 11 selects a block BLK based on the address information ADD received from the external memory controller 2. The row decoder 11 controls the write and read operations of data for the memory cell array 10 by applying the desired voltage to multiple word lines respectively.

[0029] The sense amplifier 12 applies the desired voltage to each bit line based on the write data DAT received from the memory controller 2. The sense amplifier 12 determines the data stored in the memory cell transistor MT based on the voltage of the bit line and sends the determined read data DAT to the memory controller 2.

[0030] The sequencer 13 controls the overall operation of the semiconductor memory device 1 based on the command CMD received from the memory controller 2.

[0031] The semiconductor storage device 1 and storage controller 2 described above can also be combined to form a semiconductor device. Examples of semiconductor devices include memory cards such as SD cards (registered trademark) and SSDs (Solid State Drives).

[0032] <1-2> Circuit structure of memory cell array 10

[0033] Next, the electrical structure of the memory cell array 10 will be described.

[0034] Figure 2 This is a diagram showing the equivalent circuit of a portion of the memory cell array 10. Figure 2 The block BLK contained in the storage cell array 10 is extracted and represented. The block BLK includes multiple (e.g., 4) strings STR0 to STR3.

[0035] Each string STR0 to STR3 is a collection of multiple NAND strings NS. One end of each NAND string NS is connected to any one of the bit lines BL0 to BLm (where m is an integer greater than or equal to 1). The other end of the NAND string NS is connected to the source line SL. Each NAND string NS includes multiple memory cell transistors MT0 to MTn (where n is an integer greater than or equal to 1), a first selection transistor S1, and a second selection transistor S2.

[0036] Multiple memory cell transistors MT0 to MTn are electrically connected in series. Each memory cell transistor MT includes a control gate and a storage layer (e.g., a charge accumulation film) to store data in a non-volatile manner. The memory cell transistor MT causes a change in the state of the storage layer (e.g., accumulating charge in the charge accumulation film) based on the voltage applied to the control gate. The control gate of the memory cell transistor MT is connected to any one of the corresponding word lines WL0 to WLn. The memory cell transistor MT is electrically connected to the row decoder 11 via word line WL.

[0037] The first select transistor S1 in each NAND string NS is connected between multiple memory cell transistors MT0 to MTn and any bit line BL0 to BLm. The drain of the first select transistor S1 is connected to any bit line BL0 to BLm. The source of the first select transistor S1 is connected to the memory cell transistor MTn. The control gate of the first select transistor S1 in each NAND string NS is connected to any select gate line SGD0 to SGD3. The first select transistor S1 is electrically connected to the row decoder 11 via the select gate line SGD. When a predetermined voltage is applied to any one of the select gate lines SGD0 to SGD3, the first select transistor S1 connects the NAND string NS and the bit line BL.

[0038] The second selection transistor S2 in each NAND string NS is connected between the multiple memory cell transistors MT0 to MTn and the source line SL. The drain of the second selection transistor S2 is connected to the memory cell transistor MT0. The source of the second selection transistor S2 is connected to the source line SL. The control gate of the second selection transistor S2 is connected to the select gate line SGS. The second selection transistor S2 is electrically connected to the row decoder 11 via the select gate line SGS. When a predetermined voltage is applied to the select gate line SGS, the second selection transistor S2 connects the NAND string NS and the source line SL.

[0039] Furthermore, the memory cell array 10 can also be other circuit structures besides those described above. For example, the number of each string STR included in each BLK, the number of memory cell transistors MT included in each NAND string NS, and the number of selection transistors STD and STS can also be changed. In addition, the NAND string NS can also include more than one dummy transistor.

[0040] <1-3> Construction of storage cell array 10

[0041] Hereinafter, an example of the construction of the storage cell array 10 in this embodiment will be described.

[0042] Furthermore, in the accompanying drawings referenced below, shaded lines have been appropriately added to the top views for ease of observation. The shaded lines in the top views are not necessarily related to the material or properties of the constituent elements to which the shaded lines are added. In the sectional views, constituent elements such as insulating layers (interlayer insulating films), wiring, and contacts have been appropriately omitted for ease of observation.

[0043] <1-3-1> Planar layout of storage cell array 10

[0044] use Figure 3 An example of the planar layout of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment will be described.

[0045] Figure 3 This is a top view showing a portion of the semiconductor memory device 1 according to the first embodiment. Specifically, Figure 3 This is a top view of a characteristic portion of the cell array region of the storage cell array 10. Figure 3 This is a top view of the laminate 20, with dashed lines representing the bit lines BL1 to BL4 located above the laminate 20 in the Z direction. Figure 3 In the representation, the region corresponding to a block BLK is extracted.

[0046] like Figure 3 As shown, the memory cell array 10 includes multiple slots ST (in Figure 3 The middle part is ST1, ST2) and multiple gaps SHE (in Figure 3 (SHE1 to SHE3 are shown in the image). Each of the multiple slots ST is a groove that penetrates the laminate 20 in the Z direction and distinguishes the laminate 20 in the Y direction. That is, the slot ST extends in both the Z and X directions, and the multiple conductive layers 21 stacked in the Z direction are cut off by the slot ST in the Y direction. Each of the multiple slots SHE extends from the upper surface 20a on the bit line side of the laminate 20 to the middle of the laminate 20. The upper surface 20a is an example of a "first surface". Both the multiple slots ST and the multiple slots SHE extend in the X direction.

[0047] Multiple slots ST are each arranged extending along the X direction and aligned in the Y direction. Multiple slots SHE are arranged between adjacent slots ST in the Y direction. Multiple slots SHE are each arranged extending along the X direction and aligned in the Y direction.

[0048] Specifically, the gap ST, for example, cuts off multiple conductive layers 21 corresponding to the gate electrode, the select gate line SGD, and the select gate line SGS, respectively. In other words, the gap ST extends in the X direction, thereby isolating the multiple conductive layers 21 corresponding to the gate electrode, the select gate line SGD, and the select gate line SGS in the Y direction.

[0049] On the other hand, the gap SHE is provided from the upper surface 20a of the stack 20 to the middle of the stack 20. That is, the gap SHE extends in the Z and X directions, and cuts off at least a portion of the uppermost layer (i.e., the conductive layer 21 closest to the bit line BL) of the plurality of conductive layers 21 in the Y direction. Specifically, for example, the gap SHE is provided up to the position of the conductive layer 21 (conductive layer 21C) corresponding to the select gate line SGD. That is, the gap SHE extends in the X direction, isolating the conductive layer 21 (conductive layer 21C) corresponding to the select gate line SGD in the Y direction.

[0050] The slot ST has a structure in which a first insulator 41, formed of an insulating component, is embedded inside the slot. The slot SHE has a structure in which a second insulator 42, formed of an insulating component, is embedded inside the slot. Furthermore, a conductor may also be embedded in the slot ST, separated by the first insulator 41. This embedded conductor may also be used as a contact portion of the source line SL.

[0051] In the planar layout of the storage cell array 10 described above, each region divided by the slot ST and slot SHE corresponds to a string STR. For example, in Figure 3 In the example shown, the strings STRa and STRB, which extend in the X direction and are divided by gaps SHE1 to SHE3, are arranged in the Y direction. That is, the strings STRa and STRB are adjacent in the Y direction, sandwiched between gaps SHE2. Furthermore, the storage cell array 10 is repeatedly arranged, for example, in the Y direction. Figure 3 The layout is shown below. Here, string STRa is an example of "region 1", and string STRb is an example of "region 2".

[0052] <1-3-2> Construction of the storage cell array 10 in the cell region

[0053] Next, a detailed planar layout of the memory cell array 10 in the cell region of the semiconductor memory device 1 according to the first embodiment will be described. Furthermore, the number of pillars 30, contacts CP, vias V1, and bit lines BL described below is just one example, and this embodiment is not limited to this. That is, the number of contacts CP, vias V1, and bit lines BL in this embodiment can be varied in various ways without departing from the spirit of this embodiment.

[0054] like Figure 3 As shown, the memory cell array 10 includes multiple pillars 30, multiple contacts CP, multiple vias V1, and multiple bit lines BL. Specifically, for the memory cell array 10, each string STR includes, for example, a group consisting of four pillars 30 arranged at different positions in the Y direction, four corresponding contacts CP and four vias V1, and four bit lines BL (BL1 to BL4).

[0055] Multiple columnar bodies 30 each function as, for example, a NAND string NS.

[0056] Multiple columns 30 are set along multiple "columns" and "rows".

[0057] Each "column" of the multiple columnar bodies 30 extends in the Y direction, with two columns positioned between position lines BL1 and BL2, and between position lines BL3 and BL4. Specifically, a first column Y1 is positioned between position lines BL1 and BL2, and a second column Y2 is positioned between position lines BL3 and BL4. Furthermore, in... Figure 3 While some illustrations are omitted, the group of four pillars 30, corresponding four contacts CP, four vias V1, and four bit lines BL (BL1 to BL4) in the memory cell array 10 is sometimes repeatedly arranged, for example, in the X direction. In this case, Figure 3 The first column Y1 and the second column Y2 are set alternately in the X direction.

[0058] Regarding the "row" consisting of multiple columnar bodies 30, extending in the X direction, multiple rows are arranged along the Y direction between the gaps ST. Specifically, in Figure 3 In the example shown, each string STR has 4 rows. Here, for the 4 rows in string STa, in the Y direction, starting from the row closest to the gap ST1, they are sequentially labeled as X1, X2, X3, and X4. For the 4 rows in string STRb, in the Y direction, starting from the row closest to the gap ST1, they are sequentially labeled as X5, X6, X7, and X8. In addition, sometimes the row Xm (m is 1 to 8) is also referred to as "the m-th row" (for example, "the first row" in the case of row X1).

[0059] In the storage cell array 10 of this embodiment, columnar bodies 30 are provided in each row corresponding to any one of the first column Y1 and the second column Y2.

[0060] Multiple columnar bodies 30 extend in the Z direction, for example, each penetrating the laminate 20 in the Z direction. For example, when viewed from above in the Z direction, the multiple columnar bodies 30 are arranged in a zigzag shape in the Y direction. The number of columnar bodies 30 arranged in a zigzag shape in the Y direction is, for example, the same in each string STR. Figure 3 The string STR shown has four columnar bodies 30 arranged in a zigzag pattern in the Y direction. When viewed from above in the Z direction, the columnar bodies 30 are, for example, circles or ellipses.

[0061] Here, in string STRa (i.e., the first region), the columns 30 arranged in a zigzag pattern in the Y direction are respectively referred to as column 1 30A, column 2 30B, column 30C, and column 4 30D. In string STRb (i.e., the second region), the columns 30 arranged in a zigzag pattern in the Y direction are respectively referred to as column 5 30E, column 6 30F, column 7 30G, and column 8 30H.

[0062] In string STRa, columns 30A, 30B, 30C, and 30D are arranged in the Y direction in the order of column 1. In string STRb, columns 30E, 30F, 30G, and 30H are arranged in the Y direction in the order of column 5.

[0063] Specifically, such as Figure 3 As shown, in the case of string STRA, the first column 30A is positioned in the first row of the first column Y1, the second column 30B is positioned in the second row of the second column Y2, the third column 30C is positioned in the third row of the first column Y1, and the fourth column 30D is positioned in the fourth row of the second column Y2. That is, the first column 30A and the third column 30C are configured to overlap with the first bit line BL1 and the second bit line BL2 respectively when viewed from the Z direction, and the second column 30B and the fourth column 30D are configured to overlap with the third bit line BL3 and the fourth bit line BL4 respectively when viewed from the Z direction. Furthermore, the second column 30B is positioned between the first column 30A and the third column 30C in the Y direction, and the fourth column 30D is positioned on the opposite side of the second column 30B relative to the third column 30C in the Y direction.

[0064] On the other hand, in the case of string STRb, the 5th column 30E is located in the 5th row of the 1st column Y1, the 6th column 30F is located in the 6th row of the 2nd column Y2, the 7th column 30G is located in the 7th row of the 1st column Y1, and the 8th column 30H is located in the 8th row of the 2nd column Y2. That is, the 5th column 30E and the 7th column 30G are configured to overlap with the 1st bit line BL1 and the 2nd bit line BL2 respectively when viewed from the Z direction, and the 6th column 30F and the 8th column 30H are configured to overlap with the 3rd bit line BL3 and the 4th bit line BL4 respectively when viewed from the Z direction. In addition, the 6th column 30F is located between the 5th column 30E and the 7th column 30G in the Y direction, and the 8th column 30H is located on the opposite side of the 6th column 30F in the Y direction relative to the 7th column 30G.

[0065] Multiple bit lines BL extend in the Y direction and are arranged in the X direction. Each bit line BL is arranged to overlap with two columns 30 according to each string of STR. Furthermore, the bit line BL electrically connected to any one of the following columns 30A, 30B, 30C, 40D, 50E, 60F, 70G, and 80H is respectively named bit line BL1, bit line BL2, bit line BL3, and bit line BL4. They are arranged in the X direction in the order of bit line BL1, bit line BL2, bit line BL3, and bit line BL4.

[0066] In addition, Figure 3 In the example shown, two bit lines BL are arranged overlapping each column 30. For example, the first column 30A is configured to overlap with both the first bit line BL1 and the second bit line BL2 when viewed from the Z direction. A through hole V1 is provided between one of the two bit lines BL overlapping the column 30 and the column 30. Each column 30 is electrically connected to its corresponding bit line BL via the through hole V1. Specifically, each column 30 is connected to the bit line BL via the through hole V1 located below the bit line BL and a contact portion CP located below the through hole V1.

[0067] Here, in the string STRa, the first column 30A is electrically connected to the first bit line BL1, the second column 30B is electrically connected to the third bit line BL3, the third column 30C is electrically connected to the second bit line BL2, and the fourth column 30D is electrically connected to the fourth bit line BL4.

[0068] On the other hand, in the string STRb adjacent to the string STRa with the gap SHE2 in the Y direction, the 5th column 30E is electrically connected to the 2nd bit line BL2, the 6th column 30F is electrically connected to the 4th bit line BL4, the 7th column 30G is electrically connected to the 1st bit line BL1, and the 8th column 30H is electrically connected to the 3rd bit line BL3.

[0069] Furthermore, as a variation of the first embodiment, such as Figure 4 As shown, the following layout can also be used in the string STRa: the first column 30A is electrically connected to the second bit line BL2, the second column 30B is electrically connected to the fourth bit line BL4, the third column 30C is electrically connected to the first bit line BL1, and the fourth column 30D is electrically connected to the third bit line BL3. In this case, in the string STRb, the fifth column 30E is electrically connected to the first bit line BL1, the sixth column 30F is electrically connected to the third bit line BL3, the seventh column 30G is electrically connected to the second bit line BL2, and the eighth column 30H is electrically connected to the fourth bit line BL4.

[0070] Furthermore, in this embodiment, when the Y-direction spacing (pitch) of the vias V1 corresponding to the first columnar body 30A to the eighth columnar body 30H is defined as pitches P1, P2, P3, P4, P5, P6, and P7, it is preferable that pitches P2 and P6 are larger than pitches P1, P3, P4, P5, and P7. That is, it is preferable that the Y-direction spacing P2 of the vias V1 connected to the second columnar body 30B and the third columnar body 30C, and the Y-direction spacing P6 of the vias V1 connected to the sixth columnar body 30F and the seventh columnar body 30G, are larger than the spacing between the vias V1 corresponding to the other columnar bodies 30. When each columnar body 30 forms a contact portion CP, it is easy for portions of the vias V1 to be close together. Therefore, by increasing the spacing of the vias V1 in the Y direction in the closely spaced portions, it is possible to reduce the possibility of the vias V1 contacting each other (short-circuiting) due to manufacturing errors when each via V1 is fabricated by photolithography, and to improve the integration of the columnar body 30 within a block BLK.

[0071] Furthermore, in this embodiment, the spacing P1 between the vias V1 connected to the first column 30A and the second column 30B, the spacing P3 between the vias V1 connected to the third column 30C and the fourth column 30D, the spacing P4 between the vias V1 connected to the fourth column 30D and the fifth column 30E, the spacing P5 between the vias V1 connected to the fifth column 30E and the sixth column 30F, and the spacing P7 between the vias V1 connected to the seventh column 30G and the eighth column 30H are preferably all of the same size. This further improves the integration of the columns 30 within a single block BLK.

[0072] Furthermore, regarding the arrangement of the plurality of pillars 30, the spacing between adjacent pillars 30 in the X direction may not be the same. However, from the viewpoint of the integration of the plurality of pillars 30, it is preferable that the plurality of pillars 30 be arranged at approximately equal spacing when viewed from the Z direction. Similarly, the spacing between adjacent pillars 30 in the Y direction may also be different, but it is also preferable that the plurality of pillars 30 be arranged at approximately equal spacing in the Y direction. Specifically, the plurality of pillars 30 are preferably arranged with the same spacing in the Y direction and also with the same spacing in the X direction. This further improves the integration of the pillars 30 within a block BLK.

[0073] The detailed planar layout of the memory cell array 10 in the cell region of the semiconductor memory device 1 according to this embodiment has been described above. However, the semiconductor memory device 1 of this embodiment is not limited to... Figure 3The layout shown. The semiconductor memory device 1 of this embodiment may also be a layout in which strings STRa and strings STB are alternately and repeatedly arranged along the Y direction between adjacent gaps ST.

[0074] Furthermore, in the planar layout of the memory cell array 10 described above, the number of slot SHEs arranged between adjacent slots ST can be designed to be arbitrary. The number of strings STR between two adjacent slots ST varies based on the number of slot SHEs arranged between two adjacent slots ST.

[0075] <1-3-3> Cross-sectional structure of the cell region of the memory cell array 10

[0076] Next, use Figure 5 An example of the cross-sectional structure of the cell region of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment will be described.

[0077] Figure 5 It is along Figure 3 The cross-sectional view along the CC line shows an example of the cross-sectional structure of the cell region of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment.

[0078] The memory cell array 10 has a substrate Sub, a source line SL, a stack 20, multiple pillars 30, multiple contacts CP, multiple vias V1, and multiple bit lines BL.

[0079] The substrate Sub is, for example, a silicon substrate. On the substrate Sub, for example, a cell array region and a peripheral region of the memory cell array 10 are formed.

[0080] The source line SL is disposed on the substrate Sub. The source line SL is formed of a conductor or a semiconductor. The source line SL is, for example, a p-type semiconductor. The source line SL extends in the X and Y directions.

[0081] The laminate 20 has multiple conductive layers 21 and multiple insulating layers 22 in the Z direction. The conductive layers 21 and insulating layers 22 are stacked alternately. The multiple conductive layers 21 extend in both the X and Y directions, respectively. The multiple insulating layers 22 extend in both the X and Y directions, respectively. The conductive layers 21 are, for example, metals or semiconductors. The conductive layers 21 are, for example, polycrystalline silicon doped with tungsten or other impurities. The number of conductive layers 21 is arbitrary.

[0082] The conductive layer 21 is functionally divided into three parts.

[0083] The conductive layer 21A is located closest to the source line SL among the multiple conductive layers 21. The conductive layer 21A can also be multilayered. The conductive layer 21A functions, for example, as the select gate line SGS connected to the second select transistor S2.

[0084] Conductive layer 21B is located next to conductive layer 21A and close to the source line SL among multiple conductive layers 21. Conductive layer 21B is connected to word line WL. Conductive layer 21B functions as the gate electrode of memory cell transistor MT. Conductive layer 21B can also be multiple layers.

[0085] Conductive layer 21C is a conductive layer among multiple conductive layers 21, excluding conductive layers 21A and 21B. Conductive layer 21C is, for example, a conductive layer extending from the stack 20. Conductive layer 21C functions, for example, as a select gate line SGD connected to the first select transistor S1.

[0086] An insulating layer 22 is located between the conductive layer 21 and the source line SL, and between adjacent conductive layers 21 in the Z direction. The insulating layer 22 comprises, for example, silicon oxide. The insulating layer 22 insulates adjacent conductive layers 21 from each other. The number of insulating layers 22 is determined by the number of conductive layers 21.

[0087] Bit line BL is disposed above the uppermost conductive layer 21 (conductive layer 21C) across the contact portion CP and the via V1. Bit line BL is formed on a line extending along the Y direction. Bit line BL contains, for example, copper (Cu).

[0088] Multiple columnar bodies 30 are respectively arranged extending along the Z direction, penetrating the laminate 20, with their bottoms contacting the source line SL.

[0089] Figure 6 This is a cross-sectional view obtained by magnifying the vicinity of the columnar body 30 according to the first embodiment. Figure 7 This is a cross-sectional view obtained by cutting along the conductive layer 21 near the columnar body 30 according to the first embodiment. Figure 6 The cross-section is obtained by cutting the columnar body 30 with the YZ plane. Figure 7 The cross-section is obtained by cutting the columnar body 30 with the XY plane. The columnar body 30 is located within the storage hole MH formed in the laminate 20.

[0090] The columnar body 30 has a core 31, a semiconductor body 32, and a storage film 33. Inside the storage hole MH, the core 31, semiconductor body 32, and storage film 33 are arranged sequentially from the inside.

[0091] Core 31 extends in the Z direction and is columnar. Core 31 may contain, for example, silicon oxide. Core 31 is located inside semiconductor body 32.

[0092] The semiconductor body 32 extends in the Z direction. The semiconductor body 32 is a bottomed cylindrical shape. The semiconductor body 32 covers the outer surface of the core 31. The semiconductor body 32 may contain silicon, for example, polycrystalline silicon obtained by crystallizing amorphous silicon. The semiconductor body 32 serves as the channel for the first selection transistor S1, the memory cell transistor MT, and the second selection transistor S2. The channel is the flow path for charge carriers between the source and drain sides.

[0093] The storage film 33 extends in the Z direction. The storage film 33 covers the outer surface of the semiconductor body 32. The storage film 33 is located between the inner surface of the storage via MH and the outer surface of the semiconductor body 32. The storage film 33 includes, for example, a tunnel insulating film 34, a charge storage film 35, and a cover insulating film 36. These are located near the semiconductor body 32 in the order of tunnel insulating film 34, charge storage film 35, and cover insulating film 36.

[0094] The tunnel insulating film 34 is located between the charge storage film 35 and the semiconductor substrate 32. The tunnel insulating film 34 may comprise, for example, silicon oxide or silicon oxide and silicon nitride. The tunnel insulating film 34 acts as a potential barrier between the semiconductor substrate 32 and the charge storage film 35.

[0095] A charge storage film 35 is located between each conductive layer 21 and the insulating layer 22 and tunnel insulating film 34. The charge storage film 35 may contain, for example, silicon nitride. The various intersections of the charge storage film 35 and the multiple conductive layers 21 function as transistors. The storage cell transistor MT retains data by the presence or absence of charge, or the amount of charge stored, in the intersections (charge storage sections) of the charge storage film 35 and the multiple conductive layers 21. The charge storage section is located between each conductive layer 21 and the semiconductor body 32, and is surrounded by an insulating material.

[0096] An insulating film 36 is located, for example, between each insulating layer 22 and the charge storage film 35. The insulating film 36 comprises, for example, silicon oxide. The insulating film 36 protects the charge storage film 35 from etching during processing. The insulating film 36 may be absent or may remain partially between the conductive layer 21 and the charge storage film 35 as a barrier insulating film.

[0097] In addition, such as Figure 6As shown, barrier insulating films 21a and barrier films 21b may also be present between each conductive layer 21 and the insulating layer 22, and between each conductive layer 21 and the storage film 33. The barrier insulating film 21a suppresses back-tunneling, a phenomenon where charge returns from the conductive layer 21 to the storage film 33. The barrier film 21b improves the adhesion between the conductive layer 21 and the barrier insulating film 21a. The barrier insulating film 21a may be, for example, a laminated film consisting of a silicon oxide film, a metal oxide film, and multiple insulating films. An example of a metal oxide is aluminum oxide. The barrier film 21b, for example, when the conductive layer 21 is tungsten, may be a laminated film consisting of titanium nitride, titanium nitride, and titanium.

[0098] The contact portion CP and the via V1 are contact plugs that electrically connect the pillar 30 and the bit line BL. The contact portion CP and the via V1 are located within an interlayer insulating layer (not shown). The contact portion CP and the via V1 penetrate this interlayer insulating layer in the Z direction. The contact portion CP and the via V1 contain a conductive material. The contact portion CP and the via V1 are, for example, tungsten.

[0099] Via V1 electrically connects contact CP and bit line BL. Viewed from above in the Z direction, via V1 is smaller than contact CP, and most of it is enclosed within contact CP. The geometric center of via V1 is offset from, for example, the geometric center of contact CP. Furthermore, Figure 3 , Figure 4 The distances P1, P2, P3, P4, P5, P6, and P7 in the Y direction between the vias V1 corresponding to the first column 30A to the eighth column 30H respectively represent the distances that connect the geometric centers of the vias V1 to each other.

[0100] <1-4> Effects

[0101] As described in the semiconductor memory device 1 of this embodiment, by realizing the interlocking gap SHE in adjacent strings of STRs in the Y direction (in Figure 3 The optimization of the configuration position of each via V1 in the series STRa and STRb prevents the vias V1 from contacting each other (short circuit) during the photolithography fabrication of each via V1, and improves the integration of the pillars 30 within a block BLK. As a result, the integration of the memory transistor MT can be improved.

[0102] Furthermore, in the semiconductor memory device 1 according to the first embodiment, each column 30 is not merely a nominal unit, but can function as a recording area. That is, the columns 30 that function as storage areas are arranged closely together, resulting in excellent integration of the semiconductor memory device 1 according to the first embodiment.

[0103] Several embodiments have been described above, but the embodiments are not limited to the examples described above. For example, the storage layer film may also be the ferroelectric film contained in a FeFET (Ferroelectric FET) memory that stores data by polarization direction. The ferroelectric film is, for example, formed of hafnium oxide.

[0104] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and likewise within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device, comprising: A laminate formed by alternately stacking multiple conductive layers and multiple insulating layers in a first direction; Multiple bit lines extend above the stack along a second direction intersecting the first direction and are spaced apart from each other in a third direction intersecting the first and second directions; At least one first insulator extends within the laminate along the first and third directions and truncates the plurality of conductive layers in the second direction; At least one second insulator extending in the first direction and the second direction, wherein at least a portion of the uppermost of the plurality of conductive layers is truncated in the second direction; A plurality of columnar bodies, extending in the first direction in each of the regions between the first insulator and the second insulator and in adjacent regions between the second insulators, in adjacent first and second regions, each comprising a semiconductor body; as well as Multiple vias connect each of the multiple columnar bodies to any one of the multiple bit lines. The plurality of bit lines includes a first bit line, a second bit line, a third bit line, and a fourth bit line arranged sequentially in the third direction. The plurality of columnar bodies includes a first columnar body, a second columnar body, a third columnar body, a fourth columnar body, a fifth columnar body, a sixth columnar body, a seventh columnar body, and an eighth columnar body arranged sequentially in the second direction. The first columnar body is configured to overlap with the first position line when viewed from the first direction. The second column is configured to overlap with the third position line when viewed from the first direction. The third column is configured to overlap with the second position line when viewed from the first direction. The fourth column is configured to overlap with the fourth position line when viewed from the first direction. The fifth column is configured to overlap with the second position line when viewed from the first direction. The sixth column is configured to overlap with the fourth position line when viewed from the first direction. The seventh column is configured to overlap with the first position line when viewed from the first direction. The eighth column is configured to overlap with the third position line when viewed from the first direction. The first columnar body is electrically connected to the first position line. The second columnar body is electrically connected to the third line. The third columnar body is electrically connected to the second line. The fourth column is electrically connected to the fourth position line. The fifth column is electrically connected to the second line. The sixth column is electrically connected to the fourth wire. The seventh column is electrically connected to the first line. The eighth column is electrically connected to the third line.

2. The semiconductor memory device according to claim 1, Between adjacent first insulators, the first region and the second region are alternately and repeatedly arranged along the second direction.

3. The semiconductor memory device according to claim 1 or 2, The spacing in the second direction between the vias connected to the second and third columns respectively, and the spacing in the second direction between the vias connected to the sixth and seventh columns respectively, are larger than the spacing in the second direction between the vias connected to the first and second columns respectively, the spacing in the second direction between the vias connected to the third and fourth columns respectively, the spacing in the second direction between the vias connected to the fourth and fifth columns respectively, the spacing in the second direction between the vias connected to the fifth and sixth columns respectively, and the spacing in the second direction between the vias connected to the seventh and eighth columns respectively.

4. The semiconductor memory device according to claim 1 or 2, The plurality of vias are configured such that the spacing in the second direction between the vias connected to the first column and the second column, the spacing in the second direction between the vias connected to the third column and the fourth column, the spacing in the second direction between the vias connected to the fourth column and the fifth column, the spacing in the second direction between the vias connected to the fifth column and the sixth column, and the spacing in the second direction between the vias connected to the seventh column and the eighth column are all of the same size.

5. The semiconductor memory device according to claim 1 or 2, Viewed from the first direction, the plurality of columnar bodies are arranged at approximately equal intervals.

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