An extensible layout cell, multi-bit structure and flip chip

Abstract

The application discloses an extensible layout unit, a multi-bit structure and a flip chip, and belongs to the field of quantum chip manufacturing. The extensible layout unit comprises a first capacitor plate and a second capacitor plate which are spaced apart from each other. The extensible layout unit can further comprise two Josephson junctions connected in parallel between the first capacitor plate and the second capacitor plate. The Josephson junctions are configured with a reading cavity coupled thereto, and the reading cavity is arranged close to but not in contact with the second capacitor plate. Based on the design of the two capacitor plates, when the extensible layout unit is expanded, the multiple reading cavities can be arranged in a concentrated manner, so that the wiring difficulty during bit expansion is reduced, and the design and manufacturing efficiency are improved.

Description

Technical Field

[0001] This application belongs to the field of quantum information, especially the field of quantum chip manufacturing. In particular, this application relates to a scalable layout unit, a multi-bit structure, and a flip chip. Background Technology

[0002] In superconducting quantum chips, the number of qubits determines the chip's performance in quantum computing. Therefore, increasing the number of qubits in a chip can improve its capabilities. However, since qubits require various corresponding operational structures, introducing more qubits into the chip necessitates configuring more operational structures, making the limited chip space more crowded and leading to a trend towards larger chip sizes. In current superconducting quantum chip designs, expanding the number of qubits increases the difficulty of laying out the various operational structures, making it difficult to efficiently further increase the number of qubits on the chip. Summary of the Invention

[0003] This application provides an example of a scalable layout cell, a multi-qubit structure, and a flip chip. This approach optimizes the design of the capacitor structure within the qubit by dividing it into two separate, independent parts, allowing the resulting scalable layout cell to be configured with corresponding readout structures. Therefore, the scalable layout cell is utilized to expand the formation of multi-qubit structures and flip chips, and it provides wiring convenience for the operational structures of the qubits, such as readout components, while integrating more qubits.

[0004] The solution presented in this application is implemented through the following steps.

[0005] In the first aspect, an example of this application proposes a scalable layout unit.

[0006] This scalable layout cell defines a reference position and has three capacitor arms that radiate outwards from the reference position.

[0007] This scalable layout unit includes:

[0008] The first capacitor plate is used to provide one of the capacitor arms;

[0009] A second capacitor plate spaced apart from the first capacitor plate, the two parts of the second capacitor plate connected to each other are used to provide the remaining two capacitor arms.

[0010] In this scalable layout unit, a first capacitor plate and a second capacitor plate, connected together by Josephson junctions, can form qubits. By configuring the distribution of the capacitor arms provided by the first and second capacitor plates, this scalable layout unit can couple and expand qubits through the capacitor arms to form a multi-qubit structure.

[0011] By arranging the first and second capacitor plates alternately, the size of the capacitor arm can be optimized. Therefore, when performing qubit coupling expansion, the operation structures (such as read cavities) of multiple adjacent qubits can be centrally arranged in the expanded multi-qubit structure, thereby avoiding overly dispersed read cavities and reducing the wiring difficulty of the read cavities of each bit in the multi-qubit structure.

[0012] According to some examples of this application, the scalable layout unit also includes: a Josephson junction group, or the scalable layout unit also includes a Josephson junction and a group readout cavity.

[0013] The Josephson junction group is connected in parallel between the first capacitor plate and the second capacitor plate. The Josephson junction group includes a first Josephson junction located at a reference position, wherein the first upper superconductor of the first Josephson junction is connected to the first capacitor plate, and the first lower superconductor is connected to the second capacitor plate; the Josephson junction group also includes a second Josephson junction located at a reference position, wherein the second upper superconductor of the second Josephson junction is connected to the first capacitor plate, and the second lower superconductor is connected to the second capacitor plate.

[0014] The read cavity is positioned close to, but not in contact with, the connection of the remaining two capacitor arms and is coupled to the Josephson junction.

[0015] In a second aspect, examples of this application propose a multi-bit structure. It includes at least two of the aforementioned scalable layout cells, and adjacent scalable layout cells are coupled to each other, the coupling including a first coupling mode, a second coupling mode, or a third coupling mode;

[0016] The first coupling method is achieved through the cooperation between the capacitor arms provided by the second capacitor plate in the expandable layout unit;

[0017] The second coupling method is achieved through the cooperation between the capacitor arms provided by the first capacitor plate in the expandable layout unit;

[0018] The third coupling mode is achieved through the cooperation between capacitor arms provided by the first capacitor plate in the expandable layout unit, and the cooperation between second capacitor arms provided by the second capacitor plate.

[0019] In a third aspect, examples of this application present a scalable layout unit.

[0020] The scalable layout unit includes six qubits distributed in a hexagonal pattern and located at the six vertices respectively, the six qubits being coupled sequentially to each other, and six readout cavities located within the inner region enclosed by the hexagon, with the six qubits and six readout cavities being coupled one-to-one;

[0021] Each qubit includes a superconducting quantum interference device, and a first capacitor island and a second capacitor island spaced apart from each other;

[0022] The second capacitor island has two capacitor elements that are dispersed on both sides of the trajectory extending from the first capacitor island and connected to each other.

[0023] One end of the superconducting quantum interference device is connected to the first capacitor island, and the other end is connected to the junction of the two capacitor elements;

[0024] Two adjacent qubits are coupled through adjacent capacitive elements.

[0025] In a fourth aspect, the examples provided in this application provide a multi-bit structure derived from scalable layout units, the multi-bit structure comprising at least three scalable layout units;

[0026] All scalable layout cells are extended in a honeycomb pattern, and adjacent scalable layout cells are coupled through their respective first capacitor islands. Three adjacent scalable layout cells enclose an annular outer region outside the inner region.

[0027] In a fifth aspect, an example of this application describes a flip chip. It includes:

[0028] The first chip has the aforementioned multi-bit structure;

[0029] The second chip has a flux control line and a drive control line. The flux control line is configured to work with a superconducting quantum interference device to control the frequency of the qubits, and the drive control line is configured to work with the first capacitor island to control the transitions of the qubits.

[0030] The second chip is layered and positioned opposite the first chip to align the control lines with the external area.

[0031] In a sixth aspect, examples of this application present a layout design method for multi-bit structures that improves space utilization in a chip.

[0032] The map design methodology includes:

[0033] The qubit is configured with two separate capacitor islands and a superconducting quantum interference device connected at both ends between the two capacitor islands. The qubit has one capacitor arm provided by one of the capacitor islands and two capacitor arms provided by the other capacitor island and integrally constructed, so that the qubit has a trident-shaped structure.

[0034] A readout unit is positioned at the connection point of two adjacent capacitor arms, and the readout unit is coupled to the bit cell.

[0035] Using qubits and readout units as basic units, at least two basic units are extended and arranged, and the qubits in two adjacent basic units are coupled through a capacitor arm.

[0036] Beneficial effects:

[0037] In the example of this application, the scalable layout cells are radially distributed based on the reference position of the Josephson junction defining the qubit by configuring the capacitor arms of the capacitor plates. This allows the scalable layout cells to be expanded according to the arrangement of each capacitor arm. Furthermore, the capacitors constituting the qubit are configured with two spaced-apart first and second capacitor plates, thus the size of the capacitor arms can be specifically customized. Therefore, during bit expansion, more space is provided to centrally configure the bit operation structures (e.g., readout cavity structures for reading bit states) corresponding to the qubits (configured by the corresponding capacitor plates and Josephson junctions) in multiple adjacent scalable layout cells. This makes these bit operation structures, such as readout cavities, easier to wire and easier to manufacture. Attached Figure Description

[0038] To illustrate this more clearly, the accompanying drawings used in the description will be briefly introduced below.

[0039] Figure 1 This is a schematic diagram of the structure of a quantum bit on a quantum chip in related technologies;

[0040] Figure 2 This is an example layout structure of a multi-bit system with six bits (each bit having a single capacitor component);

[0041] Figure 3 It shows Figure 2 Example layout structure of bit structure in multi-bit system;

[0042] Figure 4 This is an example layout structure for the scalable layout unit in this application.

[0043] Figure 5 It shows Figure 4An example layout structure of bit structures in an expandable layout cell;

[0044] Figure 6 For based on Figure 5 An example layout structure with a coupler configured in the scalable layout cell;

[0045] Figure 7 For based on Figure 5 An example layout structure with two couplers configured in an expandable layout cell;

[0046] Figure 8 This is an example layout structure based on a multi-bit structure (with six bits) formed by six scalable layout units in this application.

[0047] Figure 9 This is an example layout structure in this application, which is based on a multi-bit structure (with six bits) formed by six scalable layout cells and is configured with a read bus and a coupler.

[0048] Figure 10 This is an example layout structure of another multi-bit system in this application.

[0049] Figure 11 This is a flowchart illustrating the layout design method for multi-bit structures that improve space utilization in chips, as shown in the application example.

[0050] Figure 12 This is a flowchart illustrating another design method for improving the space utilization of multi-bit structures in the chip, as shown in the application example.

[0051] Explanation of reference numerals in the attached figures: 101 - bit; 102 - first coupling structure; 103 - readout structure; 104 - second coupling structure; 201 - capacitor; 202 - superconducting quantum interference device; 300 - scalable layout unit; 301 - first capacitor plate; 3011 - first capacitor arm; 302 - second capacitor plate; 3021 - second capacitor arm; 3022 - third capacitor arm; 303 - Josephson junction group; 3031 - first Josephson junction; 3032 - second Josephson junction; 304 - readout cavity; 305 - coupler; 400 - six-bit structure; 401 - readout bus. Detailed Implementation

[0052] As mentioned earlier, the number of qubits in a superconducting quantum chip is directly related to the chip's performance in performing quantum computing. However, given the characteristics of superconducting quantum chips, integrating more qubits inevitably increases the space occupied by the qubits on the chip. Furthermore, each qubit requires corresponding operational components, such as readout and control structures. Therefore, integrating more qubits within a limited chip size becomes more difficult, for example, in terms of effectively correlating multiple qubits (e.g., high-availability coupling); and in terms of not significantly increasing the complexity of configuring the operational components of the qubits (e.g., layout design complexity).

[0053] In superconducting quantum chips, a typical method for expanding qubits is to distribute multiple qubits in a one-dimensional chain, and then achieve effective correlation between the qubits by sequentially coupling two directly adjacent qubits. Figure 1 Take the Transmon qubit as an example. When multiple qubits undergo one-dimensional linear expansion, adjacent qubits are coupled through one arm of their respective cross-shaped capacitors Cq. The curved readout resonant cavity structure engages with the other arm of the cross-shaped capacitor Cq, and the xyz control lines engage with the remaining arms of the cross-shaped capacitor Cq. Therefore, these operational structures can be arranged in the upper and lower parts of the one-dimensional chain extension trajectory of the qubits.

[0054] However, when multiple qubits are expanded in two dimensions, they can be configured into lattice points in a crisscrossing network. It is known that expanding qubits in two dimensions makes the layout of various operational structures of the qubits more difficult, because the usable space on the chip surface is squeezed due to the complex layout of the qubits based on two-dimensional expansion. Therefore, it may be necessary to optimize the structure of the qubits and their expansion methods.

[0055] exist Figure 2 In the illustrated six-bit unit, the six bits 101 are arranged in a hexagonal structure, and adjacent bits are coupled to each other through a first coupling structure 102. Two six-bit units can be coupled to each other through a second coupling structure 104. Simultaneously, two read structures 103 are used in conjunction with this six-bit unit.

[0056] Where a single bit 101 has as follows Figure 3 The structure shown has a capacitor 201 and a superconducting quantum interference device (QFID) 202 connected to it. The capacitor 201 has a trident-shaped structure, thus having three interconnected branches. The superconducting QFID 202 consists of two Josephson junctions (not shown). One end of the superconducting QFID 202 is connected to the capacitor 201, and the other end is grounded.

[0057] Please refer to it again. Figure 2 In this six-bit unit, two read structures 103 are configured within the hexagonal region formed by the six bits. The corresponding read structures 103 for the other four bits need to be configured in other spaces after expanding from the six-bit unit, or configured in other ways.

[0058] Therefore, combining Figure 2 and Figure 3 When the structure shown is used for bit expansion, it will be quite difficult to allocate read structure 103 to these bits, or it may require a special structural design, which may bring additional costs; although in such a scheme, the connectivity between bits can be increased by using a capacitor with three branches for expansion.

[0059] Based on this understanding, the inventors propose a novel bit extension scheme in this application. In this scheme, the bits are extended, thus improving the ease of configuring the read structure.

[0060] One important improvement was the adjustment of the capacitor's structure.

[0061] by Figure 3 The bit shown has a three-pronged capacitor connected to each other to form a single structure. One end of the superconducting quantum interference device is connected to the capacitor, while the other end is grounded.

[0062] Based on this, the inventor designed the capacitor as two separate parts, rather than... Figure 3 The capacitor 201 is constructed as a separate component. Furthermore, corresponding to this (the capacitor is designed as two separate components), the inventors can adjust the configuration of the superconducting quantum interference device (QFID) and make related adaptive adjustments to other components. Through such adjustments, when bits are expanded, the readout structures corresponding to the bits used for acquiring bit states during quantum computing can be configured more centrally. That is, when bits are expanded in the chip, the bit structure and its associated operational structures have higher chip space utilization. In addition to these benefits, it also exhibits a certain degree of noise immunity, thus facilitating bit operations and improving operation fidelity.

[0063] The method of this application will be described in detail below with reference to the accompanying drawings.

[0064] As is known, the fabrication of superconducting quantum chips involves the design and implementation of layout structures. Considering the various components within a superconducting quantum chip and the various operational structures corresponding to qubits, the layout design becomes increasingly complex as the number of integrated qubits increases. Therefore, in the example presented in this application, the inventors propose a scheme for integrating multiple qubits within a chip through expansion.

[0065] Therefore, a scalable layout unit is provided accordingly. In the chip design layout, this scalable layout unit can expand the number of bits through regular arrangement, and can also be expanded in two dimensions.

[0066] To facilitate the positioning and clear articulation of various structures within the scalable layout unit, a reference position can be defined within the scalable layout unit during its design. Based on this, the scalable layout unit 300 has three capacitor arms radiating outwards from the reference position. (See reference...) Figure 4 The three capacitor arms can be arranged roughly in a ring at 120-degree intervals, that is, equally spaced within a 360-degree range; or, the angles can be adjusted appropriately, for example, the angles between any two adjacent capacitor arms are not equal.

[0067] See the example. Figure 4 The scalable layout unit includes a first capacitor plate 301, a second capacitor plate 302, a Josephson junction 303, and a readout cavity 304. The Josephson junction can form a superconducting quantum interference device (capable of controlling bits via flux), while the first capacitor plate 301, the second capacitor plate 302, and the Josephson junction 303 can be combined to form qubits.

[0068] In the layout unit, the first capacitor plate 301 provides one of the three capacitor arms, referred to simply as the first capacitor arm 3011. The second capacitor plate 302 provides the remaining two capacitor arms, referred to simply as the second capacitor arm 3021 and the third capacitor arm 3022; these remaining two capacitor arms are connected to each other, i.e., they are a single integrated structure. Furthermore, the first capacitor plate and the second capacitor plate are spaced apart from each other, therefore they are two independent components, and there is no direct physical structural connection between them except for the Josephson junction. Figure 5 As shown.

[0069] In such an example, the capacitor arm provided by the first capacitor plate can extend vertically, while the two capacitor arms provided by the second capacitor plate are distributed and extended roughly on the left and right sides of the capacitor arm of the first capacitor plate, thus forming equal or unequal included angles adjacent to each other.

[0070] As described above, the Josephson junction group (which is approximately located at the reference position) can form a superconducting quantum interference device, and therefore, it has a first Josephson junction and a second Josephson junction (which may be one of each; or two or more of the same or different number). The first Josephson junction and the second Josephson junction are connected in parallel between the first capacitor plate and the second capacitor plate.

[0071] The Josephson junction has a roughly sandwich structure, generally consisting of two superconductors (which can be described as an upper superconductor and a lower superconductor, respectively) and a barrier layer between the two superconductors. Therefore, as an example of parallel Josephson junctions, the first upper superconductor of the first Josephson junction at the reference position is connected to the first capacitor plate, and the first lower superconductor is connected to the second capacitor plate; simultaneously, the second upper superconductor of the second Josephson junction at the reference position is connected to the first capacitor plate, and the second lower superconductor is connected to the second capacitor plate. The connections are, for example, via wire bonding.

[0072] To read the quantum chip from the qubits, the readout cavity is located close to the second capacitor plate, and more specifically, close to the junction of the two capacitor arms provided by the second capacitor plate. However, the readout cavity does not contact the junction of these two capacitor arms. Therefore, this readout cavity can be coupled to the Josephson junction, i.e., capacitively coupled to the qubits.

[0073] based on Figure 3 The layout cells shown can achieve bit expansion through coupling between the first capacitor plates of different cells. Alternatively, bit expansion can be achieved through coupling between the second capacitor plates of different cells.

[0074] Besides direct bit coupling via capacitor plates, other coupling structures can also be used. For example, during bit expansion, a resonant cavity, coupler (or qubit) can be placed between two mating capacitor plates to facilitate coupling.

[0075] like Figure 6 and Figure 7 As shown, coupler 305 is configured with a frequency-tunable qubit. This frequency-tunable qubit has a capacitance (…). Figure 6 The system consists of a capacitor (which has two parts that are far apart but connected to each other) and a superconducting quantum interference device (QFID) with one end connected to the capacitor and the other end grounded; that is... Figure 6 and Figure 7 The structure of the capacitor in the coupler can be found in [reference]. Figure 2The connector can be a similar structure to the first coupling structure 102 or the second coupling structure 104. In different examples, the connector can be implemented as a fixed-frequency qubit; or, the connector can be a frequency-tunable qubit. Figure 6 and Figure 7 In this context, the connector is a frequency-tunable qubit.

[0076] For the configuration of couplers in a layout cell, for example, one coupler can be set in either the first capacitor plate or the second capacitor plate, or both of them; typically, couplers can be set in any one, two, or three of the three capacitor arms formed by the two capacitor plates of the layout cell.

[0077] Therefore, it can be understood that in some examples, of the three capacitor arms formed by the two capacitor plates of a layout cell, one of the capacitor arms is coupled with a connector at its end furthest from the reference position, and this connector is configured to couple with a first capacitor plate in another scalable layout cell. Alternatively, in other examples, either one or both of the remaining two capacitor arms are coupled with a connector, and this connector is configured to couple with a second capacitor plate in another scalable layout cell.

[0078] As an application example of the aforementioned scalable layout unit, a multi-bit structure can also be disclosed. This multi-bit structure has at least two scalable layout units. As described above, the number of bits in the multi-bit structure is consistent with, i.e., equal to, the number of scalable layout units.

[0079] The coupling method of the scalable layout units can be freely selected according to actual needs and the number of scalable layout units. For example, the coupling modes of two adjacent scalable layout units include a first coupling mode, a second coupling mode, or a third coupling mode. The first coupling mode is achieved through the interaction between the capacitor arms provided by the second capacitor plate in the scalable layout unit. The second coupling mode is achieved through the interaction between the capacitor arms provided by the first capacitor plate in the scalable layout unit. The third coupling mode is achieved through the interaction between the capacitor arms provided by the first capacitor plate and the interaction between the second capacitor arms provided by the second capacitor plate in the scalable layout unit.

[0080] exist Figure 8 In this design, six scalable layout units are used. Figure 6 The structure consists of a six-bit multi-bit array (as shown). Adjacent scalable layout units are coupled via capacitor arms provided by a second capacitor plate and coupled by a coupler in the form of a frequency-tunable qubit.

[0081] In other examples, the scalable layout unit can also be implemented as Figure 8 The structure shown, and therefore, the scalable layout cell includes six qubits arranged in a hexagonal pattern and located at each of the six vertices, wherein the six qubits are coupled sequentially adjacent to each other. The scalable layout cell has six readout cavities located within an inner region enclosed by the hexagons, and the six qubits are coupled one-to-one with the six readout cavities;

[0082] Each qubit comprises a superconducting quantum interference device (SQUID) and a first and a second capacitor island spaced apart from each other. The second capacitor island has two capacitor elements (as described above, two capacitor arms) that are dispersed and connected to each other on either side of the trajectory extending from the first capacitor island. One end of the SQUID is connected to the first capacitor island, and the other end is connected to the junction of the two capacitor elements. Based on this structure, when the six qubits are coupled sequentially adjacent to each other, adjacent qubits are coupled through adjacent capacitor elements.

[0083] Therefore, adjacent qubits in these six qubits are coupled to each other via a coupler. In other words, the scalable layout cell also has a coupler that couples to the qubits via capacitive elements. Thus, the coupler is located between two adjacent capacitive elements. And in some examples, the coupler is frequency-tunable, thereby making the coupling strength between two adjacent qubits coupled to each other via the coupler adjustable.

[0084] Furthermore, when Figure 8 The illustrated six-bit structure 400 serves as a scalable layout unit. During bit expansion, in some examples, to facilitate coupling between scalable layout units, the first capacitor islands can be configured as couplers. Since the scalable layout unit of the six-bit structure has six first capacitor islands, one, two, or more of these first capacitor islands can be selected as needed to configure couplers. Furthermore, the scalable layout unit may also include a read bus 401 located within an internal region, which is coupled to each of the six read cavities to interact with each bit through each read cavity. Figure 9 The image shows a coupler configured with three of the first capacitor islands selected, and a read bus 401, which can be implemented as a coplanar waveguide.

[0085] As an example of the application of the above six-bit scalable layout unit, it is possible to use, for example, at least two to expand it into a multi-bit structure.

[0086] Specifically, the multi-bit structure may include at least three scalable layout cells. All scalable layout cells are arranged in a honeycomb pattern, and adjacent scalable layout cells are coupled via their respective first capacitor islands. Three adjacent scalable layout cells enclose an annular outer region outside the inner region; for example... Figure 10 As shown. Other operational structures for the qubits (e.g., control structures without a readout cavity), such as flux control lines and drive control lines, can be configured within the annular outer region.

[0087] exist Figure 10 A multi-bit structure based on a scalable layout cell consisting of six-bit hexagons is disclosed, formed by using three scalable layout cells in combination. In other examples, the multi-bit structure can also be constructed with two, four, five, or more cells. Therefore, it is foreseeable that such a multi-bit structure will have a honeycomb structure when expanded with a sufficiently large number of scalable layout cells.

[0088] In such or the aforementioned multi-bit structures, as described above, the concentration of the operational structures associated with qubits in the multi-bit system can be increased, mainly referring to the readout structure and control structure. This allows for better utilization of the limited space of the chip and reduces the difficulty of configuring these structures.

[0089] Therefore, the example also discloses a layout design method for multi-bit structures that improves space utilization in chips.

[0090] See Figure 11 and Figure 12 Layout design methods include:

[0091] Step S101: Design and configure a quantum bit with a readout cavity, wherein the quantum bit is based on a superconducting quantum interference device and has two capacitive elements.

[0092] A qubit in this context may have two physically separated capacitor islands and a superconducting quantum interference device connected to these two capacitor islands at both ends. Therefore, such a qubit is called a two-island qubit.

[0093] Furthermore, each qubit has one capacitor arm provided by one of the capacitor islands, and two capacitor arms integrally constructed provided by the other capacitor island, thus giving the qubit a triangular structure. A readout unit is positioned at the junction of two adjacent capacitor arms, and the readout unit is coupled to the qubit unit.

[0094] Step S102: Expand the qubits and readout units as repeating units.

[0095] In the example, the qubit and readout unit are used as the basic unit, and when expanding, the basic unit is reused and arranged in a reasonable layout.

[0096] For example, at least two basic units are arranged in an extended manner, and the qubits in two adjacent basic units are coupled through a capacitor arm.

[0097] Furthermore, based on the needs of the read operation, a read bus can be configured to transmit read signals, which is coupled to the read cavity. Therefore, with Figure 9 Taking the six-bit structure shown as an example, this design method can also include step S103 of configuring the read bus. This involves expanding and arranging the six basic units to form a hexagonal region consisting of six qubits and six read components, i.e. Figure 10 The internal area of ​​the hexagonal region. Therefore, read buses coupled to each of the six read components can be configured within the hexagonal region.

[0098] By using the scalable layout unit described above, or its extended multi-bit structure, a flip chip can be constructed, which also possesses the advantages of using the scalable layout unit. Furthermore, since flip chips can configure different quantum components or circuits on different layers of the chip, combining them with the scalable layout unit described in the examples of this application can further achieve positive effects, such as further reducing the configuration difficulty of quantum components or circuits.

[0099] The flip chip consists of a first chip and a second chip.

[0100] The first chip has the aforementioned multi-bit structure.

[0101] The second chip has flux control lines and drive control lines. The flux control lines are configured to work with a superconducting quantum interference device in the multi-qubit structure to control the frequency of the qubits via magnetic field signals. The drive control lines are configured to work with the first capacitor island to control the transitions of the qubits via voltage signals.

[0102] The first and second chips are layered and interconnected via an interconnect structure. For example, in the context of superconducting quantum chips, indium pillars (with titanium nitride deposited on their surfaces to prevent direct contact between indium and aluminum during interconnection) can be used for interconnection. Specifically, the second chip is layered opposite to the first chip, and both are positioned to align the control lines with the external region.

[0103] The specific manufacturing process of flip chips can employ known processes in the art, such as micro-nano fabrication processes and flip-chip processes in semiconductor chips and integrated circuits. To avoid redundancy, detailed descriptions are omitted in this application.

[0104] The embodiments described above with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0105] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments have been described above with reference to the accompanying drawings. Throughout the description, similar reference numerals are used to denote similar components. In the foregoing description, numerous specific details have been set forth for illustrative purposes in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the embodiments may be combined with and referenced to each other without contradiction.

[0106] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0107] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A scalable layout unit, characterized in that, It includes six qubits arranged in a hexagonal shape and located at the six vertices respectively, the six qubits being coupled sequentially and adjacently, and six readout cavities located within the inner region enclosed by the hexagon, with the six qubits and six readout cavities being coupled one-to-one; Each qubit includes a superconducting quantum interference device, and a first capacitor island and a second capacitor island spaced apart from each other; The second capacitor island has two capacitor elements that are dispersed on both sides of the trajectory extending from the first capacitor island and connected to each other. One end of the superconducting quantum interference device is connected to the first capacitor island, and the other end is connected to the junction of the two capacitor elements; Two adjacent qubits are coupled through adjacent capacitive elements; The internal region is enclosed by a second capacitor island of qubits.

2. The scalable layout unit according to claim 1, characterized in that, The scalable layout unit also features a coupler that is coupled to a qubit via a capacitive element, the coupler being located between two adjacent capacitive elements.

3. The scalable layout unit according to claim 2, characterized in that, The coupler is frequency-tunable, which makes the coupling strength of two adjacent qubits coupled to each other through the coupler adjustable.

4. The scalable layout unit according to claim 2, characterized in that, The scalable layout unit also includes a read bus located within an internal region, and the read bus is coupled to each of the six read cavities.

5. A multi-bit structure extended by scalable layout units as described in any one of claims 1 to 4, characterized in that, The multi-bit structure includes at least three scalable layout units; All scalable layout cells are extended in a honeycomb pattern, and adjacent scalable layout cells are coupled through their respective first capacitor islands. Three adjacent scalable layout cells enclose an annular outer region outside the inner region.

6. A flip chip, characterized in that, include: The first chip has the multi-bit structure described in claim 5; The second chip has a flux control line and a drive control line. The flux control line is configured to work with a superconducting quantum interference device to control the frequency of the qubits, and the drive control line is configured to work with a first capacitor island to control the transitions of the qubits. The second chip is layered and positioned opposite the first chip to align the control line with the external area.

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