Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate; a first dielectric layer on the substrate; a trench in the first dielectric layer; a conductive layer on the bottom and sidewall of the trench, the conductive layer used as a resistance structure; and a second dielectric layer filled in the trench with the conductive layer. The embodiment of the present application is beneficial to increase the equivalent conductive cross-sectional area of the resistance structure, reduce the lateral area occupied by the resistance structure, and further facilitate the miniaturization of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Integrated circuits typically include active devices and passive devices. Active devices include MOS transistors, while passive devices include resistor structures.

[0003] The basic structure of a MOS transistor includes: a channel structure; a gate structure located on the channel structure; and source and drain regions located on both sides of the gate structure, which are in contact with the ends of the channel structure along the extension direction.

[0004] To reduce manufacturing costs, a resistive structure is typically formed during the formation of a MOS transistor.

[0005] However, the current resistor structure occupies too much area. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which increases the equivalent conductive cross-sectional area of ​​the resistor structure, which is beneficial to reducing the lateral area occupied by the resistor structure, and thus beneficial to the miniaturization of the device.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a first dielectric layer located on the substrate; a trench located in the first dielectric layer; a conductive layer located at the bottom and sidewalls of the trench, the conductive layer serving as a resistive structure; and a second dielectric layer filling the trench in which the conductive layer is formed.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a first dielectric layer is formed on the substrate; forming a trench in the first dielectric layer; forming a conductive layer on the bottom and sidewalls of the trench, wherein the conductive layer on the bottom and sidewalls of the trench serves as a resistive structure; and forming a second dielectric layer on the conductive layer to fill the trench.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: The semiconductor structure provided in this embodiment of the invention has a conductive layer located on the bottom and sidewalls of the trench. The conductive layer serves as a resistive structure. Compared with a sheet-like or rectangular resistive structure, the conductive layer is located not only on the bottom of the trench but also on the sidewalls of the trench. With the direction parallel to the substrate as the lateral direction, the equivalent conductive cross-sectional area of ​​the resistive structure is larger for the same lateral area. This is beneficial for reducing the lateral area occupied by the resistive structure and thus for miniaturizing the device.

[0010] In the semiconductor structure formation method provided by the embodiments of the present invention, a trench is formed in the first dielectric layer, and a conductive layer is formed on the bottom and sidewalls of the trench. The conductive layer is used as a resistor structure. Compared with the resistor structure being a sheet structure or a rectangular structure, the conductive layer is not only located on the bottom of the trench, but also on the sidewalls of the trench. With the direction parallel to the substrate as the lateral direction, the equivalent conductive cross-sectional area of ​​the resistor structure is larger under the same lateral area, which is beneficial to reducing the lateral area occupied by the resistor structure, and thus beneficial to the miniaturization of the device. Attached Figure Description

[0011] Figures 1 to 2 This is a schematic diagram of a semiconductor structure. Figures 3 to 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention; Figure 6 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. Figures 7 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention; Figures 15 to 20 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0012] As the background technology shows, current resistor structures occupy too large an area. This paper analyzes, using a semiconductor structure as an example, why the performance of semiconductor structures needs improvement.

[0013] Figures 1 to 2 This is a schematic diagram of a semiconductor structure. Among them, Figure 1 This is a top view. Figure 2 for Figure 1 A cross-sectional view along the xx direction.

[0014] The semiconductor structure includes: a first dielectric layer 1; a conductive layer 2 located on top of the first dielectric layer 1, the conductive layer 2 being a sheet-like structure and used as a resistive structure; and a second dielectric layer 3 located on top of the conductive layer 2.

[0015] The conductive layer 2 is located on top of the first dielectric layer 1. The conductive layer 2 has a sheet-like structure and occupies a large area, which is not conducive to the miniaturization of the device.

[0016] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a first dielectric layer located on the substrate; a trench located in the first dielectric layer; a conductive layer located at the bottom and sidewalls of the trench, the conductive layer serving as a resistive structure; and a second dielectric layer filling the trench in which the conductive layer is formed.

[0017] The semiconductor structure provided in this embodiment of the invention has a conductive layer located on the bottom and sidewalls of the trench. The conductive layer serves as a resistive structure. Compared with a sheet-like or rectangular resistive structure, the conductive layer is located not only on the bottom of the trench but also on the sidewalls of the trench. With the direction parallel to the substrate as the lateral direction, the equivalent conductive cross-sectional area of ​​the resistive structure is larger for the same lateral area. This is beneficial for reducing the lateral area occupied by the resistive structure and thus for miniaturizing the device.

[0018] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 3 to 5 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 3 It is a cross-sectional view along the direction perpendicular to the extension of the channel structure. Figure 4 yes Figure 3 Top view of the resistance region Figure 5 yes Figure 4 A cross-sectional view along the xx direction.

[0019] In this embodiment, the semiconductor structure includes: a substrate 100; a first dielectric layer 160 located on the substrate 100; and a trench 200 (referring to a reference). Figure 8 The first dielectric layer 160 is located in the first dielectric layer 160; the conductive layer 210 is located on the bottom and sidewalls of the trench 200, and the conductive layer 210 is used as a resistive structure; the second dielectric layer 220 is filled in the trench 200 in which the conductive layer 210 is formed.

[0020] The substrate 100 is made of one or more of the following materials: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the substrate 100 is made of silicon and is a silicon substrate.

[0021] In this embodiment, the substrate 100 includes a device region 100a for forming a transistor and a resistor region 100b for forming a resistor structure.

[0022] Specifically, the transistor includes one or both of NMOS transistors and PMOS transistors.

[0023] The first dielectric layer 160 is used to provide a platform for subsequent trench formation, and the first dielectric layer 160 is also used to achieve electrical isolation between adjacent conductive layers.

[0024] The first dielectric layer 160 is a dielectric insulating material, for example, the material of the first dielectric layer 160 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. The first dielectric layer 160 can be a single-layer or multi-layer structure.

[0025] In this embodiment, the semiconductor structure further includes: a channel structure 120 located on the substrate 100 of the device region 100a; an isolation layer 130 located on the substrate 100 and surrounding the channel structure 120; and an interlayer dielectric layer 150 located on the isolation layer 130, wherein the interlayer dielectric layer 150 and the isolation layer 130 serve as the first dielectric layer 160.

[0026] The channel structure 120 is used to provide a conductive channel for the transistor.

[0027] In this embodiment, the transistor is described as a fin field-effect transistor, and the channel structure 120 protrudes from the substrate 100, and the channel structure 120 is a fin.

[0028] In this embodiment, the fin and the substrate 100 are an integral structure, and the material of the fin is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the fin may be different from that of the substrate. The material of the fin may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0029] In this embodiment, there are multiple fins, and the multiple fins are erected on the substrate 100 of the device region 100a.

[0030] In other embodiments, the channel structure may be of other types when forming other types of transistors. For example, when forming a fully enclosed gate transistor, the channel structure includes one or more channel layers spaced apart from the substrate. The channel layers provide a conductive channel for fully enclosing the gate transistor.

[0031] The isolation layer 130 is used to isolate adjacent channel structures, and the isolation layer 130 is also used to isolate the gate structure 140 from the substrate 100. Specifically, in this embodiment, the isolation layer 130 is used to isolate adjacent fins.

[0032] Therefore, the material of the isolation layer 130 is an insulating dielectric material, for example, the material of the isolation layer 130 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0033] In this embodiment, the semiconductor structure further includes: a gate structure 140 located on the isolation layer 130 of the device region 100a and spanning the channel structure 120; and source / drain doped regions (not shown) located on both sides of the gate structure 140 and in contact with the end of the channel structure 120 along the extension direction.

[0034] Correspondingly, the interlayer dielectric layer 150 is located on the isolation layer 130 on the side of the gate structure 140.

[0035] In this embodiment, the gate structure 140 is a device gate structure. When the device is working, the gate structure 140 is used to control the opening and closing of the transistor's conductive channel.

[0036] In this embodiment, the gate structure 140 spans the fin and covers a portion of the top and sidewalls of the fin. In other embodiments, when the transistor is a fully enclosed gate transistor, the gate structure correspondingly surrounds the channel layer.

[0037] In this embodiment, the gate structure 140 is a metal gate structure. In other embodiments, the gate structure can also be other types of gate structures, such as polycrystalline silicon or amorphous silicon gate structures.

[0038] In a specific implementation, the gate structure 140 may include a work function layer and a gate electrode layer located on the work function layer. In this embodiment, the material of the gate structure 140 includes any one or more of the following: TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0039] It should be noted that, in this embodiment, a gate dielectric layer 165 is further formed between the gate structure 140 and the channel structure 120, and the gate dielectric layer 165 is used to achieve insulation between the gate structure 140 and the conductive channel. In this embodiment, the gate dielectric layer 165 is also located between the gate structure 140 and the isolation layer 130, and on the sidewall of the gate structure 140.

[0040] In a specific implementation, the gate dielectric layer 165 may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. The material of the gate oxide layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the high-k gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0041] In other embodiments, the gate dielectric layer may comprise only the gate oxide layer or only the high-k gate dielectric layer.

[0042] In this embodiment, a sidewall 145 is also formed on the sidewall of the gate structure 140. The sidewall 145 is used to protect the sidewall of the gate structure 140 and to define the formation location of the source and drain doped regions.

[0043] The material of the sidewall 145 includes one or more of silicon oxide, silicon nitride, low dielectric constant, and ultra-low dielectric constant materials.

[0044] The source / drain doped regions are used as the source or drain of the field-effect transistor. When the field-effect transistor is operating, the source / drain doped regions provide a source of charge carriers. In this embodiment, the source / drain doped regions are located within the fins on both sides of the gate structure 140 and the sidewall 145.

[0045] In this embodiment, the source / drain doped regions include a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility. When forming a PMOS transistor, the source / drain doped regions include a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source / drain doped regions include a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0046] The interlayer dielectric layer 150 is used to isolate adjacent devices. Specifically, the interlayer dielectric layer 150 covers the sidewall of the sidewall 145.

[0047] The interlayer dielectric layer 150 is made of an insulating material. The material of the interlayer dielectric layer 150 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, germanium silicon oxide, boron nitride, and boron carbonitride. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0048] In this embodiment, the semiconductor structure further includes a contact etch barrier layer 170, located between the isolation layer 130 and the interlayer dielectric layer 150.

[0049] In the semiconductor field, the semiconductor structure typically includes a source / drain interconnect layer (not shown) that penetrates the interlayer dielectric layer 150 and contacts the source / drain doped regions. The formation steps of the source / drain interconnect layer typically include: forming an interconnect trench penetrating the top of the interlayer dielectric layer 150 above the source / drain doped regions, and forming the source / drain interconnect layer within the interconnect trench. In this embodiment, the contact etch stop layer 170 is used to temporarily define the etch stop position during the interconnect trench formation process to improve the etch uniformity of the interconnect trench and reduce the probability of damage to the source / drain doped regions caused by the interconnect trench formation process. Furthermore, the contact etch stop layer 170 is also used to define the etch stop position during trench formation to improve the bottom height uniformity of the trench.

[0050] The contact etch barrier layer 170 is made of a material that exhibits etching selectivity similar to that of the interlayer dielectric layer 150 and the isolation layer 130. As an example, the interlayer dielectric layer 150 and the isolation layer 130 are both made of silicon oxide, and the contact etch barrier layer 170 is made of silicon nitride.

[0051] The trench 200 is used to provide space for the formation of the conductive layer 210.

[0052] In this embodiment, the trench 200 penetrates the interlayer dielectric layer 150 of the resistive region 100b.

[0053] In the semiconductor field, a semiconductor structure typically includes: a source-drain interconnect layer located in the interlayer dielectric layer and in contact with the source-drain doped region; a source-drain plug in contact with the source-drain interconnect layer; and a gate plug in contact with the gate structure.

[0054] In this embodiment, the resistor structure is located in the interlayer dielectric layer 150. Accordingly, the process of forming source / drain plugs or forming gate plugs can be used to form a connection structure in contact with the resistor structure, so as to realize the electrical connection between the resistor structure and the external circuit, thereby reducing the difficulty of realizing the electrical connection between the resistor structure and the external circuit.

[0055] As one embodiment, the bottom of the trench 200 exposes the contact etch barrier layer 170. That is, during the formation of the semiconductor structure, the trench 200 can be formed in the interlayer dielectric layer 150 of the resistive region 100b with the top surface of the contact etch barrier layer 170 as the stopping position. This facilitates precise control of the height of the bottom of the trench 200 and correspondingly improves the height uniformity of the bottom of the trench 200 in the resistive region 100b.

[0056] It should be noted that in this embodiment, the trench 200 penetrates the interlayer dielectric layer 150 of the resistive region 100b as an example. In other embodiments, the trench may also penetrate the interlayer dielectric layer and the contact etch barrier layer of the resistive region, or the trench may penetrate the interlayer dielectric layer and the contact etch barrier layer of the resistive region, as well as a portion of the thickness of the isolation layer.

[0057] In this embodiment, the semiconductor structure further includes a source-drain interconnect layer (not shown) that penetrates the interlayer dielectric layer 150 on top of the source-drain doped region, and the source-drain interconnect layer is in contact with the source-drain doped region.

[0058] The source-drain interconnect layer is used to realize the electrical connection between the source-drain doped regions and the external circuit.

[0059] The source-drain interconnect layer is made of a conductive material. In this embodiment, the material of the source-drain interconnect layer includes one or more of W, Co, Cu, Ru, and Ni.

[0060] In the process of forming a semiconductor structure, the step of forming the source-drain interconnect layer includes: forming an interconnect trench through the top of the interlayer dielectric layer 150 of the source-drain doped region; and forming the source-drain interconnect layer in the interconnect trench.

[0061] In this embodiment, the semiconductor structure further includes a hard mask layer 180 located on the first dielectric layer 160 and the gate structure 140. The hard mask layer 180 serves as a mask for forming the trench 200 and the interconnect trench.

[0062] In this embodiment, the hard mask layer 180 is made of an insulating dielectric material, so that after the resistive structure is formed, the hard mask layer 180 can remain in the semiconductor structure, eliminating the need for removing the hard mask layer 180. Furthermore, the material of the hard mask layer 180 has etching selectivity with the material of the first dielectric layer 160. As an example, the material of the hard mask layer 180 includes silicon nitride.

[0063] In other embodiments, the masking layer may be omitted from the semiconductor structure.

[0064] Compared to the sheet-like or rectangular structure of the resistor structure, in this embodiment, the conductive layer 210 is not only located at the bottom of the trench 200, but also on the sidewall of the trench 200. With the direction parallel to the substrate 100 as the lateral direction, the equivalent conductive cross-sectional area of ​​the resistor structure is larger under the same lateral area, which is beneficial to reducing the lateral area occupied by the resistor structure and thus to miniaturizing the device.

[0065] In this embodiment, the material of the conductive layer 210 includes one or more of TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni. As an example, the material of the conductive layer 210 is TiN.

[0066] The second dielectric layer 220 is used to fill the trench 200, thereby providing a flat surface for the process. The material of the second dielectric layer 220 is an insulating dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0067] In this embodiment, the semiconductor structure further includes: a third dielectric layer 230 covering the first dielectric layer 160, the second dielectric layer 220, and the conductive layer 210; and a connection structure located in the third dielectric layer 230 and in contact with the conductive layer 210.

[0068] The third dielectric layer 230 is used to achieve electrical isolation between the connection structures. The material of the third dielectric layer 230 is an insulating dielectric material, including one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

[0069] It should be noted that, for ease of illustration and explanation, Figure 4 The third dielectric layer 230 is omitted in the middle.

[0070] The connection structure is used to realize the electrical connection between the resistor structure and the external circuit.

[0071] In this embodiment, the resistor structure is located in the interlayer dielectric layer 150. Accordingly, the process of forming source / drain plugs or forming gate plugs can be used to form a connection structure in contact with the resistor structure, so as to realize the electrical connection between the resistor structure and the external circuit, thereby reducing the difficulty of realizing the electrical connection between the resistor structure and the external circuit.

[0072] In this embodiment, the top surface of the conductive layer 210 is flush with the top surface of the source-drain interconnect layer, so as to achieve electrical connection between the conductive layer 210 and external circuits or other interconnect structures by using the process of forming source-drain plugs. In other embodiments, the top surface of the conductive layer may also be flush with the top surface of the gate structure, so as to achieve electrical connection between the conductive layer and external circuits or other interconnect structures by using the process of forming the gate plug.

[0073] As an example, the connection structure includes a contact plug 240 in contact with the conductive layer 210 and an interconnect layer 250 located on the contact plug 240.

[0074] The materials of the connecting structure include one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0075] Figure 6 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. The similarities between this embodiment and the foregoing embodiments will not be repeated here. The differences between this embodiment and the foregoing embodiments are as follows: In this embodiment, the trench is located in the interlayer dielectric layer 370 of the resistive region 300b and exposes the isolation layer 380.

[0076] In this embodiment, the semiconductor structure further includes: a sidewall 390 located on the sidewall of the gate structure 330 and between the sidewall of the conductive layer 350 and the interlayer dielectric layer 370.

[0077] The sidewall 390 is located on the sidewall of the gate structure 330 and between the sidewall of the conductive layer 350 and the interlayer dielectric layer 370. This is because during the formation of the semiconductor structure, a first dummy gate structure is formed on the isolation layer 380 of the resistive region 300b. The first dummy gate structure is used to occupy space for forming the trench. In other words, the trench is formed by removing the first dummy gate structure.

[0078] Furthermore, in conjunction with references Figure 15 During the formation of the semiconductor structure, a second pseudo-gate structure is formed on the device region before the gate structure is formed. The second pseudo-gate structure and the first pseudo-gate structure are formed in the same step, thereby utilizing the process steps for forming the second pseudo-gate structure 320 to form the first pseudo-gate structure 310, which is beneficial to improving process compatibility.

[0079] In this embodiment, the semiconductor structure further includes a contact etch barrier layer 395, located between the isolation layer 380 and the interlayer dielectric layer 370, and between the sidewall 390 and the interlayer dielectric layer 370.

[0080] For a description of the contact etch barrier layer 395, please refer to the corresponding description of the contact etch barrier layer 170 in the foregoing embodiments, which will not be repeated here.

[0081] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 7 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0082] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0083] refer to Figure 7 A substrate 100 is provided, on which a first dielectric layer 160 is formed.

[0084] The substrate 100 is used to provide an operating platform for subsequent process manufacturing.

[0085] The substrate 100 is made of one or more of the following materials: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the substrate 100 is made of silicon and is a silicon substrate.

[0086] In this embodiment, the substrate 100 includes a device region 100a for forming a transistor and a resistor region 100b for forming a resistor structure.

[0087] Specifically, the transistor includes one or both of NMOS transistors and PMOS transistors.

[0088] The first dielectric layer 160 is used to provide a platform for subsequent trench formation, and the first dielectric layer 160 is also used to achieve electrical isolation between adjacent conductive layers.

[0089] The first dielectric layer 160 is a dielectric insulating material, for example, the material of the first dielectric layer 160 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. The first dielectric layer 160 can be a single-layer or multi-layer structure.

[0090] In this embodiment, during the step of providing the substrate 100, a channel structure 120 is formed on the substrate 100 of the device region 100a, and an isolation layer 130 is also formed on the substrate 100 surrounding the channel structure 120. A gate structure 140 is formed on the isolation layer 130 of the device region 100a and spans the channel structure 120. Source and drain doped regions (not shown) are also formed on both sides of the gate structure 140. The source and drain doped regions are in contact with the ends of the channel structure 120 along the extension direction. An interlayer dielectric layer 150 is formed on the isolation layer 130 on the side of the gate structure 140. The interlayer dielectric layer 150 and the isolation layer 130 are used as the first dielectric layer 160.

[0091] The channel structure 120 is used to provide a conductive channel for the transistor.

[0092] In this embodiment, the transistor is described as a fin field-effect transistor, and the channel structure 120 protrudes from the substrate 100, and the channel structure 120 is a fin.

[0093] In this embodiment, the fin and the substrate 100 are an integral structure, and the material of the fin is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the fin may be different from that of the substrate. The material of the fin may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0094] In this embodiment, there are multiple fins, and the multiple fins are erected on the substrate 100 of the device region 100a.

[0095] In other embodiments, the channel structure may be of other types when forming other types of transistors. For example, when forming a fully enclosed gate transistor, the channel structure includes one or more channel layers spaced apart from the substrate. The channel layers provide a conductive channel for fully enclosing the gate transistor.

[0096] The isolation layer 130 is used to isolate adjacent channel structures, and the isolation layer 130 is also used to isolate the gate structure 140 from the substrate 100. Specifically, in this embodiment, the isolation layer 130 is used to isolate adjacent fins.

[0097] Therefore, the material of the isolation layer 130 is an insulating dielectric material, for example, the material of the isolation layer 130 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0098] In this embodiment, a gate structure 140 spanning the channel structure 120 is also formed on the isolation layer 130 of the device region 100a. Source and drain doped regions (not shown) are also formed on both sides of the gate structure 140, and the source and drain doped regions are in contact with the end of the channel structure 120 along the extension direction.

[0099] Correspondingly, the interlayer dielectric layer 150 is located on the isolation layer 130 on the side of the gate structure 140.

[0100] In this embodiment, the gate structure 140 is a device gate structure. When the device is working, the gate structure 140 is used to control the opening and closing of the transistor's conductive channel.

[0101] In this embodiment, the gate structure 140 spans the fin and covers a portion of the top and sidewalls of the fin. In other embodiments, when the transistor is a fully enclosed gate transistor, the gate structure correspondingly surrounds the channel layer.

[0102] In this embodiment, the gate structure 140 is a metal gate structure. In other embodiments, the gate structure can also be other types of gate structures, such as polycrystalline silicon or amorphous silicon gate structures.

[0103] In a specific implementation, the gate structure 140 may include a work function layer and a gate electrode layer located on the work function layer. In this embodiment, the material of the gate structure 140 includes any one or more of the following: TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0104] It should be noted that, in this embodiment, a gate dielectric layer 165 is further formed between the gate structure 140 and the channel structure 120, and the gate dielectric layer 165 is used to achieve insulation between the gate structure 140 and the conductive channel. In this embodiment, the gate dielectric layer 165 is also located between the gate structure 140 and the isolation layer 130, and on the sidewall of the gate structure 140.

[0105] In a specific implementation, the gate dielectric layer 165 may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. The material of the gate oxide layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the high-k gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0106] In other embodiments, the gate dielectric layer may comprise only the gate oxide layer or only the high-k gate dielectric layer.

[0107] In this embodiment, a sidewall 145 is also formed on the sidewall of the gate structure 140. The sidewall 145 is used to protect the sidewall of the gate structure 140 and to define the formation location of the source and drain doped regions.

[0108] The material of the sidewall 145 includes one or more of silicon oxide, silicon nitride, low dielectric constant, and ultra-low dielectric constant materials.

[0109] The source / drain doped regions are used as the source or drain of the field-effect transistor. When the field-effect transistor is operating, the source / drain doped regions provide a source of charge carriers. In this embodiment, the source / drain doped regions are located within the fins on both sides of the gate structure 140 and the sidewall 145.

[0110] In this embodiment, the source / drain doped regions include a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility. When forming a PMOS transistor, the source / drain doped regions include a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source / drain doped regions include a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0111] The interlayer dielectric layer 150 is used to isolate adjacent devices. Specifically, the interlayer dielectric layer 150 covers the sidewall of the sidewall 145.

[0112] The interlayer dielectric layer 150 is made of an insulating material. The material of the interlayer dielectric layer 150 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, germanium silicon oxide, boron nitride, and boron carbonitride. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0113] It should also be noted that, in this embodiment, a contact etching barrier layer 170 is formed between the isolation layer 130 and the interlayer dielectric layer 150.

[0114] In this embodiment, the contact etch barrier layer 170 is used to temporarily define the etch stop position during the subsequent interconnect trench formation process, so as to improve the etch consistency of the interconnect trench and reduce the probability of damage to the source and drain doped regions caused by the interconnect trench formation process. In addition, the contact etch barrier layer 170 is also used to define the etch stop position during the subsequent trench formation process, so as to improve the bottom height consistency of the trench.

[0115] The contact etch barrier layer 170 is made of a material that exhibits etching selectivity similar to that of the interlayer dielectric layer 150 and the isolation layer 130. As an example, the interlayer dielectric layer 150 and the isolation layer 130 are both made of silicon oxide, and the contact etch barrier layer 170 is made of silicon nitride.

[0116] refer to Figure 8 A trench 200 is formed in the first dielectric layer 160.

[0117] The trench 200 is used to provide space for the formation of the conductive layer.

[0118] In this embodiment, the step of forming the trench 200 in the first dielectric layer 160 includes: forming the trench 200 in the interlayer dielectric layer 150 of the resistive region 100b.

[0119] Accordingly, a conductive layer is subsequently formed on the bottom and sidewalls of the trench 200. The conductive layer on the bottom and sidewalls of the trench 200 serves as a resistive structure, which is located in the interlayer dielectric layer 150.

[0120] In the semiconductor field, subsequent steps typically include: forming a source-drain interconnect layer located in the interlayer dielectric layer and in contact with the source-drain doped regions; forming a source-drain plug in contact with the source-drain interconnect layer; and forming a gate plug in contact with the gate structure. In this embodiment, the resistor structure is located in the interlayer dielectric layer 150. Accordingly, the subsequent processes for forming source-drain plugs or forming gate plugs can be used to form a connection structure in contact with the resistor structure, thereby realizing the electrical connection between the resistor structure and the external circuit, which reduces the difficulty of realizing the electrical connection between the resistor structure and the external circuit.

[0121] More specifically, in this embodiment, the step of forming the trench 200 includes: taking the top surface of the contact etch barrier layer 170 as the stop position, forming the trench 200 in the interlayer dielectric layer 150 of the resistor region 100b, which is beneficial to accurately control the height of the bottom of the trench 200 and correspondingly improve the height consistency of the bottom of the trench 200 in the resistor region 100b.

[0122] In this embodiment, an anisotropic dry etching process is used to etch the interlayer dielectric layer 150 of the resistive region 100b to form the trench 200. The anisotropic dry etching process has the characteristics of anisotropic etching, which is beneficial to improving the profile control of the trench 200. Moreover, the dry etching process can easily achieve a high etching selectivity, so the dry etching process can easily stop on the top surface of the contact etch barrier layer 170.

[0123] It should be noted that in this embodiment, the trench 200 penetrates the interlayer dielectric layer 150 of the resistive region 100b as an example. In other embodiments, the trench may also penetrate the interlayer dielectric layer and the contact etch barrier layer of the resistive region, or the trench may penetrate the interlayer dielectric layer and the contact etch barrier layer of the resistive region, as well as a portion of the thickness of the isolation layer.

[0124] It should also be noted that, in this embodiment, the method for forming the semiconductor structure further includes: in the step of forming the trench 200, forming an interconnect trench (not shown) that penetrates the interlayer dielectric layer 150 on the top of the source / drain doped region. The interconnect trench is used to provide space for forming the source / drain interconnect layer.

[0125] In this embodiment, the trench 200 and the interconnect trench are formed in the same step, thereby enabling the formation of the trench 200 using the process steps for forming the interconnect trench. This simplifies the process and improves the compatibility of forming the trench 200 with existing processes.

[0126] Specifically, the interconnect trench exposes the source / drain doped regions so that the source / drain interconnect layer subsequently formed in the interconnect trench can contact the source / drain doped regions.

[0127] In this embodiment, before forming the trench 200, the method for forming the semiconductor structure further includes forming a hard mask layer 180 on the first dielectric layer 160 and the gate structure 140. The hard mask layer 180 is used as a mask for forming the trench 200 and the interconnect trench.

[0128] In this embodiment, the hard mask layer 180 is made of an insulating dielectric material, so that after the resistive structure is formed, the hard mask layer 180 can remain in the semiconductor structure, eliminating the need for removing the hard mask layer 180. Furthermore, the material of the hard mask layer 180 has etching selectivity with the material of the first dielectric layer 160. As an example, the material of the hard mask layer 180 includes silicon nitride.

[0129] In this embodiment, the method for forming the semiconductor structure further includes: after forming the interconnect trench, forming a source-drain interconnect layer in the interconnect trench, wherein the source-drain interconnect layer is in contact with the source-drain doped region.

[0130] The source-drain interconnect layer is used to realize the electrical connection between the source-drain doped regions and the external circuit.

[0131] The source-drain interconnect layer is made of a conductive material. In this embodiment, the material of the source-drain interconnect layer includes one or more of W, Co, Cu, Ru, and Ni.

[0132] refer to Figure 9 A conductive layer 210 is formed on the bottom and sidewalls of the trench 200, and the conductive layer 210 located on the bottom and sidewalls of the trench 200 is used as a resistive structure.

[0133] In this embodiment, a conductive layer 210 is formed on the bottom and sidewalls of the trench 200. The conductive layer 210 located on the bottom and sidewalls of the trench 200 serves as a resistive structure. Compared with the resistive structure being a sheet structure or a rectangular structure, the conductive layer 210 is not only located at the bottom of the trench 200, but also on the sidewalls of the trench 200, with the direction parallel to the substrate 100 as the lateral direction. Under the same lateral area, the equivalent conductive cross-sectional area of ​​the resistive structure is larger, which is beneficial to reducing the lateral area occupied by the resistive structure, and thus beneficial to the miniaturization of the device.

[0134] In this embodiment, the material of the conductive layer 210 includes one or more of TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni. As an example, the material of the conductive layer 210 is TiN.

[0135] In this embodiment, the process for forming the conductive layer 210 includes atomic layer deposition (ALD). ALD has high step coverage capability, which is beneficial for improving the deposition capability of the conductive layer 210 on the bottom and sidewalls of the trench 200, and also helps to improve the thickness uniformity of the conductive layer 210.

[0136] It should be noted that, in this embodiment, during the step of forming the conductive layer 210, the conductive layer 210 is also formed on top of the first dielectric layer 160.

[0137] refer to Figures 10 to 11 A second dielectric layer 220 is formed on the conductive layer 210 to fill the trench 200.

[0138] The second dielectric layer 220 is used to fill the trench 200, thereby providing a flat surface for subsequent process steps.

[0139] The material of the second dielectric layer 220 is an insulating dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0140] In this embodiment, the step of forming the second dielectric layer 220 includes: like Figure 10 As shown, a dielectric material layer 190 filling the trench 200 is formed on the conductive layer 210, and the dielectric material layer 190 is also formed on the conductive layer 210 on top of the first dielectric layer 160.

[0141] The dielectric material layer 190 is used to form the second dielectric layer 220.

[0142] As one embodiment, the dielectric material layer 190 is formed using a chemical vapor deposition (CVD) process. CVD has good gap-filling capabilities, low process cost, and high process compatibility.

[0143] like Figure 11 As shown, the conductive layer 210 and the dielectric material layer 190 located on top of the first dielectric layer 160 are removed, and the remaining dielectric material layer 190 filling the trench 200 is used as the second dielectric layer 220.

[0144] In this embodiment, a planarization process is used to remove the conductive layer 210 and the dielectric material layer 190 located on top of the first dielectric layer 160. By employing a planarization process, the top flatness and height consistency of the second dielectric layer 220 and the hard mask layer 180 can be improved while removing the conductive layer 210 and the dielectric material layer 190 located on top of the first dielectric layer 160, thereby providing a flat surface for subsequent process steps.

[0145] In this embodiment, the planarization process includes chemical mechanical planarization (CMP) process.

[0146] refer to Figures 12 to 14 , Figure 12 Based on Figure 11 Cross-sectional view, Figure 13 yes Figure 12 Top view corresponding to resistance region 100b Figure 14 yes Figure 13 A cross-sectional view along the xx direction shows that the method of forming the semiconductor structure further includes: forming a third dielectric layer 230 covering the first dielectric layer 160, the second dielectric layer 220 and the conductive layer 210, and a connection structure located in the third dielectric layer 230 and in contact with the conductive layer 210.

[0147] The connection structure is used to realize the electrical connection between the resistor structure and the external circuit.

[0148] In the semiconductor field, the steps for forming a semiconductor structure typically include: forming a source-drain interconnect layer located in the first dielectric layer 160 and in contact with the source-drain doped regions; forming a source-drain plug in contact with the source-drain interconnect layer; and forming a gate plug in contact with the gate structure. In this embodiment, the resistor structure is located in the interlayer dielectric layer 150. Accordingly, the process of forming source-drain plugs or forming gate plugs can be used to form a connection structure in contact with the resistor structure, thereby realizing the electrical connection between the resistor structure and the external circuit, which reduces the difficulty of realizing the electrical connection between the resistor structure and the external circuit.

[0149] In this embodiment, the top surface of the conductive layer 210 is flush with the top surface of the source-drain interconnect layer, so as to achieve electrical connection between the conductive layer 210 and external circuits or other interconnect structures by using the process of forming source-drain plugs. In other embodiments, the top surface of the conductive layer may also be flush with the top surface of the gate structure, so as to achieve electrical connection between the conductive layer and external circuits or other interconnect structures by using the process of forming the gate plug.

[0150] As an example, the connection structure includes a contact plug 240 in contact with the conductive layer 210 and an interconnect layer 250 located on the contact plug 240.

[0151] The materials of the connecting structure include one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0152] The third dielectric layer 230 is used to achieve electrical isolation between the connection structures. The material of the third dielectric layer 230 is an insulating dielectric material, including one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

[0153] Figures 15 to 20 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are: refer to Figure 15 In the step of providing the substrate 300, a first pseudo-gate structure 310 is also formed on the isolation layer 380 of the resistor region 300b.

[0154] The first pseudo-gate structure 310 is used to occupy space for the subsequent formation of trenches.

[0155] In this embodiment, the first pseudo-gate structure 310 is a polycrystalline silicon gate structure or an amorphous silicon gate structure, and the material of the first pseudo-gate structure 310 includes polycrystalline silicon or amorphous silicon.

[0156] In this embodiment, during the step of providing the substrate 300, the gate structure located in the device region 300a is a second pseudo-gate structure 320, which occupies space for forming the device gate structure.

[0157] In this embodiment, the material of the second pseudo-gate structure 320 is the same as that of the first pseudo-gate structure 310, and the material of the second pseudo-gate structure 320 includes polycrystalline silicon or amorphous silicon.

[0158] It should be noted that the first pseudo-gate structure 310 and the second pseudo-gate structure 320 are formed in the same step, thereby utilizing the process steps for forming the second pseudo-gate structure 320 to form the first pseudo-gate structure 310, which is beneficial to improving process compatibility.

[0159] refer to Figure 16 The second pseudo-gate structure 320 is removed to form a gate opening (not shown); a device gate structure 330 is formed within the gate opening.

[0160] When the device is in operation, the device gate structure 330 is used to control the opening and closing of the transistor's conductive channel.

[0161] For a description of the device gate structure 330, please refer to the corresponding description of the device gate structure in the foregoing embodiments, which will not be repeated here.

[0162] refer to Figure 17 The step of forming the trench 340 includes: removing the first pseudo-gate structure 310 to form the trench 340.

[0163] In this embodiment, after removing the second pseudo-gate structure 320, the first pseudo-gate structure 310 is removed to form the trench 340.

[0164] In other embodiments, the second dummy gate structure can be removed during the step of removing the first dummy gate structure to form the trench, forming a gate opening; and a device gate structure can be formed within the gate opening. By removing the first dummy gate structure and the second dummy gate structure in the same step, the first dummy gate structure can be removed to form the trench using the transistor fabrication process in the device region, improving the compatibility of forming the trench with existing processes.

[0165] refer to Figure 18 A conductive layer 350 is formed on the bottom and sidewalls of the trench 340, and the conductive layer 350 located on the bottom and sidewalls of the trench 340 is used as a resistive structure.

[0166] For a detailed description of the conductive layer 350 and the resistive structure, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0167] refer to Figures 19 to 20 A second dielectric layer 360 is formed on the conductive layer 350 to fill the trench 340. For a detailed description of the second dielectric layer 360, please refer to the corresponding description of the second dielectric layer 220 in the foregoing embodiments, which will not be repeated here.

[0168] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A first dielectric layer is located on the substrate; The trench is located in the first dielectric layer; A conductive layer is located at the bottom and on the sidewalls of the trench, and the conductive layer is used as a resistive structure; wherein the conductive layer is located only within the trench and exposes a first dielectric layer located on the side of the trench, and the conductive layer located on the sidewalls of the trench is the conductive layer side; A second dielectric layer is filled in the trench in which the conductive layer is formed; The contact plug is located on the top surface of the side portion of the conductive layer and is in contact with the top surface of the side portion of the conductive layer.

2. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a device region for forming transistors and a resistive region for forming resistive structures; The semiconductor structure further includes: a channel structure located on the substrate of the device region; an isolation layer located on the substrate and surrounding the channel structure; and an interlayer dielectric layer located on the isolation layer, wherein the interlayer dielectric layer and the isolation layer serve as the first dielectric layer. The trench penetrates the interlayer dielectric layer of the resistive region.

3. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes: a contact etch barrier layer located between the isolation layer and the interlayer dielectric layer; The bottom of the trench exposes the contact etch barrier layer.

4. The semiconductor structure as described in claim 2 or 3, characterized in that, The semiconductor structure further includes: a gate structure located on the isolation layer of the device region and spanning the channel structure; source / drain doped regions located on both sides of the gate structure and in contact with the ends of the channel structure along the extension direction; and a source / drain interconnect layer penetrating the interlayer dielectric layer on top of the source / drain doped regions, wherein the source / drain interconnect layer is in contact with the source / drain doped regions.

5. The semiconductor structure as described in claim 4, characterized in that, The trench is located in the interlayer dielectric layer of the resistive region and exposes the isolation layer; The semiconductor structure further includes: sidewalls located on the sidewalls of the gate structure and between the sidewalls of the conductive layer and the interlayer dielectric layer.

6. The semiconductor structure as described in claim 5, characterized in that, The semiconductor structure further includes: a contact etch barrier layer located between the isolation layer and the interlayer dielectric layer, and between the sidewall and the interlayer dielectric layer.

7. The semiconductor structure as described in claim 1, 2, 3, 5 or 6, characterized in that, The conductive layer is made of one or more of the following materials: TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a first dielectric layer is formed; Trenches are formed in the first dielectric layer; A conductive layer is formed on the bottom and sidewalls of the trench, and the conductive layer on the bottom and sidewalls of the trench is used as a resistive structure; A second dielectric layer is formed on the conductive layer to fill the trench; In the step of forming the second dielectric layer, the conductive layer is located only within the trench and exposes the first dielectric layer located on the side of the trench, and the conductive layer located on the sidewall of the trench is the conductive layer side; A contact plug is formed on the top surface of the side portion of the conductive layer, and the contact plug is in contact with the top surface of the side portion of the conductive layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The substrate includes a device region for forming transistors and a resistive region for forming resistive structures; In the step of providing a substrate, a channel structure is formed on the substrate of the device region, and an isolation layer surrounding the channel structure is also formed on the substrate. An interlayer dielectric layer is formed on the isolation layer, and the interlayer dielectric layer and the isolation layer are used as the first dielectric layer. The step of forming the trench in the first dielectric layer includes: forming the trench in the interlayer dielectric layer of the resistive region.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, a gate structure spanning the channel structure is also formed on the isolation layer of the device region, and source and drain doped regions are formed on both sides of the gate structure, and the source and drain doped regions are in contact with the end of the channel structure along the extension direction. The method for forming the semiconductor structure further includes: in the step of forming the trench, forming an interconnect trench that penetrates the interlayer dielectric layer on the top of the source / drain doped region; After the interconnect trench is formed, a source / drain interconnect layer is formed in the interconnect trench, and the source / drain interconnect layer is in contact with the source / drain doped region.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, a contact etching barrier layer is also formed between the isolation layer and the interlayer dielectric layer; The step of forming the trench includes: forming the trench in the interlayer dielectric layer of the resistive region with the top surface of the contact etch barrier layer as the stop position.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing the substrate, a first pseudo-gate structure is also formed on the isolation layer of the resistive region; The step of forming the trench includes: removing the first pseudo-gate structure to form the trench.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, the gate structure located in the device region is a second pseudo-gate structure; The method for forming the semiconductor structure further includes: in the step of removing the first dummy gate structure to form the trench, removing the second dummy gate structure to form a gate opening; A device gate structure is formed within the gate opening.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the conductive layer, the conductive layer is also formed on top of the first dielectric layer; The step of forming the second dielectric layer includes: forming a dielectric material layer filling the trench on the conductive layer, the dielectric material layer also being formed on the conductive layer on top of the first dielectric layer; The conductive layer and the dielectric material layer located on top of the first dielectric layer are removed, and the remaining dielectric material layer filling the trench is used as the second dielectric layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, A planarization process is used to remove the conductive layer and the dielectric material layer located on top of the first dielectric layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The planarization process includes chemical mechanical planarization.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process for forming the conductive layer includes atomic layer deposition.

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