A method for designing a forward error correction code (FEC) and related devices

Abstract

The application provides a design method of a forward error correction code (FEC) and related equipment. The method comprises the following steps: determining the number of transmission channels for transmitting data, and determining a plurality of FEC working areas based on the number of the transmission channels, wherein the number of the plurality of FEC working areas is the same as the number of the transmission channels, the transmission channels are used for transmitting data, and the FEC working areas are used for checking and correcting the data; uniformly distributing the data on the transmission channels to each of the plurality of FEC working areas; and processing the data received by each of the plurality of FEC working areas. According to the scheme, by selecting the same number of FEC working areas as the number of transmission channels, the size and design complexity of an interface circuit can be reduced, and the production cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a design method and related equipment for a forward error correction code (FEC). Background Technology

[0002] Forward error correction (FEC), or channel coding, is a technique for controlling transmission errors in a one-way communication system. It reduces the bit error rate by sending additional information along with the data to recover from errors. FEC further improves the burst error correction capability of each channel by interleaving the data on each lane onto multiple FEC working areas, distributing burst errors across multiple FEC blocks. Figure 1 As shown, during data transmission, continuous bit errors occur on a certain transmission channel. After deinterleaving at the receiving end, these continuous bit errors are converted into sporadic bit errors, making error correction easier during channel decoding. Reed-Solomon (RS) codes are a type of FEC encoding suitable for correcting such burst errors and are widely used in various commercial scenarios, such as high-density digital video discs (DVDs), Blu-ray discs, digital subscriber lines (DSL), and digital video broadcasting (DVB).

[0003] Interface services are used in various scenarios. Interfaces contain multiple transmission channels, and different numbers of transmission channels are required in different scenarios. However, in the existing protocol, regardless of the number of transmission channels used, the data is interleaved onto a fixed number of FEC work areas. This will result in different data interleaving situations when the number of transmission channels used is different, which will lead to an increase in the size of the interface circuit, increased design complexity, and increased production costs.

[0004] Therefore, how to unify the data interleaving form and the data arrangement structure on each transmission channel when using different numbers of transmission channels to transmit data, reduce the size and design complexity of interface circuits, and reduce production costs is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a design method and related equipment for forward error correction codes (FEC). By using FEC working areas with the same number of transmission channels, the data on the transmission channels is evenly distributed to each FEC working area, which can unify the data layout structure on each transmission channel, reduce the size and design complexity of the interface circuit, and effectively reduce production costs.

[0006] In a first aspect, a forward error correction (FEC) code design method is provided. The method includes: determining the number of transmission channels for transmitting data, and determining multiple FEC work areas based on the number of transmission channels, wherein the number of multiple FEC work areas is the same as the number of transmission channels, wherein the transmission channels are used to transmit data, and the FEC work areas are used to perform error correction on the data; uniformly distributing the data on the transmission channels to each of the multiple FEC work areas; and processing the received data using the multiple FEC work areas.

[0007] In the solution provided in this application, the data on the transmission channel is processed by an FEC work area that matches the transmission channel, and the data on the transmission channel is evenly distributed to each FEC work area. This ensures that the amount of data received by each FEC work area per unit time is equal. Since the processing performance and latency of each FEC work area are the same, the structure of the FEC block and the link transmission block on each transmission channel are consistent after processing by the FEC work area, and the period of the link transmission block boundary is also the same. That is, the data arrangement structure on each transmission channel is consistent, which can reduce the size and design complexity of the interface circuit and reduce production costs.

[0008] In conjunction with the first aspect, in one possible implementation of the first aspect, the data on each transmission channel is divided into multiple data blocks, wherein each data block contains X characters, where X is a positive integer greater than 1; and the X characters contained in each data block are evenly distributed to the multiple FEC work areas.

[0009] In the solution provided in this application, in order to facilitate the processing of data on the transmission channel, the data on the transmission channel needs to be segmented to obtain multiple data blocks. When the data on the transmission channel is evenly distributed to the FEC work area, it is not a simple correspondence between one transmission channel and one FEC work area, and all the data on the transmission channel is distributed to the FEC work area for processing. Instead, the X characters contained in a data block on each transmission channel are distributed one by one to multiple FEC work areas, so that the data processed by the FEC work area each time comes from multiple transmission channels, thereby improving the error correction capability.

[0010] In conjunction with the first aspect, in one possible implementation of the first aspect, if the plurality of FEC work areas are in the encoding state, each of the plurality of FEC work areas performs a calculation every time it receives X characters to obtain Y FEC check bits corresponding to the X characters; or, if the plurality of FEC work areas are in the decoding state, each of the plurality of FEC work areas uses the Y FEC check bits corresponding to each received X characters to perform error correction on the X characters.

[0011] In the scheme provided in this application, the FEC working area can process the data according to its current state. That is, in the encoding state, the FEC working area performs calculations on the X characters mapped from each transmission channel to obtain Y FEC check bits. It is easy to understand that the data processed by the FEC working area comes from different transmission channels. Compared with data from the same transmission channel, continuous errors can be turned into sporadic errors, thus improving the error correction capability. Similarly, in the decoding state, the FEC working area uses Y FEC check bits to check and correct the X characters mapped from each transmission channel.

[0012] In conjunction with the first aspect, in one possible implementation of the first aspect, a data sequence is inserted between the transmission blocks transmitted on each transmission channel in the transmission channel, wherein the transmission block includes Z data blocks, and the data sequence is used to delimit the data transmitted on the transmission channel, wherein Z is a positive integer greater than 1.

[0013] In the solution provided in this application, in order to further improve the processing efficiency of data streams on the transmission channel, the data transmitted on each transmission channel can be divided into more hierarchical structures. Data sequences can be inserted between the transmission blocks. These data sequences are not encoded and are used to delimit, align between channels, and initialize scrambling seeds for the data transmitted on the transmission channel.

[0014] In conjunction with the first aspect, in one possible implementation of the first aspect, a contention reset sequence SR is included between the transport blocks transmitted on each transport channel in the transport channel, the transport block containing Z FEC blocks, the FEC blocks including X characters and Y FEC check bits, wherein X, Y and Z are positive integers greater than 1.

[0015] In conjunction with the first aspect, in one possible implementation of the first aspect, the X characters contained in the data block are equal to the amount of data processed at one time by any one of the plurality of FEC work areas, wherein the amount of data processed at one time by the FEC work area is the amount of data received by the FEC work area per unit time.

[0016] In conjunction with the first aspect, in one possible implementation of the first aspect, the data received by the plurality of work areas and the calculated FEC check bits are inversely mapped onto the transmission channel. Each transmission channel includes a plurality of FEC blocks, wherein each of the plurality of FEC blocks includes X characters and Y FEC check bits.

[0017] In conjunction with the first aspect, in one possible implementation of the first aspect, the FEC block on each transmission channel is divided into multiple transmission blocks, and an SR is inserted between two adjacent transmission blocks. Each transmission block includes Z FEC blocks, where Z is a positive integer greater than 1.

[0018] In conjunction with the first aspect, in one possible implementation of the first aspect, each of the plurality of FEC work areas has the same processing performance and processing latency, and receives the same amount of data to be processed per unit time.

[0019] In a second aspect, a data processing apparatus is provided, comprising: a determining unit, configured to determine the number of transmission channels for transmitting data, and to determine a plurality of FEC work areas based on the number of transmission channels, wherein the number of the plurality of FEC work areas is the same as the number of transmission channels, wherein the transmission channels are used for transmitting data, and the FEC work areas are used for verifying and correcting errors on the data; an allocation unit, configured to evenly allocate the data on the transmission channels to each of the plurality of FEC work areas; and a processing unit, configured to process the data received by each of the plurality of FEC work areas.

[0020] In conjunction with the second aspect, in one possible implementation of the second aspect, the allocation unit is specifically used to: divide the data on each transmission channel into multiple data blocks, wherein each data block contains X characters, where X is a positive integer greater than 1; and evenly distribute the X characters contained in each data block to the multiple FEC work areas.

[0021] In conjunction with the second aspect, in one possible implementation of the second aspect, the processing unit is specifically configured to: if the plurality of FEC working areas are in an encoding state, perform calculations on each of the plurality of FEC working areas for every X characters received to obtain Y FEC check bits corresponding to the X characters; or if the plurality of FEC working areas are in a decoding state, each of the plurality of FEC working areas uses the Y FEC check bits corresponding to each of the X characters received to perform error correction on the X characters.

[0022] In conjunction with the second aspect, in one possible implementation of the second aspect, the processing unit is further configured to insert a data sequence between the transmission blocks transmitted on each transmission channel in the transmission channel, wherein the transmission block includes Z data blocks, and the data sequence is used to delimit the data transmitted on the transmission channel, wherein Z is a positive integer greater than 1.

[0023] In conjunction with the second aspect, in one possible implementation of the second aspect, a contention reset sequence SR is included between the transport blocks transmitted on each transport channel in the transport channel, the transport block containing Z FEC blocks, the FEC blocks including X characters and Y FEC check bits, wherein X, Y and Z are positive integers greater than 1.

[0024] In conjunction with the second aspect, in one possible implementation of the second aspect, the X characters contained in the data block are equal to the amount of data processed at one time by any one of the plurality of FEC work areas, wherein the amount of data processed at one time by the FEC work area is the amount of data received by the FEC work area per unit time.

[0025] In conjunction with the second aspect, in one possible implementation of the second aspect, the allocation unit is further configured to inversely map the data received by the plurality of work areas and the calculated FEC check bits onto the transmission channel, wherein each transmission channel includes a plurality of FEC blocks, wherein each of the plurality of FEC blocks includes X characters and Y FEC check bits.

[0026] In conjunction with the second aspect, in one possible implementation of the second aspect, the processing unit is further configured to divide the FEC block on each transmission channel into multiple transmission blocks, and insert an SR between two adjacent transmission blocks, wherein each transmission block includes Z FEC blocks, where Z is a positive integer greater than 1.

[0027] In conjunction with the second aspect, in one possible implementation of the second aspect, each of the plurality of FEC work areas has the same processing performance and processing latency, and receives the same amount of data to be processed per unit time.

[0028] Thirdly, this application provides a data processing apparatus, the data processing apparatus including a processor and a transmission interface, the processor being configured to invoke computer instructions stored in a memory to execute the methods provided in the first aspect and in combination with any implementation of the first aspect.

[0029] Fourthly, this application provides a computer storage medium storing a computer program that, when executed by a computer or processor, can implement the process of the method provided in the first aspect and in combination with any of the implementations of the first aspect.

[0030] Fifthly, this application provides a computer program product including instructions that, when executed by a computer or processor, cause the computer or processor to perform the process of the method provided in the first aspect and in combination with any implementation of the first aspect. Attached Figure Description

[0031] Figure 1 A schematic diagram of a forward error correction principle provided in an embodiment of this application;

[0032] Figure 2A This application provides a schematic diagram of a 3-channel data interleaving transmission method.

[0033] Figure 2B This is a schematic diagram of a 3-channel data transmission arrangement structure provided in an embodiment of this application;

[0034] Figure 3A This application provides a schematic diagram of a 4-channel data interleaving transmission method.

[0035] Figure 3B This is a schematic diagram of a 4-channel data transmission arrangement structure provided in an embodiment of this application;

[0036] Figure 4 A schematic diagram of a system architecture provided for an embodiment of this application;

[0037] Figure 5 A flowchart illustrating a forward error correction code design method provided in an embodiment of this application;

[0038] Figure 6 A schematic diagram illustrating a data block segmentation method provided in an embodiment of this application;

[0039] Figure 7 A schematic diagram of FEC work area encoding provided in an embodiment of this application;

[0040] Figure 8 This is a schematic diagram of the structure of an FEC block provided in an embodiment of this application;

[0041] Figure 9 This is a schematic diagram of the data structure transmitted through a transmission channel provided in an embodiment of this application;

[0042] Figure 10A schematic diagram of data mapping and transmission between a transmission channel and an FEC work area is provided for an embodiment of this application;

[0043] Figure 11A This is a schematic diagram of data processing in a 1-channel mode provided in an embodiment of this application;

[0044] Figure 11B This is a schematic diagram of a data transmission structure in a 1-channel mode provided in an embodiment of this application;

[0045] Figure 12A This is a schematic diagram of data processing in a 2-channel mode provided in an embodiment of this application;

[0046] Figure 12B This is a schematic diagram of a data transmission structure in a 2-channel mode provided in an embodiment of this application;

[0047] Figure 13 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0048] Figure 14 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0049] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] First, some of the terms and related technologies used in this application will be explained in conjunction with the accompanying drawings to facilitate understanding by those skilled in the art.

[0051] In this embodiment of the application, the transmission channel specifically refers to the channel for transmitting data. Its specific form can be a wired transmission channel or a wireless transmission channel. A transmission interface, such as a high definition multimedia interface (HDMI), can be configured to use multiple transmission channels to transmit data. Depending on the application scenario, different numbers of transmission channels can be used for data transmission. For example, if standard definition video data is to be transmitted, two transmission channels can be selected, and if high definition video data is to be transmitted, four transmission channels can be selected.

[0052] In this embodiment of the application, the FEC work area specifically refers to a hardware circuit used for data processing and error correction. The amount of data processed by each FEC work area is called an FEC block, that is, the amount of data processed by an FEC work area at one time is the same as the amount of data contained in an FEC block.

[0053] In this embodiment of the application, data interleaving specifically refers to mapping data on the transmission channel to the FEC work area, that is, distributing data on each transmission channel to multiple FEC work areas.

[0054] In this embodiment of the application, the data arrangement structure refers to a structural division of data transmitted on the transmission channel. The transmission channel is used to transmit data, and the data to be transmitted includes individual characters. A data block includes X characters, an FEC block includes X characters and Y parity bits, and the Y parity bits correspond to the X characters. A transmission block (also called a link transmission block) includes Z FEC blocks. An SR is inserted between every two adjacent transmission blocks. The SR can also be some character sequence, but the SR is not encoded and is used to delimit the transmission block, initialize the scrambling seed, etc.

[0055] To facilitate understanding of this application, relevant technical knowledge involved in the embodiments of this application will be introduced first.

[0056] In scenarios utilizing multi-channel data transmission, the number of FEC work areas used is fixed, but the data interleaving situation differs depending on the number of transmission channels. When using three transmission channels, the data interleaving situation is as follows: Figure 2A As shown, data from the three transmission channels is interleaved into four different FEC working areas with a four-clock cycle. Each FEC working area performs calculations on the interleaved data to obtain a parity bit. Then, each FEC working area remaps the obtained parity bit and FEC block back onto the previous three transmission channels. The data arrangement structure on each channel is as follows: Figure 2B As shown, the data between a scrambling reset (SR) character and another start super block (SSB) is called a data block. A data block contains not only valid data but also parity bits obtained from FEC work area operations (i.e., RS parity bits in the diagram). This ensures that after receiving data, the receiving end can use the included parity bits to check and correct errors in the data within the transport block. When using four transmission channels to transmit data, the data interleaving situation is as follows... Figure 3AAs shown, data from the four transmission channels is interleaved into four different FEC working areas with a two-clock cycle. Each FEC working area performs calculations on the interleaved data to obtain a parity bit. Then, each FEC working area remaps the obtained parity bit and FEC block back onto the previous four transmission channels. The data arrangement structure on each channel is as follows: Figure 3B As shown, with Figure 2B Similarly, a data block between an SR and an SSB is called a transport block. The transport block also contains a parity bit to check and correct the data in the transport block.

[0057] It can be seen that when interleaving data from the transmission channels to the four FEC work areas, the interleaving methods used in the 3-channel and 4-channel transmission modes differ significantly. The amount of data processed per unit time in each FEC work area is different, and the processing latency is also different. Furthermore, as mentioned above… Figure 2B and Figure 3B As shown, the position of the parity bit is different for each transmission channel, and the transmission block boundary is also different, resulting in huge differences in the entire data arrangement structure. If the transmission interface needs to support both 3-channel and 4-channel transmission modes at the same time, it will lead to an increase in the size of the interface circuit and the design complexity, and the overall production cost will also increase.

[0058] To address the aforementioned issues, this application provides a design method and related equipment for a forward error correction code (FEC). This method interleaves the data on the transmission channels using FEC working areas with the same number of selected transmission channels, evenly distributing the data on the transmission channels to each FEC working area. Each FEC working area then performs calculations and error correction on its interleaved data. This ensures that each FEC working area processes the same amount of data per unit time, that the parity bit positions on each transmission channel are the same, and that the transmission block boundaries are also the same. This reduces the size and design complexity of the interface circuit and effectively lowers production costs.

[0059] The technical solutions of this application can be applied to various scenarios that require flexible selection of the number of transmission channels for data transmission, such as using HDMI to transmit video or audio data.

[0060] See Figure 4 , Figure 4 This is a schematic diagram of a system architecture provided in an embodiment of this application. For example... Figure 4As shown, the system includes a data transmitter 410 and a data receiver 420. The data transmitter can be a set-top box, monitor, etc. The transmission interface on the data transmitter 410 can flexibly select the number of transmission channels according to business needs and perform FEC encoding on the data to be transmitted. The data receiver 420 can be a television, monitor, etc. The data receiver 420 receives data from the transmission channels and performs FEC decoding and error correction on the received data. The data transmitter 410 transmits the data to be transmitted to the transmission interface 4110, which contains multiple transmission channels, such as transmission channel 0, transmission channel 1, and transmission channel 2. The data on each transmission channel is first encoded using a transport block structure, processing the data on each transmission channel into periodic transport blocks, and then FEC encoding is performed. This involves cross-mapping the data from multiple transmission channels to multiple FEC work areas. It should be noted that the number of FEC work areas is the same as the number of transmission channels. The data on each transmission channel is evenly distributed among multiple FEC work areas, and each FEC work area receives the same amount of data per unit time. Multiple parity bits are obtained by operating on the FEC working area, and then the data in the FEC working area is remapped to each transmission channel. It should be understood that the multiple parity bits obtained by operating on each FEC working area will also be cross-mapped to each transmission channel. After completing the FEC encoding, the data on each transmission channel is scrambled to increase the non-coherence capability of the transmission channel. Finally, the data on each transmission channel is sent to the data receiver 420 through the transmission channel via the transmitter, such as transmitter 4111, transmitter 4112 and transmitter 4113. Data receiver 420 receives data sent by data transmitter 410 through multiple receivers in transmission interface 4210, such as receiver 4211, receiver 4212 and receiver 4213. Then, it performs descrambling on the data on each transmission channel. After the descrambling is completed, it performs FEC decoding, which cross-maps the data on multiple transmission channels to multiple FEC working areas. Each FEC working area uses multiple parity bits to check and correct the data. Then, the data after removing the parity bits is re-cross-mapped to each transmission channel. Finally, it performs transport block structure decoding on the data on each transmission channel and reprocesses the transport blocks on each transmission channel into a data stream. This completes the entire data reception process.

[0061] Based on the above, the design method and related equipment of the forward error correction code (FEC) provided in the embodiments of this application will be described below. Please refer to... Figure 5 , Figure 5 This is a flowchart illustrating an FEC design method provided in an embodiment of this application. Figure 5 The data transmitter and data receiver described herein can respectively correspond to Figure 4The data transmitter 410 and data receiver 420 shown are, for example Figure 5 As shown, the method includes, but is not limited to, the following steps:

[0062] S501: Determine the number of transmission channels for transmitting data, and determine multiple FEC work areas based on the number of transmission channels.

[0063] Specifically, the data transmitter's transmission interface can flexibly select the number of transmission channels according to business needs. For example, standard definition, high definition, and 4K video data can be transmitted via HDMI. In this case, the data transmitter will select different numbers of transmission channels to support business needs. Therefore, before sending data, it is necessary to determine the number of transmission channels for transmitting data.

[0064] Furthermore, after determining the number of transmission channels, it is necessary to determine the number of corresponding FEC working areas. It is worth noting that during the manufacturing process of the data transmitter's transmission interface, multiple FEC working areas will be pre-manufactured to ensure sufficient redundancy to adapt to different scenarios. For example, 10 FEC working area circuits can be pre-manufactured during the design and manufacturing process, allowing the transmission interface to support a maximum of 10 transmission channels. This ensures that the transmission interface meets the needs of various scenarios. Of course, the redundancy of the FEC working area circuits can also be set to other values, which are not limited in this application.

[0065] S502: Distribute the data on the transmission channel evenly to each of the plurality of FEC work areas.

[0066] Specifically, the data transmitted on each transmission channel can be referred to as a data stream. To facilitate subsequent processing of the data stream, it can be segmented into multiple data blocks in units of X characters. The value of X can be flexibly set as needed, and this application does not impose any limitations on it. It is worth noting that the data stream on the transmission channel is generally segmented based on the amount of data processed by each FEC work area at one time. That is, the value of X is equal to the amount of data processed by each FEC work area at one time, and the amount of data processed by the FEC work area at one time is the amount of data received by the FEC work area per unit time.

[0067] For example, such as Figure 6 As shown, this diagram illustrates the process of dividing a data stream on a transmission channel into data blocks. Each small box in the diagram represents a data unit, where M / N represents the Nth data unit in a data block on channel M. For example, 0 / 0 represents the 0th data unit in a data block on channel 0, and 0 / 2 represents the 2nd data unit in a data block on channel 0.

[0068] It should be understood that in the process of evenly distributing data on a transmission channel to multiple FEC work areas, it is necessary to ensure that each FEC work area receives the same amount of data per unit time. For example, if there are 3 transmission channels and 3 FEC work areas, and a data block on each transmission channel contains 100 characters, then during distribution, the 300 characters contained in the 3 data blocks need to be distributed to the 3 FEC work areas simultaneously, so that each FEC work area receives 100 characters. Furthermore, in the specific distribution, the transmission channels are not mapped one-to-one with the FEC work areas. Allocating all the characters contained in a data block on a certain transmission channel to a single FEC work area would result in all the data processed by that FEC work area coming from the same transmission channel. Instead, the characters contained in a data block on any transmission channel are distributed one-to-one to multiple FEC work areas, so that each FEC work area processes a portion of the data in that data block. For example, in the above... Figure 6 In the diagram, each small square is a different color, indicating that the data unit will be assigned to a different FEC work area.

[0069] S503: Process the data received by each of the multiple FEC work areas.

[0070] Specifically, after receiving the data allocated by each transmission channel, each FEC work area begins to process it, with each processing session involving X characters of data.

[0071] It is worth noting that if the FEC work area is the FEC work area of ​​the data sending end, the FEC work area will perform calculations on the received X characters to obtain Y FEC check bits, and these Y FEC check bits will be mapped to each transmission channel. For example, the Y check bits can be mapped one by one to multiple transmission channels, and then the mapping can be repeated multiple times until all Y check bits are mapped. The specific process is similar to the allocation of characters on the transmission channels to the FEC work area, and can be referred to the method described above, which will not be repeated here. The value of Y is related to the selected check algorithm. Using different check algorithms may result in different Y values. This application does not limit the specific check algorithm to be used.

[0072] For example, such as Figure 7As shown, the FEC work area receives data allocated by each transmission channel, such as the 0th data unit (0 / 0) in a data block on channel 0, the 1st data unit (2 / 1) in a data block on channel 2, and the 2nd data unit (1 / 2) in a data block on channel 1. Then, it performs calculations on this data to obtain Y FEC check bits, where M / PS N represents one FEC check bit. This check bit will be mapped to the Nth FEC check bit on channel M. The Y FEC check bits obtained by the FEC work area will be mapped to different transmission channels. Furthermore, to facilitate data processing and simplify the data processing procedure, the data stream transmitted on each transmission channel can be further structurally divided. Specifically, for each transmission channel, the data structure composed of the X characters contained in each data block and the Y FEC check bits mapped from each FEC work area is called an FEC block. The specific structure of an FEC block is as follows: Figure 8 As shown, 0 / 0 represents the 0th data unit in an FEC block on channel 0, and 0 / PS 0 represents the 0th parity bit in an FEC block on channel 0.

[0073] Correspondingly, if the FEC work area is the FEC work area of ​​the data receiving end, the data received by the FEC work area includes X characters allocated from each transmission channel and Y FEC check bits (that is, the total amount of data received by the FEC work area is the same as the amount of data in an FEC block). The FEC work area uses the Y FEC check bits to check and correct the X characters. The specific check and correction process is similar to the existing check and correction algorithm, and will not be described in detail here.

[0074] Furthermore, to perform character delimiting, link transport block delimiting, inter-channel alignment, and initialization of scrambling seeds on the data transmitted on each transmission channel, a data sequence, namely a scramble reset sequence (SR), needs to be inserted between the link transport blocks transmitted on the transmission channel. One link transport block (LT Block) contains Z FEC blocks, and the value of Z can be set as needed; this application does not limit this value. It should be noted that the SR inserted between two LT Blocks will not be encoded; that is, the data in the SR will not be allocated to the FEC working area for processing. For example, the data structure transmitted on a transmission channel is as follows: Figure 9 As shown, an SR is inserted between link transport block 1 and link transport block 2, and both contain Z FEC blocks.

[0075] To better illustrate the mapping relationship between the FEC work area and the data on the transmission channels, we will use an example of a transmission interface containing three transmission channels and three FEC work areas. Figure 10 As shown, the data layout structure on transmission channels 0, 1, and 2 is consistent. Different link transmission blocks are separated by using SR as the link transmission block boundary. Each link transmission block contains Z FEC blocks, and each FEC block contains X characters and Y FEC parity bits. FEC working area 0, FEC working area 1, and FEC working area 2 calculate Y FEC parity bits when they receive X characters mapped from transmission channels 0, 1, and 2. 0-X-1 represent the data characters allocated by the transmission channel, and PS0-PSY-1 represent the Y parity bits calculated based on 0-X-1 characters. The arrows from FEC blocks on the transmission channel to FEC working areas represent data from different FEC blocks mapped to different FEC working areas. For example, the 0th data unit of FEC block 0 on transmission channel 0 is mapped to FEC working area 2, the 1st data unit of FEC block 0 on transmission channel 1 is mapped to FEC working area 0, and the 2nd data unit of FEC block 0 on transmission channel 2 is mapped to FEC working area 1. The arrows from FEC working areas to FEC blocks on the transmission channel represent FEC parity bits calculated in different FEC working areas mapped to different FEC blocks. For example, the 2nd parity bit on FEC working area 0 is mapped to the 2nd FEC parity bit of FEC block 0 on transmission channel 0, the 1st parity bit on FEC working area 1 is mapped to the 1st FEC parity bit of FEC block 0 on transmission channel 0, and the 0th parity bit on FEC working area 2 is mapped to the 0th FEC parity bit of FEC block 0 on transmission channel 0.

[0076] It can be seen that when the number of FEC work areas used matches the number of transmission channels used by the transmission interface, the amount of data processed by each FEC work area is the same. Therefore, the size of the FEC block on each transmission channel is fixed and the same, and the boundary of the link transmission block on each transmission channel is also the same. That is, the data arrangement structure on each transmission channel is the same. This can effectively reduce the size and design complexity of the interface circuit and reduce production costs.

[0077] Based on the aforementioned FEC block structure and LT block structure, taking a transmission interface containing two transmission channels that can flexibly select the number of channels to transmit data as needed as an example, the data processing process under different channel numbers is explained.

[0078] like Figure 11AAs shown, in channel 1 mode, the X characters to be encoded contained in the FEC block on channel 0 are sequentially sent to FEC work area 0 for processing. FEC work area 0 calculates Y FEC parity bits and inserts these Y FEC parity bits immediately following the FEC block on channel 0. The final transmitted data structure is as follows. Figure 11B As shown. In 2-channel transmission mode, the data of the FEC blocks from the two channels are interleaved onto FEC work area 0 and FEC work area 1, as follows. Figure 12A As shown, the X characters to be encoded contained in the FEC block on channel 0 are evenly distributed to FEC work areas 0 and 1 for processing. For example, the 0th character is sent to FEC work area 0 and the 1st character is sent to FEC work area 1. Similarly, the X characters to be encoded contained in the FEC block on channel 1 are also evenly distributed to FEC work areas 0 and 1 for processing. For example, the 0th character is sent to FEC work area 1 and the 1st character is sent to FEC work area 0. After FEC work areas 0 and 1 complete the data processing, the calculated Y FEC parity bits are evenly mapped to the FEC blocks on channels 0 and 1. The transmitted data structure is as follows. Figure 12B As shown, the data layout structure on the two channels is the same, the SR position is also the same, and the amount of data contained in each link transmission block on channel 0 is the same as the amount of data contained in each link transmission block on channel 1.

[0079] Based on the above, it can be observed that in the 1-channel transmission mode, data on one transmission channel is allocated to one FEC work area, and in the 2-channel transmission mode, data on two transmission channels is allocated to two FEC work areas. Therefore, for each FEC work area, regardless of which channel transmission mode is selected, the amount of data received per unit time is the same. Thus, whether it is 1-channel transmission, 2-channel transmission, or even more transmission channels, the data volume and boundaries of the FEC block, the data volume and boundaries of the LT block, and the periodicity of each channel are the same. That is, the data arrangement structure on each channel is consistent, which facilitates data processing using a unified circuit, reduces the size and design complexity of the interface circuit, and effectively reduces production costs.

[0080] The methods of the embodiments of this application have been described in detail above. In order to facilitate better implementation of the above solutions of the embodiments of this application, relevant equipment for cooperating in implementing the above solutions is also provided below.

[0081] See Figure 13 , Figure 13 This is a schematic diagram of the structure of a data processing device 100 provided in an embodiment of this application. The data processing device 100 includes a determining unit 110, an allocation unit 120, and a processing unit 130. Wherein:

[0082] The determining unit 110 is used to determine the number of transmission channels for transmitting data, and to determine multiple FEC work areas based on the number of transmission channels. The number of multiple FEC work areas is the same as the number of transmission channels. The transmission channels are used to transmit data, and the FEC work areas are used to perform verification and error correction on the data.

[0083] The allocation unit 120 is used to evenly distribute the data on the transmission channel to each of the plurality of FEC work areas;

[0084] The processing unit 130 is used to process the data received by each of the multiple FEC work areas.

[0085] As an example, the allocation unit 120 is specifically used to: divide the data on each transmission channel into multiple data blocks, wherein each data block contains X characters, where X is a positive integer greater than 1; and evenly distribute the X characters contained in each data block to the multiple FEC work areas.

[0086] As one embodiment, the processing unit 130 is specifically used for: if the plurality of FEC working areas are in the encoding state, performing calculations on each of the plurality of FEC working areas for every X characters received to obtain Y FEC check bits corresponding to the X characters; or if the plurality of FEC working areas are in the decoding state, performing error correction on the X characters using the Y FEC check bits corresponding to each of the X characters received.

[0087] As an example, the processing unit 130 is further configured to insert a data sequence between the transmission blocks transmitted on each transmission channel in the transmission channel, wherein the transmission block includes Z data blocks, and the data sequence is used to delimit the data transmitted on the transmission channel, wherein Z is a positive integer greater than 1.

[0088] It is understood that the determining unit 110, the allocation unit 120, and the processing unit 130 in the embodiments of this application can be implemented by a processor or processor-related circuit components, and the data processing device can perform operations such as Figure 5 The steps performed by the data transmitter or data receiver in the method shown are not elaborated here; please refer to [link to relevant documentation] for details. Figure 5 And related content.

[0089] See Figure 14 , Figure 14 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Figure 14As shown, the data processing device 200 includes a processor 210, a communication interface 220, and a memory 230, which are interconnected via an internal bus 240.

[0090] The data processing device 200 may be Figure 4 The data transmitter or data receiver in the system. Figure 4 The functions performed by the data transmitter or data receiver are actually executed by the processor 210 of the data transmitter or data receiver.

[0091] The processor 210 may consist of one or more general-purpose processors, such as a central processing unit (CPU), or a combination of a CPU and hardware chips. The hardware chips may be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The PLDs may be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof.

[0092] Bus 240 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Bus 240 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 14 The symbol is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0093] The memory 230 may include volatile memory, such as random access memory (RAM); the memory 230 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 230 may also include combinations of the above types. The program code may be used to implement the functional units shown in the data processing device 100, or to implement... Figure 5 The method steps shown in the embodiment are performed by a data transmitter or a data receiver.

[0094] This application also provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the program can implement some or all of the steps described in the above method embodiments, and implement the above... Figure 13 The function of any one of the described functional units.

[0095] This application also provides a computer program product that, when run on a computer or processor, causes the computer or processor to perform one or more steps of any of the methods described above. If the constituent units of the aforementioned devices are implemented as software functional units and sold or used as independent products, they can be stored in the computer-readable storage medium.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0097] It should also be understood that, in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0098] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0099] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0100] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A design method for a forward error correction code (FEC), characterized in that, include: The number of transmission channels for transmitting data is determined, and multiple FEC work areas are determined based on the number of transmission channels. The number of multiple FEC work areas is the same as the number of transmission channels. The transmission channels are used to transmit data, and the FEC work areas are used to verify and correct the data. Distributing the data on the transmission channel evenly to each of the multiple FEC work areas includes: dividing the data on each transmission channel into multiple data blocks, wherein each data block contains X characters, where X is a positive integer greater than 1, and distributing the X characters contained in each data block to the multiple FEC work areas one by one. The multiple FEC work areas are used to process the data received by each.

2. The method as described in claim 1, characterized in that, The multiple FEC work areas are used to process the data received by each, including: If the plurality of FEC work areas are in an encoding state, each of the plurality of FEC work areas performs a calculation every X characters received to obtain Y FEC check bits corresponding to the X characters; or... If the plurality of FEC working areas are in the decoding state, each of the plurality of FEC working areas uses Y FEC check bits corresponding to each X received characters to perform check and error correction on the X characters.

3. The method as described in claim 1 or 2, characterized in that, After processing the received data using the multiple FEC work areas, the method further includes: A data sequence is inserted between the transmission blocks transmitted on each of the transmission channels, wherein each transmission block comprises Z data blocks, and the data sequence is used to delimit the data transmitted on the transmission channel, wherein Z is a positive integer greater than 1.

4. The method according to any one of claims 1-3, characterized in that, The transmission blocks transmitted on each transmission channel include a contention reset sequence SR. Each transmission block contains Z FEC blocks, and each FEC block includes X characters and Y FEC check bits, where X, Y, and Z are positive integers greater than 1.

5. A data processing apparatus, characterized in that, include: A determining unit is configured to determine the number of transmission channels for transmitting data, and to determine multiple FEC work areas based on the number of transmission channels, wherein the number of multiple FEC work areas is the same as the number of transmission channels, wherein the transmission channels are used for transmitting data, and the FEC work areas are used for verifying and correcting errors on the data; The allocation unit is used to evenly distribute the data on the transmission channel to each of the multiple FEC work areas, including: dividing the data on each transmission channel into multiple data blocks, wherein each data block contains X characters, where X is a positive integer greater than 1, and allocating the X characters contained in each data block to the multiple FEC work areas one by one. The processing unit is used to process the data received by each of the multiple FEC work areas.

6. The data processing apparatus as described in claim 5, characterized in that, The processing unit is specifically used for: If the plurality of FEC working areas are in the encoding state, each of the plurality of FEC working areas is used to perform calculations for every X characters received, to obtain Y FEC check bits corresponding to the X characters; or If the plurality of FEC working areas are in the decoding state, each of the plurality of FEC working areas uses Y FEC check bits corresponding to each X received characters to perform check and error correction on the X characters.

7. The data processing apparatus as described in claim 5 or 6, characterized in that, The processing unit is further configured to insert a data sequence between the transmission blocks transmitted on each transmission channel in the transmission channel, wherein the transmission block includes Z data blocks, and the data sequence is used to delimit the data transmitted on the transmission channel, wherein Z is a positive integer greater than 1.

8. The data processing apparatus according to any one of claims 5-7, characterized in that, The transmission blocks transmitted on each transmission channel include a contention reset sequence SR. Each transmission block contains Z FEC blocks, and each FEC block includes X characters and Y FEC check bits, where X, Y, and Z are positive integers greater than 1.

9. A data processing apparatus, characterized in that, The device includes a processor and a transmission interface, the processor being configured to invoke computer instructions stored in a memory, causing the device to perform the method according to any one of claims 1-4.

10. A computer-readable storage medium storing a computer program that, when executed by a computer or processor, implements the method of any one of claims 1-4.

11. A computer program product comprising instructions that, when executed by a computer or processor, implement the method of any one of claims 1-4.

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