Bioelectric detection channel circuit and invasive semiconductor brain-machine device

Abstract

The application provides a bioelectric signal detection channel circuit and an invasive semiconductor brain-computer device, and relates to the field of integrated circuits.The bioelectric signal detection channel circuit comprises a voltage-current conversion unit, a signal counting unit, a count sampling unit, a residual control unit and a residual counting unit.The voltage-current conversion unit converts the received bioelectric signal into a corresponding current signal.The signal counting unit counts the pulse signal which is in a linear relationship with the current signal.The count sampling unit samples the counting result.The residual control unit generates a first enable signal and a second enable signal, and transmits the first enable signal and the second enable signal to the count sampling unit and the residual counting unit respectively.The residual counting unit counts the residual.The bioelectric voltage value is obtained by calculation.The application improves the detection accuracy, reduces the size and power consumption, and better inhibits the influence of motor heating on the brain temperature.The application meets the bioelectric signal detection and is especially suitable for the invasive brain-computer interface.The overall circuit structure has high integrability and expandability, and can better improve the probe resolution.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a bioelectric signal detection channel circuit and an invasive semiconductor brain-computer interface device. Background Technology

[0002] Living cells or tissues constantly generate a series of electrical signals that reflect or control the state of life. These signals are called bioelectric signals. Common bioelectric signals include electrocardiogram (ECG), electroencephalogram (EEG), and electromyogram (EMG).

[0003] By detecting bioelectric signals, biological information can be collected to understand the body's condition to some extent without instigating wounds. It also allows for deeper, more detailed signal collection from within the body for further research, exploring how various bodily behaviors are controlled. Furthermore, bioelectric signal detectors, as the front-end for collecting bioelectric signals, can assist scientists in studying the pathology of various diseases and developing neural prostheses for nerve repair.

[0004] However, current detection channel circuits used to detect bioelectric signals are large in size and consume a lot of power. Furthermore, because they calculate bioelectric voltage values ​​using a single counting result, their detection accuracy is low. How to improve detection accuracy as much as possible while reducing size and power consumption is a pressing problem that needs to be solved. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a bioelectric signal detection channel circuit and an invasive semiconductor brain-computer interface that solves or partially solves the above problems.

[0006] The first aspect of this invention provides a bioelectric signal detection channel circuit, which includes: multiple channel unit circuits and a base, each channel unit including: a voltage-to-current conversion unit, a pulse signal conversion unit, a signal counting unit, and a margin control unit;

[0007] The base includes: a counting sampling unit and a margin counting unit;

[0008] The voltage-to-current conversion unit converts the received bioelectric signal into a corresponding current signal and transmits it to the pulse signal conversion unit;

[0009] The pulse signal conversion unit converts the current signal into a pulse signal that is linearly related to the current signal.

[0010] The signal counting unit counts the pulse signals;

[0011] During each quantization cycle, the counting sampling unit uses a first enable signal from the margin control unit to sample the counting result of the signal counting unit, and obtains a first count value based on the sampling results of two adjacent quantization cycles.

[0012] During each quantization cycle, the margin control unit generates the first enable signal and the second enable signal using the sampling window signal and the pulse signal, and transmits them to the counting sampling unit and the margin counting unit, respectively.

[0013] Within each quantization cycle, the margin counting unit counts the margin of the counting time of the pulse signal based on the second enable signal, and obtains a second count value based on the sampling results of two adjacent quantization cycles.

[0014] The signal counting unit and the margin counting unit respectively transmit the first count value and the second count value to the external processing unit so that the external processing unit can calculate the bioelectric voltage value.

[0015] Among them, multiple channel units correspond to one base;

[0016] The margin refers to the residual amount of the quantization period.

[0017] Optionally, the voltage-to-current conversion unit includes: a high-pass filter and a transconductance module;

[0018] The high-pass filter receives the bioelectric signal and the reference signal, filters the bioelectric signal to obtain a precise voltage signal, and transmits it to the transconductance module.

[0019] The transconductance module converts the precise voltage into a corresponding current signal and transmits it to the pulse signal conversion unit.

[0020] Optionally, the counting sampling unit uses a first enable signal from the margin control unit to sample the counting result of the signal counting unit, and obtains a first count value based on the sampling results of two adjacent quantization cycles in the following manner:

[0021] Within the sampling window of the nth quantization cycle, the counting sampling unit receives the first enable signal and samples the first reading of the signal counting unit when the first pulse of the pulse signal arrives within the sampling window;

[0022] Within the sampling window of the (n+1)th quantization cycle, the counting sampling unit uses the sampling window signal to sample the second reading of the signal counting unit when the first pulse of the pulse signal arrives within the sampling window;

[0023] The difference between the second reading and the first reading is calculated to obtain the first count value.

[0024] Optionally, the margin control unit generates the first enable signal and the second enable signal using the sampling window signal, and transmits them to the counting sampling unit and the margin counting unit respectively, in the following manner:

[0025] The margin control unit receives the sampling window signal;

[0026] When the rising edge of the sampling window signal arrives, the margin control unit generates a first second enable signal and transmits the first second enable signal to the margin counting unit.

[0027] When the first pulse of the pulse signal arrives within the sampling window, the margin control unit generates a first enable signal and a second enable signal, and transmits the first enable signal to the counting sampling unit and the second enable signal to the margin counting unit.

[0028] Optionally, the margin counting unit counts the margin of the counting time of the pulse signal based on the second enable signal, and obtains the second count value based on the sampling results of two adjacent quantization cycles in the following ways:

[0029] The margin counting unit uses the global high-frequency clock as its input. When it receives the first second enable signal in the nth quantization cycle, it starts counting and ends counting when it receives the second second enable signal, thus obtaining the third reading.

[0030] The margin counting unit uses the global high-frequency clock as its input. When it receives the first second enable signal in the (n+1)th quantization cycle, it starts counting and ends counting when it receives the second second enable signal, thus obtaining the fourth reading.

[0031] The difference between the fourth reading and the third reading is calculated to obtain the second count value.

[0032] Optionally, if the margin control unit generates the first enable signal when the rising edge of the first pulse arrives, the first enable signal is transmitted to the counting and sampling unit after a preset delay.

[0033] If the margin control unit generates the first enable signal when the rising edge of the first pulse arrives, the first enable signal is directly transmitted to the counting and sampling unit after it is generated.

[0034] Optionally, the formula for calculating the bioelectric voltage value is:

[0035]

[0036] In the above formula, V s represents the voltage value of the bioelectric signal, f osc K represents the frequency of the pulse signal. n+1 This indicates that within the sampling window of the (n+1)th quantization cycle, the counting sampling unit uses the sampling window signal to sample and obtain the second reading of the signal counting unit when the first pulse arrives, K. n This indicates that within the sampling window of the nth quantization cycle, the counting sampling unit receives the first enable signal and samples the first reading of the signal counting unit when the first pulse arrives, Q. n+1 Q represents the fourth indicator. n T represents the third reading, T0 represents the quantization period duration, and T... MCK This represents the period of the global high-frequency clock.

[0037] Optionally, the pulse signal conversion unit includes: a folded integrator or a flow-controlled oscillator;

[0038] The product of the maximum oscillation frequency of the pulse signal and the duration of the quantization period is less than the range of the signal counting unit;

[0039] The duration of the high level of the sampling window signal includes one and a half cycles of the pulse signal.

[0040] Optionally, a first NMOS transistor and a second NMOS transistor are disposed between the signal counting unit and the counting sampling unit; the counting sampling unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

[0041] The gate of the first NMOS transistor receives the reading of the signal counting unit, the source is grounded, and the drain is connected to the source of the second NMOS transistor;

[0042] The gate of the second NMOS transistor receives the window sampling signal, and its drain is connected to the drain of the third NMOS transistor and the source of the fourth NMOS transistor, respectively.

[0043] The gate of the fourth NMOS transistor receives a first bias voltage, and its drain is connected to the drain of the first PMOS transistor, the gate of the third PMOS transistor, and the gate of the fifth NMOS transistor, respectively.

[0044] The source of the third NMOS transistor is grounded;

[0045] The gate of the first PMOS transistor receives a second bias voltage, and the source receives a power supply voltage.

[0046] The source of the third PMOS transistor receives the power supply voltage, and its drain is connected to the source of the second PMOS transistor.

[0047] The gate of the second PMOS transistor receives the base readout signal, and its drain is connected to the drain of the sixth NMOS transistor and the D flip-flop.

[0048] The gate of the sixth NMOS transistor receives the inverted signal of the base readout signal, and its source is connected to the drain of the fifth NMOS transistor, while the source of the fifth NMOS transistor is grounded.

[0049] The first PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor constitute a judgment structure. By setting the first bias voltage and the second bias voltage, the pull-up capability of the judgment structure is greater than the pull-down capability.

[0050] A second aspect of the present invention provides an invasive semiconductor brain-computer interface device, the invasive semiconductor brain-computer interface device including a bioelectrical signal detection channel circuit as described in any of the first aspects.

[0051] The bioelectric signal detection channel circuit provided by this invention includes a voltage-to-current conversion unit that converts the received bioelectric signal into a corresponding current signal and transmits it to a pulse signal conversion unit; the pulse signal conversion unit converts the current signal into a pulse signal that is linearly related to the current signal; and a signal counting unit counts the pulse signals.

[0052] Within each quantization cycle, the counting sampling unit uses the first enable signal from the margin control unit to sample the counting result of the signal counting unit, and obtains the first count value based on the sampling results of two adjacent quantization cycles; within each quantization cycle, the margin control unit uses the sampling window signal and the pulse signal to generate the first enable signal and the second enable signal, and transmits them to the counting sampling unit and the margin counting unit, respectively.

[0053] Within each quantization cycle, the margin counting unit counts the margin of the pulse signal counting time based on the second enable signal, and obtains the second count value based on the sampling results of two adjacent quantization cycles; the signal counting unit and the margin counting unit respectively transmit the first count value and the second count value to the external computing unit so that the external computing unit can calculate the bioelectric voltage value.

[0054] This invention samples the count margin of the pulse signal, improving conversion accuracy compared to a single count result, thereby enhancing detection precision. Furthermore, most of the area of ​​the margin count is transferred to the base, maintaining detection accuracy without increasing the area of ​​the detection channel unit, reducing size and power consumption, and effectively suppressing the impact of motor heating on brain temperature. It meets the requirements for bioelectrical signal detection and is particularly suitable for invasive brain-computer interfaces. The overall circuit structure has high integrability and scalability, further improving probe resolution. Attached Figure Description

[0055] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of a preferred bioelectric signal detection channel circuit structure in an embodiment of the present invention;

[0057] Figure 2 These are timing diagrams of various signals in embodiments of the present invention;

[0058] Figure 3 This is a schematic diagram of the circuit structure of the folded integrator in an embodiment of the present invention. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] The bioelectric signal detection channel circuit of this invention includes: multiple channel unit circuits and a base. Each channel unit includes: a voltage-to-current conversion unit, a pulse signal conversion unit, a signal counting unit, and a margin control unit. The base includes: a counting sampling unit and a margin counting unit. Generally, invasive semiconductor brain-computer interfaces (BCIs) use a needle to penetrate the human brain to obtain bioelectric signals. The front end of the needle is equipped with a large number of single channels (i.e., channel unit circuits) to fully acquire multi-directional and different types of bioelectric signals from the brain. However, the rear end of the needle is larger than the front end, which is not conducive to brain penetration; therefore, a base is placed at the rear end of the needle. Generally, multiple channel unit circuits correspond to one base. The specific number of channel unit circuits corresponding to one base can be determined according to actual needs, for example: 128 channel unit circuits corresponding to one base, 64 channel unit circuits corresponding to one base, etc.

[0061] In this embodiment of the invention, during the operation of the bioelectric signal detection channel circuit, the voltage-to-current conversion unit converts the received bioelectric signal into a corresponding current signal and transmits it to the pulse signal conversion unit. Upon receiving the current signal, the pulse signal conversion unit converts it into a pulse signal that is linearly related to the current signal.

[0062] The signal counting unit can directly count the pulse signal, and this counting is continuous. During each quantization cycle, the counting sampling unit in the base uses the first enable signal from the margin control unit to sample the counting result of the signal counting unit, and obtains the first count value based on the sampling results of two adjacent quantization cycles.

[0063] Similarly, within each quantization cycle, the margin control unit uses the sampling window signal and the pulse signal to generate a first enable signal and a second enable signal, which are then transmitted to the counting sampling unit and the margin counting unit in the base, respectively.

[0064] Within each quantization cycle, when the margin counting unit receives the second enable signal, it counts the margin of the pulse signal's counting time based on the second enable signal, and obtains the second count value based on the sampling results of two adjacent quantization cycles. Here, the margin refers to the residual amount of the quantization cycle duration, which can also be understood as the time from the rising edge of the sampling window signal to the arrival of the first pulse of the pulse signal within the sampling window. The margin exists because the frequency of the pulse signal is related to the magnitude of the bioelectric signal. Therefore, the rising and falling edges of the pulse signal are not strictly aligned with the rising and falling edges of the sampling window signal. This results in the counting time of the signal counting unit not being strictly the same as the quantization cycle time, leaving a margin. This margin needs to be accurately obtained to ensure the accuracy of the bioelectric voltage value obtained in subsequent calculations. Otherwise, if the calculation is based solely on the count value of the signal counting unit, the obtained bioelectric voltage will differ significantly from the actual bioelectric voltage, naturally resulting in lower detection accuracy of the detection channel circuit.

[0065] After the signal counting unit and the margin counting unit obtain the first count value and the second count value respectively, they transmit the first count value and the second count value to the external processing unit so that the external processing unit can calculate the bioelectric voltage value.

[0066] In one possible embodiment, the voltage-to-current conversion unit includes: a high-pass filter and a transconductance module; the high-pass filter receives a bioelectric signal and a reference signal, filters the bioelectric signal to obtain a precise voltage signal and transmits it to the transconductance module; the transconductance module converts the precise voltage into a corresponding current signal and transmits it to the pulse signal conversion unit.

[0067] During operation, the counting sampling unit uses the first enable signal from the margin control unit to sample the counting result of the signal counting unit, and the preferred method for obtaining the first count value based on the sampling results of two adjacent quantization cycles includes:

[0068] Within the sampling window of the nth quantization cycle, the counting sampling unit receives the first enable signal and samples the first reading of the signal counting unit when the first pulse arrives; within the sampling window of the (n+1)th quantization cycle, the counting sampling unit uses the sampling window signal to sample the second reading of the signal counting unit when the first pulse arrives; that is, in two adjacent quantization cycles, two readings are sampled respectively, and finally the difference between the second reading and the first reading is calculated to obtain the first count value.

[0069] A preferred method for the margin control unit to generate a first enable signal and a second enable signal using the sampling window signal, and transmit them to the counting sampling unit and the margin counting unit respectively, includes:

[0070] The margin control unit receives the sampling window signal. When the rising edge of the sampling window signal arrives, the margin control unit generates a first second enable signal and transmits it to the margin counting unit. When the first pulse arrives, the margin control unit generates a first enable signal and a second second enable signal, transmitting the first enable signal to the counting sampling unit and the second enable signal to the margin counting unit. That is, within one quantization cycle, the margin control unit generates two second enable signals: one when the rising edge of the sampling window signal arrives and the other when the first pulse arrives.

[0071] A preferred method for the margin counting unit to count the margin of the pulse signal's counting time based on the second enable signal, and to obtain the second count value based on the sampling results of two adjacent quantization cycles, includes:

[0072] The margin counting unit uses the global high-frequency clock as its input. It starts counting when it receives the first second enable signal in the nth quantization cycle, and stops counting when it receives the second second enable signal, thus obtaining the third reading.

[0073] The margin counting unit uses the global high-frequency clock as its input. It begins counting when it receives the first second enable signal within the (n+1)th quantization cycle and ends counting when it receives the second second enable signal, thus obtaining the fourth reading. In other words, within any quantization cycle, the margin counting unit starts counting when it receives the second enable signal for the first time and ends counting when it receives the second enable signal for the second time, obtaining one reading. Finally, the difference between the fourth and third readings is calculated to obtain the second count value.

[0074] Considering the inherent characteristics of the signal counting unit, which also flips at the rising edge of the first pulse, if the counting sampling unit samples the signal counting unit's reading using the first enable signal generated at the rising edge of the first pulse, it might sample the flipping signal, potentially causing bit errors. To avoid bit errors, an additional delay unit is needed to generate sufficient delay to ensure the signal counting unit finishes flipping. Therefore, the margin control unit generates the first enable signal at the rising edge of the first pulse, then delays its transmission, transmitting it to the counting sampling unit after a preset delay. This sampling approach increases the external circuitry. A better solution is for the margin control unit to generate the first enable signal at the falling edge of the first pulse, without delay. In this case, the first enable signal can be transmitted directly to the counting sampling unit immediately after generation.

[0075] To more clearly explain and illustrate the bioelectric signal detection channel circuit of the embodiments of the present invention, a preferred structural form is used as an example to describe the bioelectric signal detection channel circuit of the embodiments of the present invention. (Refer to...) Figure 1 The diagram shows a preferred circuit structure for a bioelectric signal detection channel. The voltage-to-current conversion unit includes a high-pass filter (HP) and a transconductance module (GM). The pulse signal conversion unit includes a folded integrator or a current-controlled oscillator. Figure 1 The example shown is the folded integrator PFM. Figure 1 Multiple channel unit circuits are located at the handle end (i.e., the handle end of the invasive detection device), and the peripheral circuit is the base.

[0076] The voltage-to-current conversion unit operates as follows: the high-pass filter HP receives the bioelectric signal V. s and reference voltage signal V CM For bioelectrical signals V s Filtering is performed to remove unwanted low-frequency stimulus artifacts from the bioelectrical signal, thereby obtaining a precise voltage signal V. in The signal is then transmitted to the transconductance module GM. Since signals smaller than 1Hz need to be filtered out, the resistance value in the high-pass filter needs to be in the hundreds of megahertz range. Generally, pseudo-resistors are used instead of physical resistors to reduce the area of ​​the high-pass filter.

[0077] Transconductance module GM for precise voltage V in The conversion is performed to obtain the corresponding current signal I. O The signal is then transmitted to the folded integrator PFM, and the transconductance module operates in the subthreshold region to reduce power consumption. Therefore, the bioelectrical signal V... s and the corresponding current signal I O The following relationship exists between them:

[0078] ΔI o =G m ·ΔV s

[0079] G in the above formula m ΛI represents the transconductance value of the transconductance module GM. o ΔV represents the deviation of the current signal. S Represents bioelectrical signal V s and the reference voltage signal V CM The deviation between them.

[0080] The current signal I obtained by the transconductance module GM conversion O The folded integrator PFM is used for folding and integration to obtain the pulse signal V. osc Pulse signal V osc frequency f osc With input current I O It is a linear relationship, that is:

[0081] f osc ∝I o ∝ΔV s

[0082] Obtain pulse signal V osc Then, in each quantization cycle, the duration T o Inside, the signal counting unit Cu is used to count the pulse signal V. osc Continuous counting: Since there is an initial sampling window signal CS, if the counter reading is K when the first pulse arrives within the sampling window of the nth quantization cycle... n The counter reading when the first pulse arrives within the sampling window of the (n+1)th quantization cycle is K. n+1 Then the accumulated count in the nth quantization period is ΔK. n =f osc ·T o =K n+1 -K n Using counting and bioelectrical signals V s The first-order relationship between can be used to calculate the bioelectric voltage value through counting results.

[0083] Due to pulse signal V osc Frequency and bioelectric signal V s related to pulse signal V osc The rising and falling edges are not strictly aligned with the sampling window signal CS, therefore the counting time of the signal counting unit Cu is not strictly the same as the quantization period time T. o Similarly, a margin control unit Mgtu and a margin counting unit Mgcu were also designed to collect the margin during the pulse signal counting time, that is, the time Δt from the start of the sampling window to the arrival of the first pulse within the sampling window. n Then we have:

[0084] ΔK n =f osc ·(T o -Δt n +Δt n+1 ) = K n+1 -K n

[0085] Based on the global high-frequency clock MCK and the margin unit Mgcu, the global high-frequency clock MCK serves as the input to the margin unit Mgcu. When the rising edge of the sampling window signal CS arrives, the margin control unit Mgcu generates the first second enable signal ΔTDC, and the margin counting unit Mgcu starts counting. When the first pulse arrives within the sampling window time, a first enable signal QSH is generated in the channel. This first enable signal causes the counting sampling unit Csu to sample the reading K of the signal counting unit Cu. n Deposit into QS <1> ~QS <n>At the node, the margin control unit Mgtu generates the first second enable signal ΔTDC, which can also be understood as causing the first second enable signal ΔTSC to flip, thereby causing the margin counting unit Mgcu to stop counting, and finally the reading Q of the margin counting unit Mgcu. n have:

[0086] Δt n =T MCK ·Q n

[0087] In the above formula, T MCK K represents the period of the global high-frequency clock. n+1 and Q n+1 The same method is used in the sampling window of the next quantization cycle. The formula for calculating the final detected bioelectric voltage value is:

[0088]

[0089] In the above formula, V s represents the bioelectric signal V s The voltage value of , f osc Indicates pulse signal V osc The frequency, K n+1 This indicates that within the sampling window of the (n+1)th quantization cycle, the counting sampling unit samples and obtains a reading, K. n Q represents a reading obtained by the counting sampling unit within the sampling window of the nth quantization cycle. n+1 This represents a reading obtained by the margin counting unit within the sampling window of the (n+1)th quantization cycle, Q. n This represents a sample obtained by the margin counting unit within the sampling window of the nth quantization cycle, where T0 represents the quantization cycle duration, and T... MCK This represents the period of the global high-frequency clock.

[0090] The entire workflow described above can be combined Figure 2 The timing diagrams of the various signals shown can be better understood. Figure 2 In this context, CK represents the external clock signal, CS represents the sampling window signal, and osc represents the pulse signal. Figure 2 The second enable signal QSH is generated at the falling edge of the first pulse in the pulse signal osc. Margin = Δt n+1 -Δt n .

[0091] It should be noted that if the range of the signal counting unit is small, the product of the maximum oscillation frequency of the pulse signal and the quantization period must be less than the range of the signal counting unit. Otherwise, the signal counting unit will experience an overflow error, causing subsequent calculation results to be incorrect. Assuming the high-level duration of the window signal is t0 and the total number of channel unit circuits is N, then the quantization period T... o =N*t0. If the signal counting unit is a 9-bit counter, its continuous integration does not reset. Therefore, to prevent the counter range from overflowing, the maximum oscillation frequency f of the pulse signal should be guaranteed. max satisfy: Furthermore, for accuracy, the high-level duration of the sampling window signal must contain at least one and a half cycles of the pulse signal, which is equivalent to the minimum oscillation frequency f of the pulse signal. min satisfy:

[0092] In addition, to ensure the timeliness of data processing, the data obtained by all channel unit circuits share a common data bus and are sequentially transmitted to the base circuit for further processing in a pipeline manner. The sampling window time of each channel unit circuit is staggered to control the switching between the signal and the data bus of each channel unit circuit.

[0093] In this embodiment of the invention, a novel circuit structure for a counting sampling unit is also proposed, which has better sampling accuracy than currently known counting sampling units. This is beneficial for improving the accuracy of pulse signal counting results, enabling it to more accurately reflect bioelectric voltage values. (Refer to...) Figure 3 The diagram shown is a schematic of the counting and sampling unit structure. Figure 3 Taking channel i (i.e., a channel unit circuit) as an example, the connection relationship between it and the counting sampling unit is schematically shown.

[0094] A first NMOS transistor MN1 and a second NMOS transistor MN2 are positioned between the signal counting unit and the counting sampling unit. These two NMOS transistors can be considered as two switches, and can naturally be replaced by any component or circuit with switching functionality. The second NMOS transistor MN2 is controlled by the sampling window signal ( Figure 3 In the example, CS<i+1> is used to control the order of row selection, which is equivalent to the order of row selection. The smallest size MOS transistor can be used; the first NMOS transistor MN1 is controlled by the counting result (i.e., the reading) of the signal counting unit.

[0095] In the peripheral circuit (i.e., the base), the counting sampling unit includes: the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6.

[0096] The reading of the gate receive signal counting unit of the first NMOS transistor MN1 ( Figure 3 In the example shown (represented by QS<1>), the source is grounded, and the drain is connected to the source of the second NMOS transistor MN2. The gate of the second NMOS transistor MN2 receives the window sampling signal, and its drain is connected to the drain of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4, respectively.

[0097] The gate of the fourth NMOS transistor MN4 receives the first bias voltage VBP1, and its drain is connected to the drain of the first PMOS transistor MP1, the gate of the third PMOS transistor MP3, and the gate of the fifth NMOS transistor MN5, respectively; the source of the third NMOS transistor MN3 is grounded.

[0098] The gate of the first PMOS transistor MP1 receives the second bias voltage VBP2, and the source receives the power supply voltage; the source of the third PMOS transistor MP3 also receives the power supply voltage, and the drain is connected to the source of the second PMOS transistor MP2.

[0099] The gate of the second PMOS transistor MP2 receives the base readout signal CSH, and its drain is connected to the drain of the sixth NMOS transistor MN6 and the trigger terminal D of the D flip-flop DFF. The gate of the sixth NMOS transistor MN6 receives the inverted signal CSHn of the base readout signal, and its source is connected to the drain of the fifth NMOS transistor MN5, whose source is grounded. Simultaneously, the D flip-flop DFF uses the base readout signal CSH as its clock signal, RN as its reset signal, and Q as its output, which is also the output of the counting and sampling unit.

[0100] In the circuit structure of the counting sampling unit, the first PMOS transistor MP1, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 constitute a judgment structure Jl (i.e., a judgment stage). By setting the first bias voltage VBP1 and the second bias voltage VBP2, the pull-up capability of the judgment structure Jl is greater than the pull-down capability.

[0101] When the paths of the first NMOS transistor MN1 and the second NMOS transistor MN2 are disconnected, Q is significantly stronger than Q because the pull-up capability is much greater than the pull-down capability. temp The junction (i.e., the connection point between the drain of PMOS transistor MP1 and the source of the fourth NMOS transistor MN4) is pulled up and is at a high level.

[0102] When the first NMOS transistor MN1 and the second NMOS transistor MN2 are both conducting, the pull-down capability of the first NMOS transistor MN1 and the second NMOS transistor MN2 is significantly greater than the pull-up capability of the first PMOS transistor MP1. Therefore, Q temp The node is pulled down to a low level. Then Q... temp The signal at the node is shaped by a tri-state gate consisting of the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the second PMOS transistor MP2, and the third PMOS transistor MP3, and then output after being synchronized by the D flip-flop DFF. The output after synchronization by the D flip-flop DFF improves the convenience of subsequent calculations.

[0103] The base readout signal CSH, as the readout-based sampling signal, requires the period T before the end of the high-level duration of the window signal. MCK The time (i.e., the period of the global high-frequency clock) is used to prevent sampling errors on the transition edge.

[0104] Compared to traditional counting and sampling units, the most significant advantage of this circuit structure is that it transfers the area and power consumption overhead to the base. Traditional counting and sampling units contain all their circuitry within the channel unit circuit, resulting in significant area and power consumption. In contrast, the circuit structure of the counting and sampling unit proposed in this invention uses only two transistors as switches within the channel unit circuit, while all other components are located at the base. Simultaneously, the bus...<N:1> The voltage fluctuation is small, and the current flowing through the two switching transistors MN1 and MN2 is also relatively small. Most of the overall power consumption is concentrated in the decision stage. Since most of the cost has been transferred to the external circuitry, the area and power consumption of the channel unit circuit have been reduced to some extent.

[0105] Based on the above-described calibrable invasive semiconductor brain-computer interface channel circuit, this invention also proposes an invasive semiconductor brain-computer device, wherein the infrared detection device includes any of the bioelectrical signal detection channel circuits described above.

[0106] Through the above examples, the bioelectric signal detection channel circuit provided by the present invention includes a voltage-to-current conversion unit that converts the received bioelectric signal into a corresponding current signal and transmits it to a pulse signal conversion unit; the pulse signal conversion unit converts the current signal into a pulse signal that is linearly related to the current signal; and a signal counting unit counts the pulse signals.

[0107] Within each quantization cycle, the counting sampling unit uses the first enable signal from the margin control unit to sample the counting result of the signal counting unit, and obtains the first count value based on the sampling results of two adjacent quantization cycles; within each quantization cycle, the margin control unit uses the sampling window signal and the pulse signal to generate the first enable signal and the second enable signal, and transmits them to the counting sampling unit and the margin counting unit, respectively.

[0108] Within each quantization cycle, the margin counting unit counts the margin of the pulse signal counting time based on the second enable signal, and obtains the second count value based on the sampling results of two adjacent quantization cycles; the signal counting unit and the margin counting unit respectively transmit the first count value and the second count value to the external computing unit so that the external computing unit can calculate the bioelectric voltage value.

[0109] This invention samples the residual time of the pulse signal counting, improving conversion accuracy compared to a single counting result, thereby enhancing detection precision. Furthermore, it proposes a novel circuit structure for the counting sampling unit, which offers better sampling accuracy than currently known units, thus improving the precision of pulse signal counting results and allowing for a more accurate reflection of bioelectric voltage values, further enhancing detection precision. A significant portion of the residual counting area is transferred to the base, maintaining detection precision without increasing the area of ​​the detection channel unit, reducing size and power consumption, and effectively suppressing the impact of motor heating on brain temperature. This design is particularly suitable for invasive brain-computer interfaces while meeting bioelectric signal detection requirements. The overall circuit structure boasts high integrability and scalability, further improving probe resolution.

[0110] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0111] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.< / n>

Claims

1. A bioelectric signal detection channel circuit, characterized in that, The bioelectric signal detection channel circuit includes: multiple channel unit circuits and a base, each channel unit including: a voltage-to-current conversion unit, a pulse signal conversion unit, a signal counting unit, and a margin control unit; The base includes: a counting sampling unit and a margin counting unit; The voltage-to-current conversion unit converts the received bioelectric signal into a corresponding current signal and transmits it to the pulse signal conversion unit; The pulse signal conversion unit converts the current signal into a pulse signal that is linearly related to the current signal. The signal counting unit counts the pulse signals; During each quantization cycle, the counting sampling unit uses a first enable signal from the margin control unit to sample the counting result of the signal counting unit, and obtains a first count value based on the sampling results of two adjacent quantization cycles. During each quantization cycle, the margin control unit generates the first enable signal and the second enable signal using the sampling window signal and the pulse signal, and transmits them to the counting sampling unit and the margin counting unit, respectively. Within each quantization cycle, the margin counting unit counts the margin of the counting time of the pulse signal based on the second enable signal, and obtains a second count value based on the sampling results of two adjacent quantization cycles. The signal counting unit and the margin counting unit respectively transmit the first count value and the second count value to the external processing unit so that the external processing unit can calculate the bioelectric voltage value. Among them, multiple channel units correspond to one base; The margin refers to the residual amount of the quantization period.

2. The bioelectric signal detection channel circuit according to claim 1, characterized in that, The voltage-to-current conversion unit includes: a high-pass filter and a transconductance module; The high-pass filter receives the bioelectric signal and the reference signal, filters the bioelectric signal to obtain a precise voltage signal, and transmits it to the transconductance module. The transconductance module converts the precise voltage into a corresponding current signal and transmits it to the pulse signal conversion unit.

3. The bioelectric signal detection channel circuit according to claim 1, characterized in that, The counting sampling unit uses a first enable signal from the margin control unit to sample the counting result of the signal counting unit, and obtains the first count value based on the sampling results of two adjacent quantization cycles in the following ways: Within the sampling window of the nth quantization cycle, the counting sampling unit receives the first enable signal and samples the first reading of the signal counting unit when the first pulse of the pulse signal arrives within the sampling window; Within the sampling window of the (n+1)th quantization cycle, the counting sampling unit uses the sampling window signal to sample the second reading of the signal counting unit when the first pulse of the pulse signal arrives within the sampling window; The difference between the second reading and the first reading is calculated to obtain the first count value.

4. The bioelectric signal detection channel circuit according to claim 1, characterized in that, The margin control unit generates the first enable signal and the second enable signal using the sampling window signal, and transmits them to the counting sampling unit and the margin counting unit respectively, in the following manner: The margin control unit receives the sampling window signal; When the rising edge of the sampling window signal arrives, the margin control unit generates a first second enable signal and transmits the first second enable signal to the margin counting unit. When the first pulse of the pulse signal arrives within the sampling window, the margin control unit generates a first enable signal and a second enable signal, and transmits the first enable signal to the counting sampling unit and the second enable signal to the margin counting unit.

5. The bioelectric signal detection channel circuit according to claim 4, characterized in that, The margin counting unit counts the margin of the counting time of the pulse signal based on the second enable signal, and obtains the second count value based on the sampling results of two adjacent quantization cycles in the following ways: The margin counting unit uses the global high-frequency clock as its input. When it receives the first second enable signal in the nth quantization cycle, it starts counting and ends counting when it receives the second second enable signal, thus obtaining the third reading. The margin counting unit uses the global high-frequency clock as its input. When it receives the first second enable signal in the (n+1)th quantization cycle, it starts counting and ends counting when it receives the second second enable signal, thus obtaining the fourth reading. The difference between the fourth reading and the third reading is calculated to obtain the second count value.

6. The bioelectric signal detection channel circuit according to claim 4, characterized in that, If the margin control unit generates the first enable signal when the rising edge of the first pulse arrives, the first enable signal is transmitted to the counting and sampling unit after a preset delay. If the margin control unit generates the first enable signal when the rising edge of the first pulse arrives, the first enable signal is directly transmitted to the counting and sampling unit after it is generated.

7. The bioelectric signal detection channel circuit according to claim 5, characterized in that, The formula for calculating the bioelectric voltage value is: In the above formula, V s < i > indicates the voltage value of the bioelectric signal. f osc This indicates the frequency of the pulse signal. K n+1 This indicates that within the sampling window of the (n+1)th quantization cycle, the counting sampling unit uses the sampling window signal to sample and obtain the second reading of the signal counting unit when the first pulse arrives. K n This indicates that within the sampling window of the nth quantization cycle, the counting sampling unit receives the first enable signal and samples the first reading of the signal counting unit when the first pulse arrives. Q n+1 This represents the fourth indicator. Q n This indicates the third indicator. T 0 indicates the duration of the quantization period. T MCK This represents the period of the global high-frequency clock.

8. The bioelectric signal detection channel circuit according to claim 1, characterized in that, The pulse signal conversion unit includes: a folded integrator or a flow-controlled oscillator; The product of the maximum oscillation frequency of the pulse signal and the duration of the quantization period is less than the range of the signal counting unit; The duration of the high level of the sampling window signal includes one and a half cycles of the pulse signal.

9. The bioelectric signal detection channel circuit according to claim 1, characterized in that, A first NMOS transistor and a second NMOS transistor are disposed between the signal counting unit and the counting sampling unit; the counting sampling unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The gate of the first NMOS transistor receives the reading of the signal counting unit, the source is grounded, and the drain is connected to the source of the second NMOS transistor; The gate of the second NMOS transistor receives the sampling signal from the window, and its drain is connected to the drain of the third NMOS transistor and the source of the fourth NMOS transistor, respectively. The gate of the fourth NMOS transistor receives a first bias voltage, and its drain is connected to the drain of the first PMOS transistor, the gate of the third PMOS transistor, and the gate of the fifth NMOS transistor, respectively. The source of the third NMOS transistor is grounded; The gate of the first PMOS transistor receives a second bias voltage, and the source receives a power supply voltage. The source of the third PMOS transistor receives the power supply voltage, and its drain is connected to the source of the second PMOS transistor. The gate of the second PMOS transistor receives the base readout signal, and its drain is connected to the drain of the sixth NMOS transistor and the trigger terminal of the D flip-flop; the output terminal of the D flip-flop is the output terminal of the counting sampling unit. The gate of the sixth NMOS transistor receives the inverted signal of the base readout signal, and its source is connected to the drain of the fifth NMOS transistor, while the source of the fifth NMOS transistor is grounded. The first PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor constitute a judgment structure. By setting the first bias voltage and the second bias voltage, the pull-up capability of the judgment structure is greater than the pull-down capability.

10. An invasive semiconductor brain-computer interface device, characterized in that, The invasive semiconductor brain-computer interface includes the bioelectric signal detection channel circuit as described in any one of claims 1-9.

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