A desaturation detection circuit and its application

Abstract

This invention discloses a desaturation detection circuit and its application, belonging to the field of detection circuit technology. The invention includes a resistor network positioned between the first terminal of a blanking capacitor and the switch under test. Under the action of the resistor network, the voltage v across the blanking capacitor... DESAT The voltage v of the switch under test DS An adjustable linear relationship exists between them, ensuring that the blanking capacitor has a higher potential before the FUL fault occurs. This reduces the transient time of the blanking capacitor during the FUL fault, improving the detection speed and shortening the detection time required for FUL faults. Furthermore, this invention achieves a higher detection voltage threshold V. REF Under fixed conditions, the threshold voltage of the switching transistor under overcurrent conditions can be adjusted by changing the resistance value of each resistor branch in the resistor network to meet the switching transistor characteristic curve and actual application requirements, and to achieve rapid detection under overcurrent conditions as needed.

Description

Technical Field

[0001] This invention belongs to the field of detection circuit technology, and more specifically, relates to a desaturation detection circuit and its application. Background Technology

[0002] The desaturation detection method is currently the most common method for detecting short-circuit faults in power semiconductors (switches) such as IGBTs, MOSFETs, and GaN HEMTs. Taking SiC MOSFETs as an example, it relies on the drain-source voltage v of the SiC MOSFET. DS With drain-source current i DS The corresponding relationship is used to realize current detection.

[0003] Companies such as Infineon and Texas Instruments have launched driver chips with current source desaturation detection function. However, most of these driver chips have a fixed detection voltage threshold and do not have the function of adjusting the protection threshold. They cannot be used in applications where the protection threshold is sensitive, because too small a protection threshold will trigger a fault and affect normal operation, while too large a protection threshold will increase the detection time.

[0004] There are two main types of short circuits in switching transistors: Hard Switching Fault (HSF) and Fault Under Load (FUL). HSF occurs when the switching transistor is already in a short circuit loop before it is turned on, and the short circuit is caused by the switching transistor being turned on. FUL occurs when the switching transistor is already fully turned on, and a short circuit occurs in the load, causing a fault.

[0005] To distinguish the transient process of normal switching of the transistor from HSF, existing detection circuits set a certain blanking time during desaturation detection. However, this also introduces a delay when detecting FUL, as the blanking time of FUL is equal to that of HSF. Since FUL is a fault caused by a short circuit in the load, the transistor is already turned on when the fault occurs, and there is no transient process. Therefore, theoretically, there is no need to distinguish the transient process of normal conduction from HSF. Based on this, it can be seen that when an FUL fault occurs, the existing detection circuit limits the detection speed of FUL, requiring a long detection time and failing to realize the potential for rapid detection of FUL. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a desaturation detection circuit and its application to solve the technical problem that the existing detection circuit limits the detection speed of FUL and the detection time of FUL is too long.

[0007] To achieve the above objectives, in a first aspect, the present invention provides a desaturation detection circuit, comprising: a level comparator, a blanking capacitor, a Zener diode, a charging switch, and a resistor network;

[0008] The positive terminal of the level comparator and the first terminal of the blanking capacitor are used to connect to the charging current source; the negative terminal of the level comparator is connected to the detection voltage threshold V. REF The second terminal of the blanking capacitor is grounded; the Zener diode and the charging switch are connected in parallel across the blanking capacitor.

[0009] The resistor network includes a first resistor branch, a second resistor branch, and a third resistor branch. One end of each of the three resistor branches is connected together and used to connect to the first terminal of the blanking capacitor through a first anti-reverse-current diode. The other end of the first resistor branch is used to connect to the positive terminal of the switch under test (SUTP) through a second anti-reverse-current diode. The negative terminal of the SUTP is grounded. The driving terminal of the SUTP is connected to the driving output terminal of the driving chip. The other end of the second resistor branch is used to connect to the driving output terminal of the driving chip. The other end of the third resistor branch is grounded.

[0010] The level comparator is used to compare the voltage v of the blanking capacitor. DESAT With detection voltage threshold V REF The size of v DESAT Greater than V REF When the signal is applied, it indicates that the switch under test has a fault.

[0011] More preferably, under steady state, the voltage v of the blanking capacitor is... DESAT The voltage v of the switch under test DS The following linear relationship is satisfied:

[0012] v DESAT =kv DS +V B

[0013] Among them, slope intercept G1 is the admittance of the first resistor branch; G2 is the admittance of the second resistor branch; G3 is the admittance of the third resistor branch; V D1 V is the forward voltage drop of the first anti-reverse-current diode; D2 The forward voltage drop of the second anti-reverse-current diode; V GS I is the driving voltage output by the driver chip. CHG The current output by the charging current source.

[0014] More preferably, the resistance values ​​of the first resistor branch, the second resistor branch, and the third resistor branch in the desaturation detection circuit are determined in the following way:

[0015] The threshold voltage V of the switch under test required for the specific application scenario. DS-th The maximum delay time T required under FUL fault conditions delay-max Substitute these values ​​into the threshold voltage expression of the switch under test. The expression for the maximum delay time under FUL fault. Solving for the slope k and intercept V yields the slope k and intercept V. B Thus, the resistance values ​​of the first resistance branch, the second resistance branch, and the third resistance branch are obtained;

[0016] Among them, C BLK The value of the blanking capacitor.

[0017] More preferably, the capacitance C of the blanking capacitor is... BLK The blanking time required under HSF fault conditions of the switch under test is determined as follows:

[0018]

[0019] Among them, T BLK This is the blanking time required for the switch under test to undergo an HSF fault.

[0020] More preferably, the driving electrode of the switch under test is connected to the driving output terminal of the driving chip through a resistor.

[0021] More preferably, the above-mentioned desaturation detection circuit further includes the charging current source connected to the positive terminal of the level comparator and the first terminal of the blanking capacitor.

[0022] In a second aspect, the present invention provides a bridge arm system, comprising:

[0023] The bridge arm includes: a first switch and a second switch connected in series;

[0024] A first desaturation detection circuit for detecting the first switching transistor;

[0025] A second desaturation detection circuit for detecting the second switching transistor;

[0026] The first desaturation detection circuit and the second desaturation detection circuit are both desaturation detection circuits provided in the first aspect of the present invention.

[0027] More preferably, the above-mentioned bridge arm system further includes a charging current source connected to the positive terminal of the level comparator and the first terminal of the blanking capacitor.

[0028] An interlock circuit connected to the first and second switching transistors respectively;

[0029] The controller is used to determine that the switch corresponding to the desaturation detection circuit that first detected the fault has a FUL fault when the first switch and the second switch are turned on in succession, and to control the interlock circuit to block the first switch and the second switch, so as to realize the exit of the entire bridge arm.

[0030] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0031] 1. This invention provides a desaturation detection circuit, including a resistor network disposed between the first terminal of a blanking capacitor and the switch transistor under test. Under the action of the resistor network, the voltage v of the blanking capacitor is... DESAT The voltage v of the switch under test DS There is an adjustable linear relationship between them, which results in a voltage bias in the blanking capacitor under steady state. That is, the blanking capacitor has a higher potential before the FUL fault occurs, thereby reducing the detection delay time caused by the transient process of the blanking capacitor when the FUL fault occurs, improving the detection speed under FUL fault, and shortening the detection time required under FUL fault.

[0032] 2. Furthermore, the desaturation detection circuit provided by the present invention, at the detection voltage threshold V REF Under fixed conditions, the threshold voltage of the switching transistor can be adjusted by changing the resistance values ​​of each resistor branch in the resistor network to meet the switching transistor's characteristic curve and practical application requirements, thereby configuring a shorter FUL detection delay time T as needed. delay and the short-circuit protection threshold V under overcurrent conditions DS-th It can achieve rapid detection under overcurrent conditions as needed.

[0033] 3. Furthermore, the desaturation detection circuit provided by this invention can use a resistor network to detect the short-circuit protection threshold V under overcurrent conditions. DS-th Adjustments are made to suit the actual needs of different application scenarios, selecting a value slightly greater than the maximum voltage of the switching transistor under normal conduction conditions. DS The short-circuit protection threshold can achieve rapid protection while meeting short-circuit protection requirements.

[0034] 4. The present invention provides a bridge arm system that can quickly detect the switching transistors in the FUL state when the bridge arm module is short-circuited, thereby accelerating the short-circuit protection speed of the bridge arm module.

[0035] 5. The bridge arm system provided by the present invention further includes an interlock circuit connected to the first switch and the second switch respectively; when the first switch and the second switch are turned on in succession, it is determined that the switch corresponding to the desaturation detection circuit that first detected the fault has a FUL fault, and the first switch and the second switch are blocked by the interlock circuit to realize the withdrawal of the entire bridge arm and avoid the occurrence of secondary faults. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the desaturation detection circuit provided in Embodiment 1 of the present invention;

[0037] Figure 2 The detection voltage v provided in Embodiment 1 of the present invention DESAT With the drain-source voltage v of the switching transistor DS The relationship curve is shown in the figure; where (a) is V. DS-th V at a certain time B (a) is the selectable range; (b) is V B V at a certain time DS-th The optional range;

[0038] Figure 3 The following are timing waveform diagrams of the main parameters under short-circuit conditions provided in Embodiment 1 of the present invention; wherein, (a) is the timing waveform diagram of the main parameters under HSF; and (b) is the timing waveform diagram of the main parameters under FUL.

[0039] Figure 4 The timing waveform diagram of the main parameters under overcurrent conditions provided in Embodiment 1 of the present invention;

[0040] Figure 5 This is a schematic diagram of the application of the present invention in the bridge arm module according to Embodiment 1. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0042] Example 1

[0043] A desaturation detection circuit includes: a level comparator, a blanking capacitor, a Zener diode, a charging switch, and a resistor network;

[0044] The positive terminal of the level comparator and the first terminal of the blanking capacitor are used to connect to the charging current source; the negative terminal of the level comparator is connected to the detection voltage threshold V. REF The second terminal of the blanking capacitor is grounded; the Zener diode and the charging switch are connected in parallel across the blanking capacitor.

[0045] The resistor network includes a first resistor branch, a second resistor branch, and a third resistor branch. One end of each of the three resistor branches is connected together and used to connect to the first terminal of the blanking capacitor through a first anti-reverse-current diode. The other end of the first resistor branch is used to connect to the positive terminal of the switch under test (SUTP) through a second anti-reverse-current diode. The negative terminal of the SUTP is grounded. The driving terminal of the SUTP is connected to the driving output terminal of the driving chip. The other end of the second resistor branch is used to connect to the driving output terminal of the driving chip. The other end of the third resistor branch is grounded.

[0046] The level comparator is used to compare the voltage v of the blanking capacitor. DESAT With detection voltage threshold V REF The size of v DESAT Greater than V REF When the circuit is short-circuited, the output signal indicates that the switch under test has a short-circuit fault.

[0047] When a fault is detected, the driver chip controller turns off the fault switch transistor, thereby cutting off the fault.

[0048] In the desaturation detection circuit provided by this invention, the voltage v of the blanking capacitor... DESAT The voltage v of the switch under test DS The following linear relationship is satisfied:

[0049] v DESAT =kv DS +V B

[0050] Among them, slope intercept G1 is the admittance of the first resistor branch; G2 is the admittance of the second resistor branch; G3 is the admittance of the third resistor branch; V D1 V is the forward voltage drop of the first anti-reverse-current diode; D2 The forward voltage drop of the second anti-reverse-current diode; V GS I is the driving voltage output by the driver chip. CHG The current output by the charging current source.

[0051] Under overcurrent conditions, the rate of current change is small, and the circuit always satisfies the relationship v. DESAT =kv DS +V B When v DS Rise to At that time, v DESAT Reaching V REF Trigger a fault signal by properly configuring k and V through a resistor network. B Reduce the short-circuit protection threshold while meeting protection requirements. This enables rapid protection. In HSF and FUL states, vDS Rapid rise, anti-reverse current diode cut off, I CHG The flow goes to the blanking capacitor. Under HSF, v DESAT From 0 for a blanking time T BLK Rise to V REF Trigger fault signal; under FUL, v DESAT From the steady-state value kv before the fault DS +V B After a delay of time T delay Rise to V REF A fault signal is triggered. This is achieved by properly configuring k and V through a resistor network. B Increase the steady-state value kv before the fault DS +V B In order to shorten its v after the failure DESAT Rise to V REF This reduces the delay time, thereby speeding up the FUL testing process.

[0052] Furthermore, the resistance values ​​of the first, second, and third resistor branches in the desaturation detection circuit are determined in the following way:

[0053] v DESAT =V REF and v DS =v DS-th Substitute into v DESAT =kv DS +V B In this process, the threshold voltage expression for the switch under test is obtained.

[0054] The threshold voltage V of the switch under test required for the specific application scenario. DS-th The maximum delay time T required under FUL fault conditions delay-max Substitute these values ​​into the threshold voltage expression of the switch under test. The expression for the maximum delay time under FUL fault. Solving for the slope k and intercept V yields the slope k and intercept V. B Thus, the resistance values ​​of the first resistance branch, the second resistance branch, and the third resistance branch are obtained;

[0055] Among them, by V DS-th With V B From the expression, we can obtain the constraint relationship between them as: V B V DS-th ≥V GS (V REF -V B -V DS-th C BLK This refers to the capacitance of the blanking capacitor. Specifically, the capacitance C of the blanking capacitor... BLKThe blanking time required under HSF fault conditions of the switch under test is determined as follows:

[0056]

[0057] Among them, T BLK This is the blanking time required for the switch under test to undergo an HSF fault.

[0058] It should be noted that the resistor branch in this invention can be composed of one or more resistors. When multiple resistors are included, they can be multiple resistors connected in series, multiple resistors connected in parallel, or a resistor topology that includes both series and parallel structures. Figure 1 This is just an example structure and is not limited to... Figure 1 The structure shown.

[0059] Preferably, in one optional implementation, the driving electrode of the switch under test is connected to a resistor R. G It is connected to the drive output terminal of the driver chip to limit the charging and discharging current.

[0060] Preferably, in an optional embodiment, the desaturation detection circuit further includes the charging current source connected to the positive terminal of the level comparator and the first terminal of the blanking capacitor.

[0061] It should be noted that the switching transistors applicable to this invention can be MOSFETs, IGBTs, BJTs, GTOs, etc.

[0062] Specifically, when the transistor under test is a MOSFET, its anode is the drain, its cathode is the source, and its drive electrode is the gate. When the transistor under test is an IGBT, its anode is the collector, its cathode is the emitter, and its drive electrode is the gate. When the transistor under test is a GaN HEMT, its anode is the drain, its cathode is the source, and its drive electrode is the gate.

[0063] The following explanation uses a SiC MOSFET as an example of the switch under test:

[0064] like Figure 1 The diagram shown is a schematic of the desaturation detection circuit provided in this embodiment, wherein the charging switch Q... DESAT When the switching transistor is turned off, it conducts to short-circuit the charging current source I. CHGTo prevent false triggering of fault signals, the diode is turned off when the switching transistor is on, enabling the desaturation detection function. The first anti-reverse-current diode D1 and the second anti-reverse-current diode D2 are used to conduct forward current and sense drain-source voltage when the switching transistor is on, and to block high drain-source voltage when the switching transistor is off. Zener diode ZD is used to regulate the voltage of the entire circuit.

[0065] Specifically, when the MOSFET is normally turned on, the detection voltage (voltage of the blanking capacitor) v DESAT With MOSFET drain-source voltage v DS The relationship is shown in the following formula:

[0066]

[0067] Where G1 is the admittance of the first resistor branch; G2 is the admittance of the second resistor branch; G3 is the admittance of the third resistor branch; V D1 V is the forward voltage drop of the first anti-reverse-current diode; D2 The forward voltage drop of the second anti-reverse-current diode; V GS I is the driving voltage output by the driver chip. CHG The current output by the charging current source.

[0068] In order to set the threshold voltage of the switching transistor according to its characteristic curve and actual application requirements, this invention sets up a corresponding resistor network, the specific process of which is as follows:

[0069] Figure 2 To detect voltage v DESAT With the drain-source voltage v of the switching transistor DS The relationship curve is expressed as follows:

[0070] v DESAT =kv DS +V B

[0071] By adjusting the resistance value of the resistor network, the intercept voltage V can be changed. B The linear slope value k is shown in the following formula:

[0072]

[0073]

[0074] Select an appropriate resistor value to obtain the target switch threshold voltage V. DS-th :

[0075]

[0076] By V DS-th With V BThe expression gives us the constraint relationship between them: V B V DS-th ≥V GS (V REF -V B -V DS-th ). Specifically, Figure 2 Figure (a) in the middle is V DS-th V at a certain time B The optional range, Figure 2 Figure (b) in the middle is V B V at a certain time DS-th The optional range.

[0077] Figure 3 Figure 1 shows the timing waveforms of the main parameters under short-circuit conditions according to an embodiment of the present invention; wherein, Figure (a) is the timing waveform of the main parameters under HSF, T BLK The blanking time under HSF is given by the following formula, and the capacitance C of the blanking capacitor can be changed. BLK Adjust the value:

[0078]

[0079] t d This refers to the delay in time for the driver chip to turn off the switching transistor after detecting a fault;

[0080] Figure (b) shows the timing waveforms of the main parameters under FUL, T delay Let v be the blanking time under FUL. DESAT From the steady state kV before the fault DS-nor +V B by The charging slope increases to V REF Time:

[0081]

[0082] Among them, V DS-nor This represents the drain-source voltage of the MOSFET before the short-circuit fault occurred.

[0083] When V DS-nor =0 when T delay-max Take the maximum value:

[0084]

[0085] Adjust V by changing G1, G2, and G3 of the resistor network. B It can make T delay-max A smaller value is used to shorten the FUL detection time.

[0086] t dSimilarly, this refers to the delay in time from when the driver chip detects a fault to when it turns off the switching transistor.

[0087] Figure 4 This is a timing waveform diagram of the main parameters under overcurrent conditions in an embodiment of the present invention. Figure 4 As shown, t1 is v DESAT From 0 to kv DS +V B The time required for the transient process; t2 is the time required for v DESAT Follow KV DS +V B Rise to V REF Time; t d This refers to the delay in time from when the driver chip detects a fault to when it turns off the switching transistor. V REF The corresponding threshold voltage V of the switching transistor DS-th for:

[0088]

[0089] Adjust V by changing G1, G2, and G3 of the resistor network. B k can change V DS-th The value of is used to change the protection threshold of the switching transistor.

[0090] Example 2

[0091] A bridge arm system, comprising:

[0092] The bridge arm includes: a first switch and a second switch connected in series;

[0093] A first desaturation detection circuit for detecting the first switching transistor;

[0094] A second desaturation detection circuit for detecting the second switching transistor;

[0095] Preferably, in one optional embodiment, the above-mentioned bridge arm system further includes:

[0096] An interlock circuit connected to the first and second switching transistors respectively;

[0097] The first desaturation detection circuit and the second desaturation detection circuit are both desaturation detection circuits provided in Embodiment 1 of the present invention.

[0098] The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.

[0099] The controller is used to determine that the switch corresponding to the desaturation detection circuit that first detected the fault has a FUL fault when the first switch and the second switch are turned on in succession and a short circuit fault occurs, and to control the interlock circuit to block the first switch and the second switch, so as to realize the exit of the entire bridge arm.

[0100] Figure 5 This is a schematic diagram illustrating the principle of Embodiment 1 of the present invention when applied to a bridge arm module. Figure 5 As shown, the desaturation circuit provided in Embodiment 1 of this invention can be used in a bridge arm module. When a shoot-through short-circuit fault occurs in the bridge arm module, the switch that triggered the short-circuit fault during the conduction process is in the HSF state, while another switch that was already turned on before the short circuit is in the FUL state. The proposed desaturation circuit can significantly shorten the fault detection time under FUL, and will turn off the switch in the FUL state more quickly than the switch in the HSF state, and output a fault signal FLT1 (fault signal low level active; taking the upper switch as an example, the upper switch is in the FUL state). After the logic gate circuit de-enables the drive signals of the upper and lower switches, the entire bridge arm module is turned off. This invention enables the entire bridge arm module to be quickly protected in the event of a shoot-through short-circuit fault by rapidly detecting and protecting the switch in the FUL state of the bridge arm module.

[0101] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A desaturation detection circuit, characterized in that, include: Level comparator, blanking capacitor, Zener diode, charging switch and resistor network; The positive terminal of the level comparator and the first terminal of the blanking capacitor are used to connect to the charging current source; the negative terminal of the level comparator is connected to the detection voltage threshold V. REF The second terminal of the blanking capacitor is grounded; the Zener diode and the charging switch are respectively connected in parallel across the blanking capacitor. The resistor network includes a first resistor branch, a second resistor branch, and a third resistor branch; one end of each of the first, second, and third resistor branches is connected together and used to connect to the first terminal of the blanking capacitor through a first anti-reverse-current diode; the other end of the first resistor branch is used to connect to the positive terminal of the switch under test (SUTP) through a second anti-reverse-current diode; the negative terminal of the SUTP is grounded; the driving terminal of the SUTP is connected to the driving output terminal of the driving chip; the other end of the second resistor branch is used to connect to the driving output terminal of the driving chip; and the other end of the third resistor branch is grounded. The level comparator is used to compare the voltage v of the blanking capacitor. DESAT With the detection voltage threshold V REF The size of v DESAT Greater than V REF When the test transistor is faulty, a signal is output indicating that the transistor under test is faulty.

2. The desaturation detection circuit according to claim 1, characterized in that, Under steady state, the voltage v of the blanking capacitor DESAT The voltage v of the switch transistor under test DS The following linear relationship is satisfied: v DESAT =kv DS +V B Among them, slope intercept G1 is the admittance of the first resistor branch; G2 is the admittance of the second resistor branch; G3 is the admittance of the third resistor branch; V D1 V is the forward voltage drop of the first anti-reverse-current diode; D2 V is the forward voltage drop of the second anti-reverse-current diode; GS The driving voltage output by the driving chip; I CHG The current output by the charging current source.

3. The desaturation detection circuit according to claim 2, characterized in that, The resistance values ​​of the first resistor branch, the second resistor branch, and the third resistor branch are determined in the following way: The threshold voltage V of the switch under test required for the specific application scenario. DS-th The maximum delay time T required under FUL fault conditions delay-max Substitute these values ​​into the threshold voltage expression of the switch under test. The expression for the maximum delay time under FUL fault. Solving for the slope k and intercept V yields the slope k and intercept V. B Thus, the resistance values ​​of the first resistance branch, the second resistance branch, and the third resistance branch are obtained; Among them, C BLK The value of the blanking capacitor.

4. The desaturation detection circuit according to claim 3, characterized in that, The capacitance C of the blanking capacitor BLK The blanking time required under HSF fault conditions of the switch under test is determined as follows: Among them, T BLK This is the blanking time required for the switch under test to undergo an HSF fault.

5. The desaturation detection circuit according to any one of claims 1-4, characterized in that, The driving electrode of the switch under test is connected to the driving output terminal of the driving chip through a resistor.

6. The desaturation detection circuit according to any one of claims 1-4, characterized in that, Also includes: The charging current source is connected to the positive terminal of the level comparator and the first terminal of the blanking capacitor.

7. A bridge arm system, characterized in that, include: The bridge arm includes: a first switch and a second switch connected in series; A first desaturation detection circuit for detecting the first switching transistor; A second desaturation detection circuit for detecting the second switching transistor; Wherein, both the first desaturation detection circuit and the second desaturation detection circuit are desaturation detection circuits as described in any one of claims 1-6.

8. The bridge arm system according to claim 7, characterized in that, Also includes: An interlock circuit connected to the first switch and the second switch respectively; The controller is used to determine that the switch corresponding to the desaturation detection circuit that first detected the fault has an FUL fault when the first switch and the second switch are turned on in succession, and to control the interlock circuit to block the first switch and the second switch, so as to realize the exit of the entire bridge arm.

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