A method and a circuit for monitoring the degradation of the gate of a SiC MOSFET device

Abstract

The application provides a trench gate SiC MOSFET device gate degradation monitoring method and a monitoring circuit. The method uses the body diode voltage drop at the intersection of the output characteristic curves of the SiC MOSFET device in the third quadrant zero gate voltage and different junction temperatures as a characteristic quantity. In the double pulse circuit, the gate voltage of the SiC MOSFET device to be tested of the lower tube is always kept at zero gate voltage. When the inductive current flows through the lower tube SiC MOSFET device, the body diode voltage drop value of the SiC MOSFET device to be tested at the intersection current is detected, and the body diode voltage drop value of the new device at the intersection current is compared to determine whether the SiC MOSFET device to be tested has occurred gate degradation. The application can ignore the influence of the junction temperature to realize accurate monitoring of the SiC MOSFET device gate degradation, and is a good candidate method for online monitoring, which can avoid economic losses caused by shutdown detection.

Description

Technical Field

[0001] This invention relates to a method for testing power equipment, and more particularly to a method and circuit for monitoring gate degradation of SiC MOSFET devices. Background Technology

[0002] Driven by the energy crisis and environmental problems, new energy technologies are constantly developing. Currently, the installed capacity of solar and wind power generation is experiencing rapid growth year by year, and electric vehicles and various consumer electronics are widely used in people's production and daily lives. Among these, the reliability of power electronic devices, as key components in new energy applications, has become a major concern.

[0003] Traditional silicon (Si) semiconductor power devices have reached their physical limits and can no longer meet the development needs of related industries. In contrast, third-generation wide-bandgap semiconductor materials have significant advantages over traditional Si materials. Therefore, third-generation wide-bandgap semiconductor power devices, represented by SiC MOSFETs, have received increasing attention and application due to their high frequency, high energy efficiency, high power density, and resistance to harsh environments, becoming the "core" of many emerging pillar industries.

[0004] In power electronic devices, SiC MOSFETs are one of the key components in power converters. Compared to Si-based devices of the same size, SiC MOSFETs have a smaller chip area, which means they can achieve higher current densities and thus withstand greater electrothermal stress. In particular, due to the properties of SiC material, the reliability of the gate oxide layer in SiC MOSFET devices has become increasingly prominent, leading to gradual aging during actual operation and severely impacting the reliability of power electronic systems. The health level of SiC MOSFET devices in power converters decreases with increasing service life.

[0005] Existing research indicates that monitoring the state of SiC MOSFET devices throughout their entire lifecycle, tracking changes in electrical and thermal characteristics that reflect device degradation or early failures, and providing timely reliability warnings is a more cost-effective solution for monitoring the reliability of SiC MOSFET devices in converters. However, existing methods for monitoring the state of SiC MOSFET devices have various problems: for example, the coupling of junction temperature fluctuations leads to inaccurate monitoring results; monitoring aging characteristics requires system shutdown; and the monitoring circuit design is complex or costly.

[0006] Therefore, how to provide a method for accurately monitoring the gate degradation of SiC MOSFET devices is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of this, and in view of the above-mentioned shortcomings of the prior art, the purpose of this invention is to provide a method for monitoring gate degradation of trench gate SiC MOSFET devices, which solves the problems of inaccurate monitoring and complex and costly monitoring circuits in the prior art; at the same time, it is also a good candidate method for online monitoring.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] This invention provides a method for monitoring gate degradation of SiC MOSFET devices. In a dual-pulse circuit, for a SiC MOSFET device under test, the gate aging state of the SiC MOSFET device under test is determined by comparing the body diode voltage drop of the SiC MOSFET device under test with that of a brand-new device under the junction current. Specifically, if the detected body diode voltage drop of the SiC MOSFET device under test under the junction current is greater than that of the brand-new SiC MOSFET device under the junction current, it indicates that the gate of the SiC MOSFET device under test has degraded; otherwise, the gate of the SiC MOSFET device under test has not degraded.

[0010] Furthermore, the third quadrant output characteristic curve of the brand-new SiC MOSFET device under test was tested using a semiconductor testing system at zero gate voltage to obtain the intersection current value. Based on the body diode voltage drop VSD-new of the SiC MOSFET device under test at this intersection current in the brand-new state, after the SiC MOSFET device under test under AC gate bias accelerated aging, the body diode voltage drop VSD-ip at this intersection current was tested again. If VSD-ip>VSD-new, it indicates that the gate degradation of the SiC MOSFET device under test has occurred.

[0011] Furthermore, the tested SiC MOSFET device and the SiC MOSFET device under test are the same type of trench-gate SiC MOSFET device. This is because the carrier lifetime of the planar-gate SiC MOSFET device is relatively larger than that of the trench-gate SiC MOSFET device, resulting in the absence of an intersection point independent of junction temperature in its zero-gate voltage output characteristic curve in the third quadrant. Specifically, the intersection point exists at the positive gate voltage; therefore, the zero-gate voltage monitoring proposed in this invention is only applicable to trench-gate SiC MOSFET devices. Gate degradation monitoring at the positive gate voltage intersection point of planar-gate SiC MOSFET devices will be further studied as a subsequent research topic.

[0012] The method of this invention is mainly applied to converters or devices including SiC MOSFET devices.

[0013] This invention also provides a gate degradation monitoring circuit for SiC MOSFET devices, comprising a dual-pulse test circuit consisting of a test SiC MOSFET device Q1 and a SiC MOSFET device under test (DUT); the test SiC MOSFET device Q1 and the DUT form a half-bridge structure, with a parallel capacitor C on the DC side for voltage regulation, an inductive load L on the AC side, and a resistor Rshunt for measuring the branch current; wherein the upper test SiC MOSFET device Q1 and the load inductor L form a loop with gradually increasing load current, and the lower test SiC MOSFET device DUT and the load inductor L form a freewheeling loop in the dual-pulse test circuit;

[0014] The test SiC MOSFET device Q1 and the SiC MOSFET device under test (DUT) are controlled by a controller and their respective drive circuits. In the dual-pulse test circuit, the gate-source voltage of the lower SiC MOSFET device DUT is always kept at zero gate voltage. The upper SiC MOSFET device Q1 is turned on under positive gate voltage, and the current is increased to the junction current value through the load inductor L. At this time, zero gate voltage is applied to the upper SiC MOSFET device Q1 to turn it off. Since the current on the load inductor L cannot change abruptly, freewheeling occurs through the lower SiC MOSFET device DUT. In the initial stage of freewheeling, the inductor current decreases very little and can be considered to remain basically unchanged. The body diode voltage drop of the SiC MOSFET device DUT when the junction current stabilizes at this time is the required value.

[0015] Furthermore, the number of SiC MOSFET driving circuits is equal to the number of SiC MOSFET devices; each SiC MOSFET device driving circuit has one signal input port and one signal output port, wherein the signal input port is the working signal port. The controller is connected to one input port of the SiC MOSFET driving circuit, and the output port of the SiC MOSFET driving circuit outputs a driving signal to the SiC MOSFET device; when the controller outputs the working signal CS, the SiC MOSFET driving circuit outputs a driving voltage of approximately +18V. V H The SiC MOSFET is controlled to operate in the normal on-state; when there is no operating signal CS, the SiC MOSFET drive circuit outputs zero voltage. V L The SiC MOSFET device is kept in a zero-voltage state; the monitoring time is the stage when the junction current does not decrease significantly when the load inductor current freewheels, i.e., the stage when the junction current value is stable.

[0016] Furthermore, to more accurately monitor the body diode voltage drop, a clamping circuit is added to the double-pulse test circuit. Due to the turn-on and turn-off of the upper-side SiC MOSFET under test, the drain-source voltage of the lower-side SiC MOSFET under test experiences a significant voltage difference within one cycle of the double-pulse test circuit. This affects the accurate measurement of the body diode voltage drop of the lower-side SiC MOSFET under test. Therefore, this invention adds a clamping circuit, as proposed in existing literature, to the double-pulse test circuit to reduce the drain-source voltage difference of the lower-side SiC MOSFET under test and improve the accuracy of the body diode voltage drop measurement. The clamping circuit includes a depletion-type SiC MOSFET M1, a Zener diode Z1, and a Schottky diode S1. The drain of M1 is connected to the drain of the DUT, and the gate of M1 is connected to the source of the DUT, and then connected in parallel to the branches Z1 and S1. VDS is the drain-source voltage obtained directly from the DUT, and VDS(m) is the drain-source voltage measured after passing through the clamping circuit. When the DUT is subjected to the DC bus voltage, the gate-source of M1 is turned off under negative voltage, and the drain-source voltage is approximately equal to the DC bus voltage. VDS is clamped to the negative threshold voltage of M1 by the clamping circuit. When the DUT is in the freewheeling phase, VDS is the reverse body diode voltage drop, M1 is turned on and operates normally, and the drain-source voltage is approximately 0V. VDS is clamped to its own value by the clamping circuit. Therefore, this clamping circuit can reduce the drain-source voltage difference of the DUT under different circuit states, improving the accuracy of the body diode voltage drop measurement.

[0017] Furthermore, the junction current value in the freewheeling state is determined based on the third quadrant output characteristic curves of multiple sample SiC MOSFET devices at zero gate voltage; specifically as follows:

[0018] The third quadrant output characteristic curves of multiple sample SiC MOSFET devices under different aging levels and junction temperatures were tested at zero gate voltage, and the source-drain current at the intersection point was used as the experimental monitoring current.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The method provided by this invention can be applied to various circuits as long as the SiC MOSFET device under test is at zero gate voltage and the load current is equal to the junction current value, allowing freewheeling through its own diode. It has strong adaptability. When applied to converters or equipment including trench-gate SiC MOSFET devices, it can accurately monitor the gate degradation state of trench-gate SiC MOSFET devices.

[0021] 2. The monitoring method of this invention can decouple the influence of junction temperature to accurately determine whether gate degradation has occurred in SiC MOSFET devices. For trench-gate SiC MOSFET devices under zero gate voltage in the third quadrant, the output characteristic curves at different junction temperatures intersect at a point. The source-drain current at this intersection is used as the experimental monitoring current, and the body diode voltage drop VSD-ip at this intersection current is used to monitor the gate degradation of the SiC MOSFET device. This is because when the gate of a SiC MOSFET device degrades, the threshold voltage Vth increases, leading to an increase in the MOS channel resistance Rch. This causes more source-drain current to flow through the body diode, increasing the body diode voltage drop VSD. This method can ignore the coupling effect of junction temperature on gate degradation monitoring, achieving accurate monitoring of SiC MOSFET devices. Furthermore, this dual-pulse test circuit can conveniently and accurately measure the body diode voltage drop, verifying the feasibility and effectiveness of the proposed method. Furthermore, since the carrier lifetime of planar gate SiC MOSFET devices is relatively larger than that of trench gate SiC MOSFET devices, the intersection point in their third quadrant output characteristic curve that is independent of junction temperature exists at a lower positive gate voltage rather than at zero gate voltage. Therefore, gate degradation monitoring of planar gate SiC MOSFET devices will continue to be a research topic.

[0022] 3. As long as the conditions are met—the SiC MOSFET device under test is at zero gate voltage and the load current equals the junction current value, allowing freewheeling through its own body diode—it can be applied to online monitoring. For example, this invention will be applied to a single-phase full-bridge inverter circuit in the future, where the body diode voltage drop under junction current is measured during the freewheeling phase to monitor the gate degradation state. Therefore, this invention is a good candidate method for online monitoring, laying a solid foundation for non-stop online monitoring of gate degradation of SiC MOSFET devices. It can effectively avoid economic losses caused by downtime testing, improve the accuracy of aging measurements, reduce the operation and maintenance costs of converters and other equipment containing SiC MOSFET devices, and improve equipment reliability.

[0023] 4. The method of this invention uses a controller and monitoring circuit to monitor the body diode voltage drop under the junction current of the SiC MOSFET under test during freewheeling, thereby achieving gate degradation monitoring. Simultaneously, a clamping circuit is added to the dual-pulse testing circuit to improve the measurement accuracy of the body diode voltage drop. Furthermore, this circuit has a simple structure and low cost. Attached Figure Description

[0024] Figure 1 This is a flowchart of the gate degradation monitoring method for SiC MOSFET devices of the present invention;

[0025] Figure 2A dual-pulse test circuit diagram for the additional clamping circuit of the SiC MOSFET device of this invention;

[0026] Figure 3 This is a schematic diagram of the drive control of the dual-pulse test circuit of the present invention;

[0027] Figure 4 This is a schematic diagram of the driving voltage of the SiC MOSFET device of the present invention;

[0028] Figure 5 This is a schematic diagram of the third quadrant output characteristic curves of a SiC MOSFET device at zero gate voltage under different aging levels. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0030] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In the description of this invention, it should also be noted that, unless otherwise expressly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] See Figure 1This invention provides a method for monitoring gate degradation of SiC MOSFET devices. In a dual-pulse circuit, for a SiC MOSFET device under test, the gate aging state of the SiC MOSFET device under test is determined by comparing the body diode voltage drop of the SiC MOSFET device under test with that of a brand-new device under the junction current. Specifically, if the detected body diode voltage drop of the SiC MOSFET device under test under the junction current is greater than that of a brand-new SiC MOSFET device under the junction current, it indicates that the gate of the SiC MOSFET device under test has degraded; otherwise, the gate of the SiC MOSFET device under test has not degraded.

[0032] Specifically, the controller applies a zero-volt drive voltage to the SiC MOSFET under test, bringing it to a zero-voltage state. The controller then measures the body diode voltage drop of the SiC MOSFET under test when the inductor current is freewheeling. This body diode voltage drop is compared with that of a brand-new device under the same cross-current condition to determine the gate degradation state of the SiC MOSFET under test. The controller can be a TI TMS320F28335.

[0033] Furthermore, the SiC MOSFET device gate degradation monitoring method includes the following steps:

[0034] The PST6747A semiconductor test system was used to test the third quadrant output characteristic curve of a brand-new SiC MOSFET device under test at zero gate voltage to obtain the intersection current value. Based on the dual-pulse test circuit proposed in this invention, the body diode voltage drop VSD-new of the SiC MOSFET device under test at the intersection current was tested in the brand-new state. After the SiC MOSFET device under test under AC gate bias accelerated aging, the body diode voltage drop VSD-ip at the intersection current was tested again. If VSD-ip > VSD-new, it indicates that the gate degradation of the SiC MOSFET device under test has occurred.

[0035] Furthermore, this method can be applied to converters or devices that include SiC MOSFET devices. Example

[0036] The following offline experiments verify the gate degradation monitoring of trench-gate SiC MOSFET devices.

[0037] See Figure 2A half-bridge structure is formed by two discrete trench-gate SiC MOSFET devices of the same model. A capacitor C is connected in parallel on the DC side for voltage regulation, and the AC side load is an inductive load L. The resistor Rshunt is used to measure the branch current. The upper SiC MOSFET device Q1 and the load inductor L form a loop with gradually increasing load current. The lower SiC MOSFET device DUT and the load inductor L form a freewheeling loop in the dual-pulse test circuit. The depletion-type SiC MOSFET device M1, the Zener diode Z1, and the Schottky diode S1 form a clamping circuit to improve the accuracy of the body diode voltage drop measurement.

[0038] See Figure 3 The dual-pulse test circuit consists of drive circuits W1 and W-DUT, with the controller providing the operating signal. W1 is the drive circuit for testing the SiC MOSFET device Q1, and W-DUT is the drive circuit for the SiC MOSFET device DUT under test. CS is the operating signal port of the SiC MOSFET drive circuit, and VO is the output port. When the controller outputs the operating signal CS, the SiC MOSFET drive circuit outputs a drive voltage of approximately +18V. V H The SiC MOSFET is controlled to operate in the normal on-state; when there is no operating signal CS, the SiC MOSFET drive circuit outputs zero voltage. V L The SiC MOSFET device is brought to a zero-voltage state. In the dual-pulse test circuit, the gate voltage of the lower SiC MOSFET device under test (DUT) remains at zero. The upper SiC MOSFET device Q1 is turned on by a positive gate drive voltage input through the drive circuit W1. During this stage, the current in the load inductor L gradually increases to the junction current value. At this point, a zero gate drive voltage is input to the test SiC MOSFET device Q1 through the drive circuit W1 to turn it off. Since the current in the load inductor L cannot change abruptly, freewheeling occurs through the lower SiC MOSFET device DUT. In the initial stage of freewheeling, the inductor current decreases very little and can be considered essentially constant. The body diode voltage drop of the SiC MOSFET device under test when the junction current value stabilizes at this point is the required value.

[0039] When the gate of a SiC MOSFET device degrades, the threshold voltage Vth increases, leading to an increase in the MOS channel resistance Rch. This causes more source-drain current to flow through the body diode, increasing the body diode voltage drop VSD. Therefore, the gate degradation of the SiC MOSFET device under test is determined based on the detected body diode voltage drop at the junction current. Specifically, if the detected body diode voltage drop of the SiC MOSFET device under test is greater than the body diode voltage drop when the SiC MOSFET device is in its brand-new state, it indicates that the gate of the SiC MOSFET device under test has degraded. When the increase in body diode voltage drop exceeds a set value, the SiC MOSFET device under test in the converter that has experienced gate degradation is replaced with a new SiC MOSFET device.

[0040] This invention also includes a controller and a SiC MOSFET driving circuit; the number of SiC MOSFET driving circuits is equal to the number of SiC MOSFET devices; each SiC MOSFET device driving circuit has a signal input port and a signal output port, wherein the signal input port is the working signal port. The controller is connected to one input port of the SiC MOSFET driving circuit, and the output port of the SiC MOSFET driving circuit outputs a driving signal to the SiC MOSFET device. CS is the working signal port of the SiC MOSFET driving circuit, and VO is the output port. When the controller outputs the working signal CS, the SiC MOSFET driving circuit outputs a driving voltage of approximately +18V. V H The SiC MOSFET is controlled to operate in the normal on-state; when there is no operating signal CS, the SiC MOSFET drive circuit outputs zero voltage. V L This puts the SiC MOSFET device in a zero-voltage state.

[0041] The method provided by this invention can be applied to various circuits as long as the SiC MOSFET device under test is at zero gate voltage and the load current equals the junction current value, allowing freewheeling through its own body diode. It is highly adaptable and can decouple the influence of junction temperature to accurately determine whether gate degradation has occurred in the SiC MOSFET device. Furthermore, it is an excellent candidate method for online monitoring, laying a solid foundation for non-stop online monitoring of gate degradation in SiC MOSFET devices. This effectively avoids economic losses caused by downtime testing, improves the accuracy of aging measurements, reduces the operation and maintenance costs of equipment containing SiC MOSFET devices such as converters, and enhances equipment reliability.

[0042] The above methods can be used to more conveniently and accurately monitor the gate aging state of the SiC MOSFET device under test.

[0043] See Figure 4 The driving voltages of the SiC MOSFET device Q1 and the SiC MOSFET device DUT are tested as follows: Figure 4 As shown, the gate degradation of the SiC MOSFET device under test (DUT) is monitored when the upper-side test SiC MOSFET device Q1 is turned off and is in a zero gate voltage state.

[0044] In this embodiment, the lower SiC MOSFET device under test (DUT) is always kept in a zero gate voltage state in the circuit. The positive gate drive voltage of the test SiC MOSFET device Q1 is turned on. When the load inductor current reaches the intersection current value, the upper test SiC MOSFET device Q1 is turned off. The inductor current freewheels through the lower test SiC MOSFET device DUT. During this freewheeling, the gate degradation of the test SiC MOSFET device DUT is monitored.

[0045] In this embodiment, the gate degradation state monitoring time of the SiC MOSFET device under test (DUT) is during the stabilization phase of the junction current value in the freewheeling phase of the double-pulse circuit. This method ensures accurate acquisition of the body diode voltage drop of the DUT.

[0046] In this embodiment, the junction current value in the freewheeling state is determined based on the third quadrant output characteristic curves of multiple sample SiC MOSFET devices at zero gate voltage. Specifically:

[0047] like Figure 5 As shown, the third quadrant output characteristic curves of multiple sample SiC MOSFET devices under different aging levels and junction temperatures were tested at zero gate voltage. The source-drain current at the intersection point was used as the experimental monitoring current, and the body diode voltage drop value at the intersection point current value was obtained to determine the gate degradation state of the SiC MOSFET device.

[0048] This invention can decouple the influence of junction temperature to accurately monitor the gate degradation state of SiC MOSFET devices, and is a good candidate method for online monitoring. It can effectively avoid economic losses caused by downtime testing, improve the accuracy of aging measurement, reduce the operation and maintenance costs of equipment containing SiC MOSFET devices such as converters, and improve the reliability of the equipment.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A gate degradation monitoring circuit for a SiC MOSFET device, characterized in that, The circuit includes a dual-pulse test circuit consisting of a test SiC MOSFET device Q1 and a SiC MOSFET device under test (DUT). The test SiC MOSFET device Q1 and the DUT form a half-bridge structure, with a parallel capacitor C on the DC side for voltage regulation, an inductive load L on the AC side, and a resistor Rshunt for measuring the branch current. The upper test SiC MOSFET device Q1 and the load inductor L form a loop with gradually increasing load current, while the lower test SiC MOSFET device DUT and the load inductor L form a freewheeling loop in the dual-pulse test circuit. The test SiC MOSFET device Q1 and the SiC MOSFET device under test (DUT) are controlled by a controller and their respective drive circuits. In the dual-pulse test circuit, the gate-source voltage of the lower SiC MOSFET device DUT is always kept at zero gate voltage. The upper SiC MOSFET device Q1 is turned on under positive gate voltage, and the current is increased to the junction current value through the load inductor L. At this time, zero gate voltage is applied to the upper SiC MOSFET device Q1 to turn it off. Since the current on the load inductor L cannot change abruptly, freewheeling is performed through the lower SiC MOSFET device DUT. In the initial stage of freewheeling, the inductor current decreases very little and is considered to remain basically unchanged. The body diode voltage drop of the SiC MOSFET device DUT when the junction current stabilizes at this time is the required value.

2. The SiC MOSFET device gate degradation monitoring circuit according to claim 1, characterized in that, The number of driving circuits for the SiC MOSFET devices is equal to the number of SiC MOSFET devices. Each driving circuit for a SiC MOSFET device has one signal input port and one signal output port, where the signal input port is the operating signal port. The controller is connected to one input port of the driving circuit for the SiC MOSFET devices, and the output port of the driving circuit for the SiC MOSFET devices outputs a driving signal to the SiC MOSFET devices. When the controller outputs the operating signal CS, the driving circuit for the SiC MOSFET devices outputs a driving voltage V of +18V. H The SiC MOSFET is controlled to operate in the normal on-state; when there is no operating signal CS, the drive circuit of the SiC MOSFET device outputs a zero voltage V. L This puts the SiC MOSFET device in a zero-voltage state. The monitoring period is the stage when the junction current value does not decrease significantly when the load inductor current freewheels, i.e., the stable stage of the junction current value.

3. The SiC MOSFET device gate degradation monitoring circuit according to claim 1, characterized in that, A clamping circuit is added to the dual-pulse test circuit. The clamping circuit includes a depletion-type SiC MOSFET device M1, a Zener diode Z1, and a Schottky diode S1. The drain of M1 is connected to the drain of the DUT, and the gate of M1 is connected to the source of the DUT, then connected in parallel to the Z1 and S1 branches. DS V is the drain-source voltage obtained directly from the DUT. DS(m) This is the drain-source voltage measured after passing through the clamping circuit; when the DUT is subjected to the DC bus voltage, the gate and source of M1 are turned off under negative voltage, and the drain-source voltage is the DC bus voltage, V. DS The clamping circuit clamps the DC bus voltage to the negative threshold voltage of M1; when the DUT is in the freewheeling phase, V DS As the reverse body diode voltage drop occurs, M1 conducts normally, and the drain-source voltage is 0V. DS The clamping circuit clamps the reverse body diode voltage drop to its own value.

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