An accelerator to process read commands

Abstract

The application relates to an accelerator for processing read commands, comprising: a logic circuit and a plurality of caches; the logic circuit, in response to receiving a plurality of first read commands sent by a host device, generates one or more second read commands according to each first read command, and stores a relationship between identification information identifying the first read command and identification information of the one or more second read commands in the cache; in response to receiving first data fed back by each second read command, processing the first data to obtain second data and first protocol information; processing one or more second data corresponding to each first read command to obtain an entry of the L2P table accessed by each first read command; generating the second protocol information and sending the second protocol information and the entry of the L2P table indicated by the second protocol information to the host device as a response to each first read command.

Description

Technical Field

[0001] This application generally relates to the field of memory. More specifically, this application relates to an accelerator for processing read commands. Background Technology

[0002] Figure 1 A block diagram of a solid-state storage device (SSD) is shown. The SSD 102 is coupled to a host computer to provide storage capabilities. The host computer and the SSD 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 (hereinafter referred to as storage device) includes interface 103, control unit 104, one or more NVM chips 105 and DRAM (Dynamic Random Access Memory) 110.

[0003] The aforementioned NVM chip 105 includes NAND flash memory, phase-change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc., which are common storage media.

[0004] The aforementioned interface 103 can be adapted to exchange data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The aforementioned control unit 104 is used to control data transmission between interface 103, NVM chip 105, and DRAM 110, and is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. Control unit 104 can be implemented in various ways, including software, hardware, firmware, or combinations thereof. For example, control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. Control unit 104 may also include a processor or controller, in which software is executed to manipulate the hardware of control unit 104 to process I / O (Input / Output) commands. Control unit 104 may also include a memory controller for coupling to DRAM 110 and accessing data in DRAM 110.

[0006] The control unit 104 includes a flash interface controller (or media interface, media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] NVM storage media typically store and retrieve data in pages, while erasing data in blocks. A block (also called a physical block) on an NVM storage medium contains multiple pages. A page (called a physical page) on the storage medium has a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0008] In storage devices, the FTL (Flash Translation Layer) is used to maintain the mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of the storage device as perceived by upper-layer software such as the operating system. Physical addresses are the addresses used to access the physical storage units of the solid-state storage device. In existing technologies, address mapping can also be implemented using intermediate address formats. For example, a logical address can be mapped to an intermediate address, and then the intermediate address can be further mapped to a physical address. Optionally, the host accessing the storage device provides the FTL.

[0009] A table structure that stores mapping information from logical addresses to physical addresses is called an FTL table (also known as an L2P table). Typically, the data items in an FTL table record the address mapping relationships in storage devices in units of specified storage sizes (e.g., 512 bytes, 2KB, 4KB, etc.).

[0010] As storage device capacity increases, the size of the L2P table increases to record more storage units, thus requiring more memory to accommodate the L2P table. To address updated storage units, the size of each entry in the L2P table also needs to increase. For example, a 32-bit L2P table entry can address 2^32 (4GB) data units. If each data unit is 4KB, 2^32 data units correspond to a 16TB storage capacity, and the L2P table itself would be 16GB (4B x 4G = 16GB, one entry is 4B, totaling 4G entries, 16GB), requiring at least 16GB of memory space. However, storage devices come in various capacities; for example, if the storage device provided to a user has a capacity of 4TB, then the L2P table itself could be 4GB. However, to provide 4TB of storage space, if each data unit is 4KB, then there would be 1GB of units, which is 2^30. Therefore, the L2P table would need to manage 2^30 data units, meaning each entry in the L2P table would only need to be 30 bits in size. Consequently, the L2P table size would be 30 * 2^30 bits (3.75GB, less than 4GB). However, due to limitations imposed by memory chips and CPU addressing methods, CPU addressing channels typically use data widths in multiples of 32 bits or bytes, and memory chips also generally use data widths in multiples of bytes. Therefore, while a 30-bit L2P table entry size reduces the overall size of the L2P table, entries crossing byte boundaries require, for example, two or more bus or memory accesses to load into the CPU. This significantly increases the loading time for L2P table entries, limiting the performance of the storage device.

[0011] To reduce the memory space occupied by L2P tables when providing storage devices of various capacities, and to reduce or eliminate the impact of non-byte-aligned L2P table entries on CPU or other devices within the chip accessing L2P table entries, compressed L2P tables are typically provided. The size of entries in a compressed L2P table may not be an integer multiple of bytes. Furthermore, compressed L2P table entries are tightly packed in memory without leaving unused memory space between entries for byte alignment. However, to eliminate the impact of using compressed L2P tables on the CPU or other devices, the CPU or other devices typically still access the L2P table in their existing byte-aligned or byte-multiple-aligned manner. Summary of the Invention

[0012] When using a hardware accelerator to accelerate the host device's access to the L2P table in the memory, in order to reduce the burden on the CPU introduced by the execution of software access to the L2P table and improve the L2P table access performance, in order to improve the processing efficiency of access commands, it is desirable to provide parallel access command processing capabilities in the hardware accelerator so that the hardware accelerator can process multiple access commands provided by the host device in parallel, so as to perform parallel access to the L2P table.

[0013] According to a first aspect of this application, an accelerator for processing read commands according to the first aspect of this application is provided for coupling a host device with a memory and accelerating the host device's access to an L2P table in the memory, characterized in that it includes: logic circuitry and multiple caches;

[0014] The logic circuit, in response to receiving multiple first read commands sent by the master device, generates one or more second read commands based on each first read command, and stores the relationship between first identification information identifying the first read command and second identification information identifying the corresponding one or more second read commands in a cache; and in response to receiving first data fed back from the memory based on each second read command, processes the first data to obtain second data and first protocol information, determines one or more second data corresponding to each first read command and generates second protocol information based on the first protocol information and the relationship, processes the one or more second data corresponding to each first read command to obtain the entry of the L2P table indicated by each first read command; and sends the second protocol information and the entry of the L2P table indicated by it as a response to each first read command to the master device;

[0015] The memory includes multiple aligned storage units, each used to store second data, which includes partial data of one or more entries of an L2P table; the partial data of one or more entries of the L2P table does not need to be stored in the memory according to byte boundary alignment; the first protocol information includes second identification information, and the second protocol information includes first identification information.

[0016] According to the first accelerator of the first aspect of this application, a second accelerator according to the first aspect of this application is provided, wherein the logic circuit includes: a parsing module, a calculation module, and a command generation module; wherein...

[0017] The parsing module, in response to receiving the plurality of first read commands, parses each first read command to obtain its corresponding first identifier information and address index, and caches the address index in the first cache;

[0018] The calculation module is coupled to the first cache, calculates the address of the memory accessed by one or more second read commands corresponding to each first read command according to the address index, and sets a corresponding second identification information for each second read command, and stores the relationship between the first identification information and its corresponding one or more second identification information in the second cache;

[0019] The command generation module is coupled to the computing module, generates one or more second read commands corresponding to each first read command based on the address and the second identification information, and sends the one or more second read commands to the memory.

[0020] According to the second accelerator of the first aspect of this application, a third accelerator according to the first aspect of this application is provided, wherein the parsing module, the computing module and the command generation module process multiple first read commands in parallel.

[0021] According to the third accelerator of the first aspect of this application, a fourth accelerator according to the first aspect of this application is provided, wherein the partial data is the valid data of the entries of the L2P table; only the valid data of each entry of the L2P table is stored in the memory; each storage unit of the memory stores the valid data of one entry, the valid data of multiple entries, or a portion of the valid data of an entry; the length of the valid data of the L2P table entry is less than the data length corresponding to its entry and less than the size of each storage unit.

[0022] According to the fourth accelerator of the first aspect of this application, a fifth accelerator according to the first aspect of this application is provided, wherein the valid data of each entry in the L2P table is sequentially concatenated end to end and stored in each storage cell in the memory according to the size and address of the storage cell; the valid data of some entries in the memory is not aligned according to storage cell alignment and / or byte alignment.

[0023] According to the fifth accelerator of the first aspect of this application, a sixth accelerator according to the first aspect of this application is provided, wherein the logic circuit, in response to receiving first data fed back by a second read command, parses the first data to obtain first protocol information and second data corresponding to the first data; or first protocol information, second data and a marker; wherein the marker is used to identify the position of the last bit in the valid data of the entry for accessing the L2P table indicated by each first read command in the corresponding second data;

[0024] The logic circuit further responds to determining the second data of all second read commands corresponding to any first read command received according to the first protocol information, parsing the valid data of the entry corresponding to the first read command from the second data of all second read commands corresponding to any first read command, and generating response data for the first read command based on the first identification information of the first read command and the valid data of its corresponding entry.

[0025] According to the sixth accelerator of the first aspect of this application, a seventh accelerator according to the first aspect of this application is provided, wherein the logic circuit further includes a merging unit; the merging unit merges the valid data and empty bit data of the entry corresponding to each first read command with respect to the entry length of the L2P table indicated by each first read command to obtain the entry of the L2P table indicated by it, wherein the valid data is located in the first N consecutive bits of the first entry, and N is the length of the valid data;

[0026] Second protocol information is generated based on the first protocol information of one or more second read commands corresponding to each first read command, and the entries and the second protocol information are merged to obtain data as a response to the first read command.

[0027] According to the seventh accelerator of the first aspect of this application, an eighth accelerator according to the first aspect of this application is provided, wherein the merging unit updates a marker in response to receiving an entry for accessing the L2P table indicated by each first read command, such that the updated marker indicates the position of the last bit of the valid data of the entry for accessing the L2P table indicated by each first read command or the entry for accessing the L2P table indicated by each first read command.

[0028] According to any one of the first to eighth accelerators of the first aspect of this application, a ninth accelerator according to the first aspect of this application is provided, wherein the plurality of caches includes: a third cache, a fourth cache, a fifth cache, a sixth cache, and a seventh cache; wherein the third cache is coupled to the fourth and fifth caches and caches one or more first data; the fourth cache is used to cache first protocol information of one or more second read commands; the fifth cache is used to cache one or more second data and the tag; the sixth cache is coupled to the fifth cache and is used to cache the entry corresponding to each first read command and the updated tag; the seventh cache is coupled to the fourth and sixth caches and is used to cache data in response to each first read command.

[0029] According to the ninth accelerator of the first aspect of this application, a tenth accelerator according to the first aspect of this application is provided, wherein the logic circuit, in response to receiving a response to a second read command, stores the response to the second read command in the third cache;

[0030] In response to storing the response to the second read command in the third cache, the first protocol information obtained from the response to the second read command in the third cache is stored in the fourth cache;

[0031] In response to storing the response to the second read command in the third cache, the second data and the second identification information are obtained from the response to the second read command in the third cache and stored in the fourth cache;

[0032] Specifically, based on the relationship between the first and second identification information stored in the second cache, in response to receiving a response to all second read commands generated according to any first read command, the merging unit retrieves the valid data of the entry for accessing the L2P table indicated by the first read command from one or more second data in the fifth cache, merges the valid data of the entry with empty bit data according to the entry length to obtain the entry, and stores the entry in the sixth cache; and updates a flag indicating the position of the last bit of the retrieved entry or the valid data of the entry in the sixth cache; the updated flag is also stored in the sixth cache.

[0033] The entry and the updated identifier are retrieved from the sixth cache. The second protocol information corresponding to the first protocol information is retrieved from the second cache. A response to the first read command is generated based on the entry and the second protocol information and stored in the seventh cache.

[0034] According to the tenth accelerator of the first aspect of this application, an eleventh accelerator according to the first aspect of this application is provided, wherein, in response to obtaining second identification information from the response to the second read command in the third cache and storing it in the fourth cache, and obtaining second data and a tag from the response to the second read command in the third cache and storing it in the fifth cache; and deleting the response to the second read command from the third cache.

[0035] According to the eleventh accelerator of the first aspect of this application, a twelfth accelerator according to the first aspect of this application is provided, wherein, in response to storing first protocol information of the second read command in a fourth cache, a second cache is also accessed according to the first protocol information to determine whether all second read commands corresponding to the first read command used to generate the second read command have been received.

[0036] According to the twelfth accelerator of the first aspect of this application, a thirteenth accelerator according to the first aspect of this application is provided, wherein if not all the second read commands corresponding to the first read command used to generate the second read command have been received, the number of all the second read commands corresponding to the first read command that have been received or have not been received is marked.

[0037] According to the thirteenth accelerator of the first aspect of this application, a fourteenth accelerator according to the first aspect of this application is provided, wherein, if all second read commands corresponding to the first read command used to generate the second read command have been received, the valid data of the entry for accessing the L2P table indicated by the first read command is obtained from all second data of all the second read commands in the fifth cache, and the valid data of the entry is merged with null bit data to obtain the entry, and the entry is stored in the sixth cache; and all second data and tags of all the second read commands are deleted from the fifth cache.

[0038] According to the fourteenth accelerator of the first aspect of this application, a fifteenth accelerator according to the first aspect of this application is provided, wherein if all second read commands corresponding to the first read command used to generate the second read command have been received, all first protocol information of all the second read commands is deleted from the fourth cache.

[0039] According to the fifteenth accelerator of the first aspect of this application, a sixteenth accelerator according to the first aspect of this application is provided, wherein, in response to storing the entry for accessing the L2P table indicated by the first read command for generating the second read command in the sixth cache, a response to the first read command is generated based on the second protocol information of the first read command and the entry obtained from the sixth cache, and stored in the seventh cache; and the second protocol information of the first read command and its corresponding first protocol information are deleted from the second cache, and the entry is deleted from the sixth cache.

[0040] According to the sixteenth accelerator of the first aspect of this application, a seventeenth accelerator according to the first aspect of this application is provided, wherein, in response to storing a response to the first read command in the seventh cache, a response to the first read command is retrieved from the seventh cache and sent to the master device, and a response to the first read command is deleted from the seventh cache.

[0041] According to the seventeenth accelerator of the first aspect of this application, an eighteenth accelerator according to the first aspect of this application is provided, wherein, in response to generating one or more second read commands according to the first read command, the address index of the first read command is deleted from the first cache.

[0042] According to any one of the ninth to eighteenth accelerators of the first aspect of this application, a nineteenth accelerator according to the first aspect of this application is provided, wherein the second cache, the fourth cache, the fifth cache or the sixth cache is a cache array, the cache array comprising a plurality of cache units, each cache unit being used to store the relationship between the first identification information of each first read command and one or more corresponding second identification information, the first protocol information of one or more second read commands corresponding to each first read command, the response data corresponding to each second read command or the entry and update marker corresponding to each first read command.

[0043] According to the nineteenth accelerator of the first aspect of this application, a twentieth accelerator according to the first aspect of this application is provided, wherein, after the merging unit determines, based on the second identification information of each second read command, that a response to all second read commands has been received, it retrieves the valid data of the entry for accessing the L2P table indicated by the first read command from one or more second data in the fifth cache, merges the valid data of the entry with empty bit data according to the entry length to obtain the entry, and stores the entry in the sixth cache.

[0044] An accelerator according to the first value of the first aspect of this application is provided, and a twenty-first accelerator according to the first aspect of this application is provided, wherein both the first protocol information and the second protocol information include AXI protocol information.

[0045] According to the control component of the second aspect of this application, a first control component according to the second aspect of this application is provided, including an accelerator as described in any one of the first to twenty-first aspects provided in the first aspect. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0047] Figure 1 A block diagram of a prior art solid-state storage device;

[0048] Figure 2A A schematic diagram of the control component structure provided in an embodiment of this application is shown;

[0049] Figure 2B This illustrates the relationship between the identification information of each read command A provided in the embodiments of this application and the identification information of one or more corresponding read commands B;

[0050] Figure 2C This application provides a schematic diagram of the L2P table structure in memory according to an embodiment of the present application.

[0051] Figure 2D A schematic diagram illustrating the conversion between L2P table entries perceived by the master device and L2P table entries stored in the memory, as provided in this application.

[0052] Figure 3 A block diagram of an accelerator for processing read commands according to an embodiment of this application is shown;

[0053] Figure 4A This diagram illustrates how the L2P accelerator processes the first data corresponding to each read command B to obtain the second data and protocol information.

[0054] Figure 4B A schematic diagram showing the logic circuit's response to each read command A is shown.

[0055] Figure 5 The processing mechanism of the accelerator in parallel processing of multiple read commands A was demonstrated;

[0056] Figure 6A A schematic diagram of another type of accelerator is shown;

[0057] Figure 6B This application illustrates a schematic diagram showing the data storage process of each cache in the logic circuit of an embodiment.

[0058] Figure 6C A schematic diagram of the structure of multiple caches in the logic circuit of an embodiment of this application is shown. Detailed Implementation

[0059] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0060] Figure 2A A schematic diagram of the control component structure provided in an embodiment of this application is shown.

[0061] exist Figure 2A In this system, the control components include a master device, an accelerator, and a slave device. For example, the master device may be a CPU, a media interface controller, or a processing core; the slave device may be a memory controller. The master device and the accelerator, and / or the accelerator and the slave device, are coupled, for example, via a bus. As another example, the accelerator in this embodiment may be an L2P accelerator, used to accelerate the master device's access to L2P tables in memory.

[0062] The control unit is also coupled to an external memory. Figure 2A The memory controller is used to access external memory (DRAM). For example, an accelerator includes a slave interface and a master interface. The accelerator is coupled to a bus via both the slave and master interfaces. Thus, one or more master devices of the control unit (e.g., CPU, media interface controller) can access the accelerator as a bus slave via the slave interface. Conversely, the accelerator can access one or more slave devices of the control unit (e.g., the memory controller) as a master via the master interface.

[0063] For ease of identification, the read command sent by the master device to the accelerator will be identified as read command A, and the read command sent by the accelerator to the slave device will be identified as read command B.

[0064] As an example, a memory located outside the control unit is used to store L2P tables. The master device can access L2P table entries in a designated storage space of the external memory. The master device sends a read command A to the bus to access an L2P table entry. The bus sends read command A to an L2P accelerator coupled to the bus. The L2P accelerator determines the storage location of the corresponding entry in the L2P table stored in the memory based on the address indicated in the received read command A, and sends one or more read commands B to the slave device (such as the memory controller) to retrieve the corresponding L2P table entry data from the DRAM. The L2P accelerator processes the L2P table entry data provided by the memory controller to obtain the response to read command A (the data of the L2P table entry to be accessed), and then the L2P accelerator sends the data of the L2P table entry to be accessed to the master device through its slave device interface.

[0065] As another example, a master device can send a single read command A to the bus to access one entry in the L2P table, or it can send multiple read commands A to the bus to access multiple entries in the L2P table simultaneously. For a single read command A, the L2P accelerator can process it using the procedures described above. However, when multiple read commands A are sent to the bus to access multiple entries in the L2P table simultaneously, since each read command A may correspond to multiple read commands B, the L2P accelerator only considers that all the data accessed by a single read command A has been received by the L2P accelerator when it receives feedback data from the memory controller for all read commands B corresponding to each read command A. Therefore, when processing multiple read commands A in parallel, the L2P accelerator needs to know which read command A corresponds to the data fed back by the memory controller in order to determine whether all the data accessed by a single read command A has been received. To facilitate identification of which read command A corresponds to the data returned by the memory controller, the L2P accelerator, when issuing one or more read commands B to the slave device (such as the memory controller) via the bus, also sets identification information (e.g., ID) for each read command B, constructs a relationship between the identification information of each read command A and the identification information of its corresponding one or more read commands B, and stores this relationship. Based on this relationship and the identification information of the read command B carried in the data returned by the memory controller, the L2P accelerator can determine whether all the data accessed by a read command A has been received.

[0066] Figure 2B This illustrates the relationship between the identification information of each read command A provided in the embodiments of this application and the identification information of one or more corresponding read commands B.

[0067] For example, the master device sends two read commands to the bus, namely read command A1 and read command A2. Read command A1 corresponds to the generation of read commands B11 and B12, and read command A2 corresponds to the generation of read commands B21 and B22. Identification information is represented by IDs. Therefore, the identification information for read command A1 is represented as ID1, the identification information for read command A2 is represented as ID2, the identification information for read command B11 is represented as ID11, the identification information for read command B12 is represented as ID12, the identification information for read command B21 is represented as ID21, and the identification information for read command B22 is represented as ID22. Figure 2B In the L2P accelerator, the relationship between identification information ID1 and identification information ID11 and ID12 is recorded, and the relationship between identification information ID2 and identification information ID21 and ID22 is recorded.

[0068] Figure 2C A schematic diagram of the L2P table structure in memory provided in an embodiment of this application is shown.

[0069] In this application, such as CPU or control unit ( Figure 1 The L2P table entries accessed by other bus devices (as shown) contain not only valid data but also null bits. As mentioned above, the valid data is determined by the number of data units provided by the addressing NVM chip. Null bits, on the other hand, are bits in the L2P table entry other than the valid data. For example, if other bus devices, such as the CPU or control unit, access an L2P table entry with a length of 64 bits and valid data of 30 bits, then the null bits will be 34 bits. The data corresponding to the valid data will be referred to as valid data in the following text.

[0070] See Figure 2C For example, to reduce the waste of memory storage resources, only the valid data of each entry in the L2P table is stored in the memory cells, and the valid data of each L2P table entry is stored in the memory space provided by the memory in a head-to-tail order. The size of the memory cell does not change with the size of the stored L2P table entries. For example, the size of the memory cell is 64 bits, regardless of whether the cell stores all the data (valid data + null bits) of the L2P table entry or just the valid data, its size is 64 bits. Therefore, when only the valid data of each L2P table entry is stored in the memory, each memory cell can store the valid data of one or more L2P table entries, or store part of the valid data of one L2P table entry. For example, if the valid data of an L2P table entry is 30 bits, the first memory cell will store the valid data of the L2P table entries corresponding to logical addresses LBA=0 and LBA=1, as well as the first 4 bits of valid data of the L2P table entry corresponding to LBA=2, while the remaining 26 bits of valid data of the L2P table entry corresponding to LBA=2 will be stored in the next memory cell.

[0071] Figure 2C In this context, a marker of the form PBA(i) represents one of the L2P table entries stored in memory (its value is the i-th physical address (PBA) of the L2P table, that is, the physical address (PBA) corresponding to the logical address LBA = i, where i is, for example, an integer). See also Figure 2CSince the valid data of each entry of the L2P table is stored in memory, if the valid data of each entry of the L2P table is 30 bits, then the 30 bits starting from the 0 byte address of memory store the valid data of L2P table entry PBA(0), the 31st to 60th bits starting from the 0 byte address of memory store the valid data of L2P table entry PBA(1), the 61st to 64th bits starting from the 0 byte address of memory store the first 4 bits of the valid data of L2P table entry PBA(2), and the remaining 26 bits of the valid data of L2P table entry PBA(2) are stored at the position starting from the 8 byte address of memory. Next, the valid data of L2P table entry PBA(3) is stored in bits 27 to 56 of memory starting from the 8-byte address. The first 8 bits of the valid data of L2P table entry PBA(4) are stored in bits 57 to 64 of memory starting from the 8-byte address. The remaining 22 bits of the valid data of L2P table entry PBA(4) are stored in memory starting from the 16-byte address. The valid data of L2P entry PBA(5) is stored in bits 23 to 52 of memory starting from the 16-byte address. The first 12 bits of the valid data of L2P entry PBA(6) are stored in bits 53 to 64 of memory starting from the 16-byte address. The remaining 18 bits of the valid data of L2P entry PBA(6) are stored in memory starting from the 24-byte address. The valid data of L2P entry PBA(7) is stored in bits 19 to 48 of memory starting from the 24-byte address, while bits 49 to 64 of memory starting from the 24-byte address are empty bits.

[0072] Therefore, one or more entries in the L2P table are not aligned to byte boundaries or to the read data bit width in memory. Consequently, the storage space occupied by the L2P table in memory is smaller than the size of the L2P table perceived by the CPU.

[0073] According to embodiments of this application, the CPU accesses the L2P table using logical address LBA as an index, while the L2P accelerator calculates the address of the valid data of the corresponding entry in the L2P table in memory based on the logical address LBA, and obtains the L2P table entry to be accessed through one or more memory accesses in response to the CPU's access to the L2P table. Since the size of the L2P table entry accessed by the CPU in this application differs from the size of the L2P table entries stored in memory, during the L2P table access process, the L2P accelerator needs to convert the L2P table entries stored in memory into L2P table entries accessible to the CPU, or convert L2P table entries accessible to the CPU into L2P table entries stored in memory for storage.

[0074] Figure 2DThis is a schematic diagram illustrating the conversion between L2P table entries perceived by the master device and L2P table entries stored in the memory, as provided in this application.

[0075] As an example, an L2P table stored in memory (SRAM or DRAM) consists of multiple entries, and each entry in the L2P table is addressed by a logical address (denoted as LBA). Figure 2D In this architecture, the L2P table entries perceived by the master device correspond one-to-one with the L2P table entries stored in memory. Therefore, the L2P table entries perceived by the master device and the L2P table entries stored in memory have the same number of entries. For example, if the L2P table includes 8 entries, namely entry 0, entry 1, entry 2, entry 3, entry 4, entry 5, entry 6, and entry 7. The size of the L2P table entries perceived by the master device is M bits, and the size of the L2P table entries stored in memory is N bits, where M and N are both positive integers.

[0076] To facilitate, for example, CPU access to the logical L2P table, the size of M is, for example, an integer multiple of bytes (e.g., 8 bytes), so that entries in the logical L2P table are aligned to 8 bytes or bytes. Figure 2D From the perspective of the CPU accessing the logical L2P table, each entry in the L2P table perceived by the master device is M bits in size. Figure 2A In the example, M = 64), the entries of the L2P table perceived by the master device are arranged sequentially in the storage space, one end to the other. The corresponding L2P table entry is obtained by indexing the storage space of the L2P table perceived by the master device using a logical address (LBA). For example, the L2P table entry address = base address + LBA * size(L2P entry), where size(L2P entry) represents the storage space occupied by each entry. The L2P table entries record the addresses used by the NVM chip (called physical addresses, denoted as PBA). Since the L2P table perceived by the master device is aligned to 8 bytes or bytes, the starting address of each entry in the storage space is located at a starting position of a byte or an integer multiple of 8 bytes, and the ending position of the entry is located at an ending position of a byte or an integer multiple of 8 bytes. Figure 2C In the example, when the CPU accesses the corresponding entry in the L2P table using the logical address (LBA) as an index, it obtains the address of the corresponding entry in the L2P table by, for example, LBA*8 (64 bits corresponding to 8 bytes).

[0077] Since each entry in the L2P table perceived by the master device may contain some or all valid data, N equals M when all entries in the L2P table perceived by the master device contain valid data. When each entry in the L2P table perceived by the master device contains some valid data and some empty bits, the size N of the L2P table entries stored in the memory is equal to the number of valid data entries in the L2P table perceived by the master device. The number of valid data entries in the L2P table perceived by the master device is determined based on the number of data units (e.g., pages) provided by the addressing NVM chip. For example, to address 2^30 data units, N is 30. Generally, if the entries in the L2P table stored in the memory can address one of 2^n data units, then N = n. As an example, Figure 2D In this context, N = 30. The L2P table stored in the memory stores the valid data for each entry, and the valid data for each entry is stored in the memory space provided by the memory in a head-to-tail order, with no unused storage space between adjacent entries. Therefore, the start and / or end positions of some entries in the memory are not located at byte boundaries.

[0078] Figure 3 A block diagram of an accelerator for processing read commands according to an embodiment of this application is shown.

[0079] exist Figure 3 In this accelerator, a logic circuit is used to couple a master device to a memory and accelerate the master device's access to an L2P table in the memory. The accelerator includes: logic circuitry and multiple caches; the logic circuitry responds to receiving multiple read commands A from the master device; generates one or more read commands B based on each read command A, and stores the relationship between identification information identifying read command A and identification information identifying the corresponding one or more read commands B in the cache; and responds to receiving first data from the memory based on each read command B, processes the first data to obtain second data and first protocol information, determines one or more second data corresponding to each read command A based on the first protocol information and the relationship, generates second protocol information, processes the one or more second data corresponding to each read command A to obtain the entry in the L2P table indicated by each read command A; and sends the second protocol information and the indicated entry in the L2P table as a response to each read command A to the master device.

[0080] As an example, in Figure 3The logic circuit includes: a parsing module, a calculation module, and a command generation module. The parsing module, in response to receiving multiple read commands A, parses each read command A to obtain its corresponding identifier information and address index, and caches the address index in a first cache of multiple caches. The calculation module, coupled to the first cache, calculates the address of the memory accessed by one or more read commands B corresponding to each read command A based on the address index; and sets a corresponding second identifier information for each read command B, storing the relationship between the first identifier information and its corresponding one or more second identifier information in a second cache. The command generation module, coupled to the calculation module, generates one or more read commands B corresponding to each read command A based on the address and the second identifier information, and sends one or more read commands B to the memory through the memory controller.

[0081] The master device sends multiple read commands A to the accelerator, as shown in process (4.1). During this process, the master device and the accelerator can exchange data via a bus, such as the AXI bus. The logic circuits in the accelerator receive the read commands A from the bus. Each read command A indicates the address index of the L2P table entry perceived by the master device, for example, the logical address LBA; it also indicates identification information, such as an ID, used to identify the read command A itself. After receiving each read command A, the logic circuits parse each read command A to obtain the address index and identification information, etc. After parsing the address index indicated by each read command A, the logic circuit calculates the address of the L2P table entry perceived by the master device in memory based on the address index indicated by each read command A. Then, it stores the address and identification information of the L2P table entry in the cache, which is represented as process (4.2). For example, the address of the L2P table entry perceived by the master device in memory = base address + LBA * size(L2P entry), where size(L2P entry) represents the size of each L2P table entry perceived by the master device, such as 64 bits.

[0082] When each entry in the L2P table perceived by the master device contains part valid data and part empty bits, the memory only stores the valid data of the L2P table entries. This means that each memory cell stores the valid data of one or more L2P table entries perceived by the master device, or stores a portion of the valid data of the L2P table entries perceived by the master device. Furthermore, the L2P table entries are stored in memory sequentially, end-to-end. Therefore, the valid data of each L2P table entry accessed by each read command A sent by the master device can be stored in one memory cell or multiple memory cells. That is, the number of memory cells occupied by different L2P table entries accessed by the master device varies. When the L2P table entry accessed by the master device occupies multiple memory cells (the master device needs to access multiple memory cells), the logic circuit generates multiple read commands B for each read command A. Each read command B is used to read data from one memory cell, as represented by process (4.3). For example, if each L2P table entry to be accessed by read command A occupies two memory cells, the logic circuit will generate two read commands B; if each L2P table entry to be accessed by read command A occupies one memory cell, the logic circuit will generate one read command B for each read command A.

[0083] Furthermore, since the logic circuit needs to process multiple read commands A in parallel, and each read command A generates one or more read commands B, after generating one or more read commands B for each read command A, identification information is set for each read command B to identify itself, and the relationship between the identification information of each read command A and the identification information of its corresponding one or more read commands B is constructed and saved in the cache. This process is represented as process (4.4). As an example, the L2P table entry address and identification information in process (4.2) and the relationship between the identification information of each read command A and the identification information of its corresponding one or more read commands B in process (4.4) can be stored in the same cache, or they can be stored in different caches. That is to say, in the embodiments of this application, the "first cache" and the "second cache" can be the same cache or different caches. Next, the command generation module sends one or more read commands B corresponding to each read command A to the memory controller, as shown in process (4.5). Then, the memory controller reads the first data from the memory according to each read command B, as shown in processes (4.6) and (4.7). For example, if multiple memory cells in the memory are aligned to 8 bytes, and their corresponding byte addresses are 0, 8, 16, 24, etc., then each read command B is used to read 8 bytes of the first data starting from any of the aforementioned byte addresses. Then, the memory controller sends the first data read by each read command B and its corresponding first protocol information as a response to each read command B to the accelerator (also called the L2P accelerator), as shown in process (4.8). Here, the first data refers to a memory cell read according to each read command B. The data in the storage unit includes the identification information of each read command B in the first protocol information. Then, the logic circuit processes the first data corresponding to each read command B to obtain the second data and the first protocol information. Based on the first protocol information and the relationship, it determines one or more second data corresponding to each read command A and generates the second protocol information. It processes one or more second data corresponding to each read command A to obtain the entry of the L2P table to be accessed by each read command A. The protocol information P and the entry of the L2P table to be accessed indicated by it are sent to the master device as a response to each read command A. This is represented as process (4.9), where the second data refers to the part of the data of the L2P table entry to be accessed by read command A contained in the first data corresponding to each read command B, and the second protocol information includes the identification information of read command A.

[0084] As another example, in response to receiving first data from a read command B, the logic circuit parses the first data to obtain first protocol information and second data corresponding to the first data; or first protocol information, second data, and a marker; wherein the marker is used to identify the position of the last bit in the valid data of the entry accessing the L2P table indicated by each read command A in the corresponding second data; the logic circuit also responds by determining the second data of all read commands B corresponding to any read command A according to the first protocol information, parses the valid data of the entry corresponding to read command A from all the second data corresponding to read command A, and generates response data for read command A based on the identification information of read command A and the valid data of its corresponding entry.

[0085] As another example, the logic circuit also includes a merging unit. The merging unit merges the valid data and empty bits of the entry corresponding to each read command A according to the entry length indicated by each read command A to obtain the entry for accessing the L2P table. The valid data is located in the first N consecutive bits of the first entry, where N is the length of the valid data. Second protocol information is generated based on the first protocol information of one or more read commands B corresponding to each read command A. The entry and the second protocol information are then merged to obtain data as a response to read command A. For example, if the length of the L2P table entry read by read command A is 64 bits, and the length of the valid data is 30 bits, then the merging unit merges the obtained 30 bits of valid data with 34 bits of empty data to obtain the 64-bit L2P table entry to be read by read command A.

[0086] Figure 4A This diagram illustrates how the L2P accelerator processes the first data corresponding to each read command B to obtain the second data and the first protocol information.

[0087] As an example, in Figure 4AIn the L2P table stored in the memory, there are entries 120, 121, 122, 123, 124, ..., where each entry in the L2P table contains 30 bits of valid data, and each memory cell is 64 bits in size. If the master device sends a read command A1 to the logic circuit, where read command A1 is used to read entry 122 in the L2P table, then the first 4 bits of entry 122 in the L2P table are located in one memory cell, while the last 26 bits of entry 122 are located in another different memory cell; that is, entry 122 in the L2P table is located in two memory cells. After receiving read command A1, the L2P accelerator generates read commands B11 and B12 to access the memory based on read command A1. Read command B11 is used to read the data in the memory cell that stores the first 4 bits of entry 122, and read command B12 is used to read the data in the memory cell that stores the last 26 bits of entry 122. The L2P accelerator sends read command B11 and read command B12 to the memory controller. The memory controller reads the data from the memory cell containing the first 4 bits of entry 122 based on read command B11, and adds protocol information 11 (such as AXI protocol information) to this data to generate data M11. Protocol information 11 includes the identification information ID11 of read command B11. The memory controller sends data M11 to the L2P accelerator as a response to read command B11. Similarly, the memory controller reads the data from the memory cell containing the last 26 bits of entry 122 based on read command B12, and adds protocol information 12 (such as AXI protocol information) to this data to generate data M12. Protocol information 12 includes the identification information ID12 of read command B12. The memory controller sends data M12 to the L2P accelerator as a response to read command B12. That is, data M11 includes data stored in the storage unit containing the first 4 bits of entry 122 and protocol information 11, and data M12 includes data stored in the storage unit containing the last 26 bits of entry 122 and protocol information 12.

[0088] Furthermore, after receiving the response data M11 of read command B11 and the response data M12 of read command B12, the L2P accelerator extracts the valid data of entry 122 from data M11 and data M12 according to the number of valid data bits in the L2P table. Specifically, it processes data M11 to extract the first 4 bits of data and protocol information 11 from entry 122, and identifies these 4 bits as data P11. Similarly, it processes data M12 to extract the last 26 bits of data and protocol information 12 from entry 122, and identifies these 26 bits as data P12.

[0089] Figure 4B A schematic diagram showing the response of the L2P accelerator to each read command A is shown.

[0090] As another example, after the L2P accelerator generates read commands B11 and B12 to access the memory based on read command A1, it also records the correspondence between the identification information of read command A1 and the identification information of read command B11 and read command B12. For example, the identification information of read command A1 is ID1, the identification information of read command B11 is ID11, and the identification information of read command B12 is ID12. After receiving the response data M11 of read command B11 and the response data M12 of read command B12, the L2P accelerator processes data M11 to obtain data P11 and protocol information 11. The protocol information 11 contains identification information ID11, and data P11 represents the first 4 bits of entry 122 in data M11. The accelerator processes data M12 to obtain data P12, protocol information 12, and a marker Q. The protocol information 12 contains identification information ID12, and the marker Q identifies the position of the last bit in the valid data of the entry accessing the L2P table indicated by each read command A, and data P12 represents the last 26 bits of entry 122 in data M12. According to protocol information 11, protocol information 12, and the relationship between the recorded identification information of read command A1 and the identification information of read commands B11 and B12, the L2P accelerator knows that after receiving data M11 and data M12, all the data to be read by read command A1 is received. The valid data of the L2P table entry to be accessed corresponding to read command A1 is data P11 and data P12. The L2P accelerator concatenates data P11 and data P12 to obtain the valid data (30 bits) of the L2P table entry to be accessed by read command A1. Since the size of the L2P table entry detected by the master device is 64 bits, in other words, the size of the data to be read by read command A1 is 64 bits. Therefore, after concatenating data P11 and data P12, 34 bits of empty data are added to the end of the concatenated data to obtain the L2P table entry to be accessed by read command A1. Additionally, the L2P accelerator generates protocol information 2 for read command A1, which includes identification information ID1 for read command A1. After concatenating the valid data of the L2P table entry to be accessed by read command A1 with 34 bits of empty data, the L2P accelerator also updates the position of the marker Q so that the marker Q indicates the position of the last bit of the L2P table entry to be accessed in the concatenated data.

[0091] As another example, after the accelerator receives multiple read commands A, the parsing module, calculation module and command generation module in the logic circuit can process the multiple read commands A in parallel.

[0092] Figure 5 The processing mechanism of the accelerator in parallel processing of multiple read commands A is demonstrated.

[0093] As an example, in Figure 5 In the process, the accelerator receives two read commands, A1 and A2, from the master device. Based on read command A1, the accelerator generates two memory access commands, B11 and B12, and based on read command A2, it generates two memory access commands, B21 and B22. The following explanation uses the accelerator's processing of read commands A1 and A2 as an example to illustrate the accelerator's parallel processing mechanism.

[0094] exist Figure 5 In the diagram, T0-T4 represent multiple consecutive time periods, and the content below each time period indicates the operations performed by each module of the accelerator within that time period.

[0095] During time period T0, the parsing module receives read command A1 and parses it to obtain the address index and identification information. After obtaining the address index and identification information of read command A1, the calculation module calculates the memory address based on the address index and identification information of read command A1. Then, after calculating the memory address, it generates read command B11 and read command B12 corresponding to read command A1 based on the memory address. Next, after generating read command B11 and read command B12 corresponding to read command A1, the relationship between the identification information of read command A1 and the identification information of read command B11 and read command B12 is stored in the second cache among multiple caches.

[0096] During the T1 time period (which is the time period after the T0 time period), the accelerator receives the data corresponding to the read command B11 and stores the data corresponding to the read command B11 in the third cache.

[0097] During time period T2 (which follows time period T1), the parsing module receives read command A2 and parses it to obtain the address index and identification information. After obtaining the address index and identification information of read command A2, the calculation module calculates the memory address based on these information. Then, after calculating the memory address, it generates read commands B21 and B22 corresponding to read command A2. Next, after generating read commands B21 and B22, the relationship between the identification information of read command A2 and the identification information of read commands B21 and B22 is stored in the second cache among multiple caches. At this time, since read command A1 has not been fully processed, the second cache stores not only the relationship between the identification information of read command A2 and the identification information of read commands B21 and B22, but also the relationship between the identification information of read command A1 and the identification information of read commands B11 and B12. According to an embodiment of this application, during time period T2, although read command A1 has not yet been processed, the L2P accelerator can still process the received read command A2. Therefore, the L2P accelerator has the ability to process multiple read commands issued by the master device in parallel. Although Figure 5 The example provided uses two read commands, A1 and A2, issued by the master device. It can be understood that the L2P accelerator can process a larger number of read commands from the host in parallel.

[0098] During time period T3 (which follows time period T2), the accelerator receives the data corresponding to read command B12 and stores it in the third buffer. At this time, the third buffer stores the data corresponding to read commands B11 and B12. Further, after the accelerator receives the data corresponding to read commands B11 and B12, all data corresponding to read command A1 is received. The accelerator processes the received data corresponding to read commands B11 and B12 and concatenates them to obtain the entry of the L2P table to be accessed by read command A1. Based on the identification information of read command A1, the accelerator generates corresponding protocol information and stores this protocol information and the entry of the L2P table to be accessed by read command A1 as a response to read command A1 in the seventh buffer. At this point, since the response to read command A1 has been received, the relationship between the identification information of read command A1 and the identification information of read commands B11 and B12 in the second cache can be deleted, and the relationship between the identification information of the remaining unprocessed read command A2 and the identification information of commands B21 and B22 can be deleted.

[0099] During time period T4 (which follows time period T3), the accelerator receives the data corresponding to read commands B21 and B22 and stores this data in the third buffer. At this point, the third buffer contains the data corresponding to read commands B21 and B22; that is, all data corresponding to read command A2 has been received. The accelerator processes the received data corresponding to read commands B21 and B22 and concatenates it to obtain the entry for the L2P table that read command A2 needs to access. Based on the identification information of read command A2, it generates corresponding protocol information and stores this protocol information and the L2P table entry that read command A2 needs to access as a response to read command A2 in the seventh buffer. Since a response to read command A2 has been received, the relationship between the identification information of read command A2 and the identification information of read commands B21 and B22 in the second buffer can be deleted. Since both read command A1 and read command A2 have been processed at this time, there is no identification information for the read command to be processed in the second cache.

[0100] As can be seen from the above, when receiving data from read command B11 and read command B12, the data received from read command B11 and read command B12 can be discontinuous in time. That is, between receiving data from read command B11 and read command B12, the accelerator can process other read commands (read command A2). Therefore, during the processing of read commands A1 and A2, the accelerator can process read commands A1 and A2 in parallel.

[0101] Figure 6A A schematic diagram of another type of accelerator is shown.

[0102] exist Figure 6A The accelerator contains multiple caches, including: a first cache, a second cache, a third cache, a fourth cache, a fifth cache, a sixth cache, and a seventh cache. The third cache is coupled with the fourth and fifth caches, caching the responses to one or more read commands B. The fourth cache caches the protocol information for one or more read commands B. The fifth cache caches partial data and the tag Q of the L2P table entry to be accessed by read command A in the response to one or more read commands B. The sixth cache is coupled with the fifth cache, caching the entry corresponding to each read command A and the updated tag Q. The seventh cache is coupled with the fourth and sixth caches, caching the response data for each read command A.

[0103] The following section describes how the logic circuit caches the data corresponding to each read command B.

[0104] As an example, in response to receiving a read command B from the memory controller, the logic circuit stores the entire response to read command B into a third cache; in response to storing the response to read command B into the third cache, it retrieves the first protocol information from the response to read command B in the third cache and stores it in a fourth cache; in response to storing the response to read command B into the third cache, it retrieves the second data and identifier from the response to read command B in the third cache and stores them in a fifth cache; wherein, based on the relationship between the first identifier information and the second identifier information stored in the second cache, in response to receiving responses to all second read commands generated according to any first read command, the logic circuit merges... The unit retrieves the valid data of the L2P table entry indicated by the first read command from one or more second data sources in the fifth cache, and merges the valid data of the entry with null bits according to the entry length to obtain the entry, storing the entry in the sixth cache; and updates a flag indicating the position of the last bit of the retrieved entry or the valid data of the entry in the sixth cache; the updated flag is also stored in the sixth cache; retrieves the entry and the updated flag from the sixth cache, retrieves the second protocol information corresponding to the first protocol information from the second cache, generates a response to the first read command based on the entry and the second protocol information, and stores it in the seventh cache. Then, it retrieves the response to the first read command from the seventh cache and provides it to the master device via the bus.

[0105] Figure 6B The diagram illustrates the process of storing data in each cache in the logic circuit of an embodiment of this application.

[0106] Taking a logic circuit receiving a read command A1 from the master device, where read command A1 requests access to the data corresponding to entry 122 in the L2P table, and entry 122 is 64 bits long with 30 bits of valid data, the valid data of entry 122 is stored in two consecutive memory cells, with the first 4 bits of the valid data in the first memory cell and the remaining 26 bits in the second memory cell. Since the valid data of entry 122 is located in two consecutive memory cells, after receiving read command A1, the logic circuit generates two read commands based on read command A1: read command B11 and read command B12. Read command B11 reads the 64 bits (8 bytes) of data from the memory cell corresponding to the first 4 bits of the valid data of entry 122, and read command B12 reads the 64 bits (8 bytes) of data from the memory cell corresponding to the remaining 26 bits of the valid data of entry 122. Figure 6BIn the second cache, the logic circuit stores the identification information of read command A1 in association with the identification information of read command B11 and read command B12, for example, in the form of <identification information of read command A1, identification information of read command B11, identification information of read command B12>, as shown in process (6.1). The memory controller sends the data M11 read according to read command B11 to the L2P accelerator. The L2P accelerator controls the storage of data M11 in the third cache, as shown in process (6.2). Then, the L2P accelerator parses the data M11 to obtain protocol information 11 and data Q11, and controls the storage of protocol information 11 in the fourth cache, as shown in process (6.3), and controls the storage of data Q11 in the fifth cache, as shown in process (6.4). Here, data Q11 represents 64 bits of data read from the memory storage cell according to read command B11. In response to the memory controller sending data M12 read according to read command B12 to the L2P accelerator, the L2P accelerator controls the storage of data M12 in the third buffer, as shown in process (6.5). Then, the L2P accelerator parses data M12 to obtain protocol information 12 and data Q12, and controls the storage of protocol information 12 in the fourth buffer, as shown in process (6.6), and controls the storage of data Q12 in the fifth buffer, as shown in process (6.7). Here, data Q12 represents 64 bits of data read from the memory's storage unit according to read command B12. Although represented as processes (6.2) and (6.5) respectively, according to the embodiments of this application, the order in which the memory controller provides data M11 and M12 to the L2P accelerator is not limited. Furthermore, between the L2P accelerator receiving data M11 and M12, it may also receive response data from the memory controller for other read commands.

[0107] Based on the relationship between protocol information 11 and protocol information 12 stored in the fourth buffer and the identification information of read command A1 and the identification information of read command B11 and read command B12 stored in the second buffer, it is determined whether the data corresponding to read command B11 and read command B12 are both stored in the fifth buffer, as shown in process (6.8). After the data corresponding to read command B11 and read command B12 are both stored in the fifth buffer, the L2P accelerator retrieves the valid data of entry 122 from the fifth buffer, and merges the valid data of entry 122 with the empty bit data according to the length of entry 122 to obtain entry 122, stores entry 122 in the sixth buffer; and generates a new flag Q to indicate the position of the last bit of the retrieved entry 122 or the valid data of entry 122 in the sixth buffer, as shown in process (6.9). Then, the L2P accelerator retrieves the identification information of read command A1 from the second cache according to the correspondence between the identification information of read command A1 and the identification information of read command B11 and read command B12 recorded in the second cache, and generates corresponding protocol information 2 (containing the identification information of read command A1) based on the identification information, which is represented as process (6.10); and generates a response to read command A1 based on the generated protocol information 2 and the entry 122 retrieved from the sixth cache, and stores it in the seventh cache, which is represented as process (6.11).

[0108] According to embodiments of this application, by setting up multiple caches to record the L2P accelerator's responses to read commands from the memory controller, the L2P accelerator can simultaneously process responses to multiple read commands from the memory controller. These responses do not need to correspond to the same read command from the master device, but can correspond to multiple read commands from the master device. For example, each response received from the memory controller is recorded in a third cache, so that even if the response does not yet provide the complete entry required for the read command from the master device, the response can still be cached without affecting the reception of other responses. Furthermore, after moving a response data from the third cache to the fourth and fifth caches respectively, this data can be deleted from the third cache to reduce the occupancy of the third cache. For example, the fifth cache records the valid data of the entry the master device wants to access. Before the master device has received all the valid data for an entry, the partially received valid data from the L2P accelerator is recorded in the fifth cache. Even if the master device issues multiple read commands simultaneously, a portion of each read command received by the L2P accelerator is recorded in the fifth cache, thus supporting parallel processing of multiple read commands issued by the master device. When the L2P accelerator receives all the valid data for a certain entry from the master device, it promptly moves this valid data from the fifth cache to the sixth cache to construct the entry the master device wants to access, and clears the space occupied by this valid data in the fifth cache. Therefore, the fifth cache serves to cache multiple responses to multiple read commands issued by the master device. The sixth cache, on the other hand, serves to concatenate the entire entry the master device wants to access.

[0109] The following section uses the example of a logic circuit receiving a read command A1 from the master device and generating read commands B11 and B12 based on read command A1 to explain other operations in each buffer.

[0110] For example, in response to the read command B11, the corresponding protocol information 11 is obtained from the response to the read command B11 in the third buffer and stored in the fourth buffer, and the corresponding data Q11 and tag Q are obtained from the response to the read command B11 in the third buffer and stored in the fifth buffer; the response to the read command B11 is deleted from the third buffer.

[0111] As another example, in response to storing the protocol information 11 corresponding to the read command B11 in the fourth cache, the second cache is also accessed according to the protocol information 11 to determine whether all read commands B11 and read commands B12 corresponding to the read command A1 have been received.

[0112] As another example, if the read command B12 corresponding to read command A1 has not been received, mark the number of read commands that have been received or have not yet been received.

[0113] As another example, if both read command B11 and read command B12 have been received, the valid data of the entry for accessing the L2P table indicated by read command A1 is obtained from the data Q11 corresponding to read command B11 and the data Q12 corresponding to read command B12 in the fifth cache, and the valid data of the entry is merged with the null bit data to obtain the entry, and the entry is stored in the sixth cache; and the data corresponding to read command B11 and read command B12 and the tag Q are deleted from the fifth cache.

[0114] As another example, if both read command B11 and read command B12 have been received, the protocol 11 corresponding to read command B11 and the protocol information 12 corresponding to read command B12 are deleted from the fourth cache.

[0115] As another example, in response to storing the entry for accessing the L2P table indicated by read command A1 in the sixth cache, a response to read command A1 is generated based on the protocol information 2 corresponding to read command A1 and the entry obtained from the sixth cache, and stored in the seventh cache; and the protocol information 2 corresponding to read command A1, the protocol information 11 corresponding to read command B11, and the protocol information 12 corresponding to read command B12 are deleted from the second cache, and the entry is deleted from the sixth cache.

[0116] As another example, the response to read command A1 is stored in the seventh cache, the response to read command A1 is retrieved from the seventh cache and sent to the master device, and the response to read command A1 is deleted from the seventh cache.

[0117] As another example, in response to generating read command B11 and read command B12 based on read command A1, the address index of read command A1 is deleted from the first cache.

[0118] By promptly deleting data from the cache, cache utilization is improved, reducing the need for a large cache size while still supporting the processing of multiple concurrent read commands. For example, if the L2P accelerator supports processing a maximum of N read commands from the host simultaneously, then the sixth cache needs to cache a maximum of 6 L2P table entries and their corresponding Q values ​​simultaneously; the third cache needs to cache a maximum of 2N responses from the memory controller simultaneously; and the fourth and fifth caches need to cache a maximum of 2N data entries simultaneously. The seventh cache only needs to accommodate the response to one master device read command. The first and second caches need to cache a maximum of N data entries simultaneously. Optionally, the capacity of each cache can be smaller than these values ​​to reduce costs without significantly reducing the L2P accelerator's concurrent processing capability for master device read commands.

[0119] By way of example, the second cache, the fourth cache, the fifth cache and the sixth cache are cache arrays, each cache array comprises a plurality of cache units, each cache unit is respectively configured to store the relationship between the identification information of one read command A and the identification information of one or more corresponding read commands B, the protocol information of one or more read commands B corresponding to each read command A, the response data corresponding to each read command B, or the entry and the updated marker corresponding to each read command A.

[0120] Figure 6C shows a schematic structural diagram of a plurality of caches in a logic circuit according to an embodiment of the present application.

[0121] taking an example that the logic circuit receives two read commands A1 and A2 from a master device, generates read commands B11 and B12 according to the read command A1, and generates read commands B21 and B22 according to the read command A2, in Figure 6C , the cache array corresponding to the second cache comprises two cache units, which are respectively configured to cache the relationship between the identification information of the read command A1 and the identifications of the read commands B11 and B12, and the relationship between the identification information of the read command A2 and the identifications of the read commands B21 and B22, for example, <identifications of A1, B11 and B12>, <identifications of A2, B21 and B22>. The cache array corresponding to the fourth cache comprises four cache units, which are respectively configured to cache the protocol information of the read command B11, cache the protocol information of the read command B12, cache the protocol information of the read command B21, and cache the protocol information of the read command B22, wherein the protocol information of the read command B11 comprises the B11 identification, the protocol information of the read command B12 comprises the B12 identification, the protocol information of the read command B21 comprises the B21 identification, and the protocol information of the read command B22 comprises the B22 identification. The cache array corresponding to the fifth cache comprises four cache units, which are respectively configured to cache the response data of the read command B11, the response data of the read command B12, the response data of the read command B21 and the response data of the read command B22. The cache array corresponding to the sixth cache comprises two cache units, which are respectively configured to cache the L2P table entry to be accessed by the read command A1 and the updated marker, and cache the L2P table entry to be accessed by the read command A2 and the updated marker.

[0122] In addition, it should be understood that in Figure 6CIn this context, once the L2P table entry to be accessed by read command A1 is cached in the sixth cache, the B11 and B12 identifiers cached in the fourth cache, the relationship between the identifier information of read command A1 and the identifiers of read commands B11 and B12 in the second cache, and the B11 and B12 data in the fifth cache can be deleted. Similarly, once the L2P table entry to be accessed by read command A2 is cached in the sixth cache, the B21 and B22 identifiers cached in the fourth cache, the relationship between the identifier information of read command A2 and the identifiers of read commands B21 and B22 in the second cache, and the B21 and B22 data in the fifth cache can be deleted.

[0123] It should be noted that, for the sake of brevity, this application describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solution of this application is not limited to the order of the described actions. Therefore, based on the disclosure or teachings of this application, those skilled in the art will understand that some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this application can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions of this application. In addition, depending on the solution, the description of some embodiments in this application also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this application can also be referred to the relevant descriptions of other embodiments.

[0124] In terms of specific implementation, based on the disclosure and teachings of this application, those skilled in the art will understand that the several embodiments disclosed in this application can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or device embodiments described above, this document has divided them based on logical functions, but in actual implementation, there may be other ways of division. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0125] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An accelerator for processing read commands, used to couple a host device to a memory and accelerate the host device's access to an L2P table in the memory, characterized in that, include: Logic circuits and multiple caches; In response to receiving multiple first read commands sent by the master device, the logic circuit generates one or more second read commands based on each first read command, and stores the relationship between the first identification information that identifies the first read command and the second identification information that identifies the one or more second read commands corresponding to it in a cache; In response to receiving first data from the memory based on each second read command, the first data is processed to obtain second data and first protocol information. Based on the first protocol information and the relationship, one or more second data corresponding to each first read command are determined and second protocol information is generated. The one or more second data corresponding to each first read command are processed to obtain the entry of the L2P table indicated by each first read command. And send the second protocol information and the entry for accessing the L2P table indicated therein to the master device as a response to each first read command; The memory includes multiple aligned storage units, each used to store second data, which includes partial data of one or more entries of an L2P table; the partial data of one or more entries of the L2P table does not need to be stored in the memory according to byte boundary alignment; the first protocol information includes second identification information, and the second protocol information includes first identification information.

2. The accelerator according to claim 1, characterized in that, The logic circuit includes: a parsing module, a calculation module, and a command generation module; wherein, The parsing module, in response to receiving the plurality of first read commands, parses each first read command to obtain its corresponding first identifier information and address index, and caches the address index into the first cache of the plurality of caches; The calculation module is coupled to the first cache, calculates the address of the memory accessed by one or more second read commands corresponding to each first read command according to the address index, and sets a corresponding second identification information for each second read command, and stores the relationship between the first identification information and its corresponding one or more second identification information in the second cache; The command generation module is coupled to the computing module, generates one or more second read commands corresponding to each first read command based on the address and the second identification information, and sends the one or more second read commands to the memory.

3. The accelerator according to claim 2, characterized in that, The parsing module, the calculation module, and the command generation module process multiple first read commands in parallel.

4. The accelerator according to any one of claims 1-3, characterized in that, The logic circuit responds to receiving the first data fed back by each second read command, and parses the first data to obtain the first protocol information and second data corresponding to the first data; or the first protocol information, second data and a marker; wherein the marker is used to identify the position of the last bit in the valid data of the entry for accessing the L2P table indicated by each first read command in the corresponding second data; The logic circuit further responds to determining the second data of all second read commands corresponding to any first read command received according to the first protocol information, parsing the valid data of the entry corresponding to the first read command from the second data of all second read commands corresponding to any first read command, and generating response data for the first read command based on the first identification information of the first read command and the valid data of its corresponding entry.

5. The accelerator according to claim 4, characterized in that, The logic circuit further includes a merging unit; the merging unit merges the valid data and empty bit data of the entry corresponding to each first read command according to the entry length of the L2P table accessed by each first read command to obtain the entry of the L2P table accessed by it, wherein the valid data is located in the first N consecutive bits of the entry, and N is the length of the valid data. Second protocol information is generated based on the first protocol information of one or more second read commands corresponding to each first read command, and the entries and the second protocol information are merged to obtain data as a response to the first read command.

6. The accelerator according to claim 5, characterized in that, In response to receiving the entry for accessing the L2P table indicated by each first read command, the merging unit updates the marker such that the updated marker indicates the position of the last bit of the valid data of the entry for accessing the L2P table indicated by each first read command or the entry for accessing the L2P table indicated by each first read command.

7. The accelerator according to claim 6, characterized in that, in, The logic circuit, in response to receiving a response to the second read command, stores the response to the second read command in the third cache; In response to storing the response to the second read command in the third cache, the first protocol information obtained from the response to the second read command in the third cache is stored in the fourth cache; In response to storing the response to the second read command in the third cache, the second identification information is obtained from the response to the second read command in the third cache and stored in the fourth cache; Specifically, based on the relationship between the first identification information and the second identification information stored in the second cache, in response to receiving a response to all second read commands generated according to any first read command, the merging unit obtains the valid data of the entry for accessing the L2P table indicated by the first read command from one or more second data in the fifth cache, and merges the valid data of the entry with empty bit data according to the entry length to obtain the entry, and stores the entry in the sixth cache; and updates a flag indicating the position of the last bit of the obtained entry or the valid data of the entry in the sixth cache; the updated flag is also stored in the sixth cache; The entry and the updated identifier are retrieved from the sixth cache. The second protocol information corresponding to the first protocol information is retrieved from the second cache. A response to the first read command is generated based on the entry and the second protocol information and stored in the seventh cache.

8. The accelerator according to claim 7, characterized in that, in, In response to obtaining second identification information from the response to the second read command in the third cache and storing it in the fourth cache, and obtaining second data and a tag from the response to the second read command in the third cache and storing it in the fifth cache; Remove the response to the second read command from the third cache.

9. The accelerator according to claim 8, characterized in that, in, If all the second read commands corresponding to the first read command used to generate the second read command have been received, the valid data of the entry for accessing the L2P table indicated by the first read command is obtained from all the second data of all the second read commands in the fifth cache, and the valid data of the entry is merged with the empty bit data to obtain the entry, and the entry is stored in the sixth cache. And remove all second data and tokens from the fifth cache for all second read commands.

10. The accelerator according to any one of claims 7-9, characterized in that, The second cache, the fourth cache, the fifth cache, or the sixth cache is a cache array. The cache array contains multiple cache units. Each cache unit is used to store the relationship between the first identification information of each first read command and one or more corresponding second identification information, the first protocol information of one or more second read commands corresponding to each first read command, the response data corresponding to each second read command, or the entry and update marker corresponding to each first read command.

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