Space distributed system high speed long distance board-to-board communication system and method

Abstract

The application discloses a high-speed long-distance board-level inter-chip communication system and method for space distribution system, which is based on a hardware scheme design of SPI and LVDS; a left board-level FPGA / DSP / ARM chip is used as a host of SPI, a right board-level FPGA / DSP / ARM chip is used as a slave of SPI, the host and the slave apply four interfaces of SPI_CLK, SPI_MOSI, SPI_CS and SPI_MISO of SPI commonly, and link transmission between the two chips is realized by using LVDS transceiver chips; when the host communicates with the corresponding slave, the host can be set by a chip selection CS signal line, and the application designs an inter-board communication method suitable for different kinds of chips, which has the advantages of high communication rate, strong anti-interference capability and suitability for space distribution system.

Description

Technical Field

[0001] This invention belongs to the field of data transmission technology, and specifically relates to a high-speed, long-distance board-level chip communication system and method for aerospace distributed systems. Background Technology

[0002] Satellites and space stations contain numerous distributed electronic systems. As the complexity of these systems increases, various controller modules, such as FPGAs, DSPs, and ARMs, are combined across these systems, creating significant data and command transmission requirements. However, the communication methods used by the controllers of different nodes within aerospace distributed systems are not entirely identical. This results in the network environment being divided into several independent areas, making it difficult to maintain consistency in communication methods between systems. Furthermore, considering the differences in transmission latency between these independent partitions, collecting information from each node must cover the maximum latency of all communication methods within the system. SPI, as a high-speed, full-duplex, synchronous communication bus, is only suitable for short-distance intra-board chip-to-chip communication. Currently, SPI is primarily used for intra-board communication and has not yet been applied to high-speed, long-distance inter-board chip-to-chip communication in aerospace distributed systems. Summary of the Invention

[0003] This invention proposes a high-speed, long-distance board-level chip communication system and method for aerospace distributed systems, which solves the technical problem of high-speed, long-distance, low-power, and anti-interference communication using the SPI communication bus protocol in aerospace distributed systems.

[0004] This invention proposes a high-speed, long-distance board-level chip-to-chip communication system for aerospace distributed systems, comprising: a host chip, a slave chip, and an intermediate LVDS interface chip.

[0005] The host chip reads the host transmission buffer to determine whether the host chip has any instruction data to send to the slave chip. If no instruction data is sent to the slave chip, it will wait for the next communication cycle.

[0006] The intermediate LVDS interface chip includes a host-side transmit driver, a slave-side receive driver, a slave-side transmit driver, and a host-side receive driver.

[0007] If the master chip determines that instruction data is to be sent to the slave chip, then communication is initiated between the master and slave chips. The master chip generates a first signal, and communication begins. The first signal is sent to the master-side transmit driver, and the first signal is converted into a first differential signal by the master-side transmit driver for inter-board transmission. The slave-side receive driver receives the first differential signal and converts it into a first signal, which is then sent to the slave chip.

[0008] The slave chip generates a second signal and sends the second signal to the slave-side transmit driver. The second signal is converted into a second differential signal by the slave-side transmit driver for inter-board transmission. The master-side receive driver receives the second differential signal and converts it into a second signal before sending it to the master chip.

[0009] Furthermore, the communication between the master and slave chips further includes:

[0010] The host chip reads the host receive buffer and determines whether the host chip's receive check bit is correct. If it is incorrect, the previous data packet is resent to the host send buffer. If the receive check bit is correct, the received data is stored in the host receive buffer, and the sent data is stored in the host send buffer for transmission. The data packet transmission within one communication cycle of the host ends.

[0011] At the start of communication, the slave device reads the slave receive buffer and checks whether the slave's receive check bit is correct. If it is incorrect, the slave device sets the send check bit to zero and sends the data. If the receive check bit is correct, the received data is stored in the slave receive buffer, and the sent data is stored in the slave send buffer for transmission. The data packet transmission in one communication cycle of the slave device ends, and thus the communication in one communication cycle of the master and slave devices ends.

[0012] Furthermore, the host chip includes a first interface and a second interface. The host chip sends a first signal to the host side via the first interface through a driver.

[0013] The host-side receiver driver sends the second signal to the second interface of the host chip;

[0014] The slave chip includes a third interface and a fourth interface. The slave chip receives a first signal from the driver sent by the intermediate LVDS interface chip via the third interface; the slave chip sends a second signal from the driver sent by the driver to the intermediate LVDS interface chip via the fourth interface.

[0015] Furthermore, the first interface of the host chip includes a first SPI_CLK sub-interface, a first SPI_MOSI sub-interface, and a first SPI_CS sub-interface; the third interface of the slave chip includes a second SPI_CLK sub-interface, a second SPI_MOSI sub-interface, and a second SPI_CS sub-interface.

[0016] The host-side transmit driver includes a first input interface, a second input interface, a third input interface, a first differential signal output interface, a second differential signal output interface, and a third differential signal output interface;

[0017] The host-side receiver driver includes a first differential signal receiving interface, a second differential signal receiving interface, a third differential signal receiving interface, a first output interface, a second output interface, and a third output interface;

[0018] Based on the SPI communication protocol, the first signal includes the SPI_CLK signal, the SPI_MOSI signal, and the SPI_CS signal. The host chip sends the SPI_CLK signal to the first input interface through the first SPI_CLK sub-interface, the SPI_MOSI signal to the second input interface through the first SPI_MOSI sub-interface, and the SPI_CS signal to the third input interface through the first SPI_CS sub-interface.

[0019] The host-side transmit driver converts the SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal into a first differential signal group, which includes the SPI_CLK differential signal, SPI_MOSI differential signal, and SPI_CS differential signal. These signals are then output through the first differential signal output interface, the second differential signal output interface, and the third differential signal output interface, respectively.

[0020] The slave-side receive driver uses the first differential signal receiving interface, the second differential signal receiving interface, and the third differential signal receiving interface to receive the SPI_CLK differential signal, the SPI_MOSI differential signal, and the SPI_CS differential signal from the first differential signal output interface, the second differential signal output interface, and the third differential signal output interface, respectively. After converting them into SPI_CLK signals, SPI_MOSI signals, and SPI_CS signals, they are then output through the first output interface, the second output interface, and the third output interface, respectively.

[0021] The slave chip receives the SPI_CLK signal output from the first output interface via the second SPI_CLK sub-interface, the SPI_MOSI signal output from the second output interface via the second SPI_MOSI sub-interface, and the SPI_CS signal output from the third output interface via the second SPI_CS sub-interface.

[0022] Furthermore, the fourth interface of the slave chip is the first SPI_MISO interface, and the second interface of the host chip is the second SPI_MISO interface;

[0023] The slave-side transmitter driver includes a fourth input interface and a fourth differential signal output interface;

[0024] The host-side receiver driver includes a fourth differential signal receiving interface and a fourth output interface;

[0025] Based on the SPI communication protocol, the second signal is the SPI_MISO signal, and the slave chip sends the SPI_MISO signal to the fourth input interface through the first SPI_MISO interface;

[0026] The slave-side driver converts the SPI_MISO signal into an SPI_MISO differential signal, which is then used as the second differential signal and output through the fourth differential signal output interface.

[0027] The host-side receiver driver uses the fourth differential signal receiver interface to receive the SPI_MISO differential signal from the fourth differential signal output interface, converts it into an SPI_MISO signal, and then outputs it through the fourth output interface.

[0028] The second SPI_MISO interface of the host chip receives the SPI_MISO signal output from the fourth output interface.

[0029] Furthermore, the host chip or slave chip is an FPGA, and the GPIO of the FPGA chip is configured as the SPI_CLK interface, SPI_MOSI interface, SPI_CS interface and SPI_MISO interface of the SPI protocol for communication.

[0030] Furthermore, the host chip or slave chip is a DSP or ARM, and communication is performed using the SPI_CLK interface, SPI_MOSI interface, SPI_CS interface and SPI_MISO interface of the SPI hard core of the DSP or ARM chip.

[0031] This invention also proposes a high-speed, long-distance board-level chip-to-chip communication method for aerospace distributed systems, comprising:

[0032] The process of the master chip sending the first signal to the slave chip is as follows: the master chip sends the first signal to the intermediate LVDS interface chip. The intermediate LVDS interface chip includes a master-side transmit driver, a slave-side receive driver, a slave-side transmit driver, and a master-side receive driver. The master-side transmit driver receives the first signal and converts it into a first differential signal group before sending it to the slave-side receive driver. The slave-side receive driver converts the first differential signal group into the first signal and sends it to the slave chip.

[0033] The process of the slave chip sending the second signal to the master chip is as follows: the slave-side sending driver receives the second signal sent by the slave chip, converts it into a second differential signal, and then sends it to the master-side receiving driver. The master-side receiving driver converts the second differential signal into a second signal and sends it to the master chip.

[0034] Furthermore, the sending of the first signal from the host chip to the slave chip further includes:

[0035] Based on the SPI communication protocol, the first signal includes the SPI_CLK signal, the SPI_MOSI signal, and the SPI_CS signal. The host chip sends the SPI_CLK signal, the SPI_MOSI signal, and the SPI_CS signal to the host-side transmit driver.

[0036] The host-side transmit driver converts the SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal into a first differential signal group before outputting them. The first differential signal group includes the SPI_CLK differential signal, the SPI_MOSI differential signal, and the SPI_CS differential signal.

[0037] The slave-side receiver driver receives the SPI_CLK differential signal, SPI_MOSI differential signal, and SPI_CS differential signal, converts them into SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal respectively, and then outputs them respectively.

[0038] The slave chip receives the SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal.

[0039] Furthermore, the process of the slave chip sending a second signal to the master chip further includes:

[0040] Based on the SPI communication protocol, the second signal is the SPI_MISO signal, and the slave chip sends the SPI_MISO signal to the slave-side transmit driver;

[0041] The slave-side transmitter converts SPI_MISO into an SPI_MISO differential signal as the second differential signal output.

[0042] The host-side receiver driver receives the SPI_MISO differential signal, converts it into an SPI_MISO signal, and then outputs it.

[0043] The host chip receives the SPI_MISO signal.

[0044] This invention combines the advantages of SPI and LVDS to achieve high-speed communication over long distances between different controllers. It is highly suitable for communication processes in aerospace distributed systems, and features a consistent slave interface, allowing for plug-and-play functionality and equivalent replacement. This invention can be applied to communication between modules in aerospace distributed systems, enabling communication between distributed systems to have advantages such as high transmission rate, long transmission distance, low power consumption, and strong anti-interference capabilities. Attached Figure Description

[0045] Figure 1 This is a communication diagram of the left-side board-level master and the right-side board-level slave of the present invention.

[0046] Figure 2This is a functional diagram of the left-side board-level master and the right-side board-level slave of the present invention.

[0047] Figure 3 This is a flowchart of the master-slave transmission process of the present invention.

[0048] Figure 4 This is a schematic diagram of the master-slave transmission protocol packet format of the present invention. Detailed Implementation

[0049] In the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details; in other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention.

[0050] This invention provides a high-speed, long-distance board-level chip-to-board communication system and method for aerospace distributed systems.

[0051] The high-speed, long-distance board-level chip-to-chip communication system for aerospace distributed systems of the present invention includes: a host chip, a slave chip, and an intermediate LVDS interface chip.

[0052] The host chip includes a first interface and a second interface. The host chip sends a first signal to the intermediate LVDS interface chip through the first interface.

[0053] The intermediate LVDS interface chip includes a host-side transmit driver LVDS31-1, a slave-side receive driver LVDS32-1, a slave-side transmit driver LVDS31-2, and a host-side receive driver LVDS32-2. The host-side transmit driver receives a first signal, converts it into a first differential signal group, and then sends it to the slave-side receive driver LVDS32-1. The slave-side receive driver LVDS32-1 converts the first differential signal group into a first signal and sends it to the slave chip.

[0054] The slave-side sender LVDS31-2 receives the second signal sent by the slave chip, converts it into a second differential signal, and then sends it to the host-side receiver LVDS32-2. The host-side receiver LVDS32-2 converts the second differential signal into a second signal and sends it to the second interface of the host chip.

[0055] The slave chip includes a third interface and a fourth interface. The slave chip receives a first signal from the driver sent by the intermediate LVDS interface chip via the third interface; the slave chip sends a second signal from the driver sent by the driver to the intermediate LVDS interface chip via the fourth interface.

[0056] In one embodiment, taking full-duplex communication between the left-side board-level master and the right-side board-level slave as an example, such as... Figure 1 The diagram illustrates the communication between the left-side board-level master and the right-side board-level slave, including a left-side board-level FPGA / DSP / ARM chip, a right-side board-level FPGA / DSP / ARM chip, and a middle LVDS interface chip. The left-side board-level FPGA / DSP / ARM acts as the master for SPI communication, and its master control chip can be an FPGA, DSP, or ARM chip. The right-side board-level FPGA / DSP / ARM acts as the slave for SPI communication, and its master control chip can be an FPGA, DSP, or ARM chip. When the master control chip of the left-side board-level master and the right-side board-level slave is an FPGA, the master and slave need to configure their GPIOs to the four common SPI interfaces: SPI_CLK, SPI_MOSI, SPI_CS, and SPI_MISO for communication. When the master control chip of the left-side board-level master and the right-side board-level slave is a DSP or ARM with an SPI hard core, the master and slave can use the four interfaces of their SPI hard core: SPI_CLK, SPI_MOSI, SPI_CS, and SPI_MISO for communication.

[0057] In one embodiment, such as Figure 2 As shown, both the left-side board-level FPGA / DSP / ARM and the right-side board-level FPGA / DSP / ARM include:

[0058] SPI_CLK is used for the clock signal and is generated by the host computer on the left side board.

[0059] SPI_MOSI is used for master data output on the left side of the board and slave data input on the right side of the board.

[0060] SPI_CS is used for the slave enable signal input on the right side of the board, and is controlled by the master output on the left side of the board.

[0061] SPI_MISO is used for master data input on the left side of the board and slave data output on the right side of the board.

[0062] In one embodiment, the intermediate LVDS interface chip includes two transmit drivers: a host-side transmit driver LVDS31-1 and a slave-side transmit driver LVDS31-2, and two receive drivers: a slave-side receive driver LVDS32-1 and a host-side receive driver LVDS32-2. The LVDS31-1 and LVDS31-2 transmit drivers convert single-ended signals into differential signals, and the LVDS32-1 and LVDS32-2 receive drivers then convert the differential signals back into single-ended signals, enabling long-distance transmission using the differential signals.

[0063] In one embodiment, such as Figure 1As shown, the left-side board-level host transmits SPI_CLK, SPI_MOSI, and SPI_CS signals respectively through the first SPI_CLK sub-interface, the first SPI_MOSI sub-interface, and the first SPI_CS sub-interface. These constitute the first signal, which is converted into SPI_CLK differential signal, SPI_MOSI differential signal, and SPI_CS differential signal by the host-side transmit driver LVDS31-1 through the first input interface TIN1, the second input interface TIN2, and the third input interface TIN3. These three pairs of differential signals are output as the first differential signal group. The SPI_CLK differential signal is output from the first differential signal output interface DOUT1+ and DOUT1-, the SPI_MOSI differential signal is output from the second differential signal output interface DOUT2+ and DOUT2-, and the SPI_CS differential signal is output from the third differential signal output interface DOUT3+ and DOUT3-. These three pairs of differential output signals are received by the first differential signal receiving interface RIN1+ and RIN1-, the second differential signal receiving interface RIN2+ and RIN2-, and the third differential signal receiving interface RIN3+ and RIN3- of the LVDS32-1 receiver driver, respectively, and then converted into SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal. They are then sent to the three signal receiving terminals of the right-side board-level slave device, namely the second SPI_CLK sub-interface, the second SPI_MOSI sub-interface, and the second SPI_CS sub-interface, respectively, through the first output interface DOUT1, the second output interface DOUT2, and the third output interface DOUT3.

[0064] Meanwhile, the single-ended SPI_MISO signal from the right-side board slave is converted into a pair of differential signals, DOUT1+ and DOUT1-, by the LVDS31-2 transmit driver and output through the fourth input interface TIN1. This pair of differential output signals is received by the fourth differential signal receive interfaces RIN1+ and RIN1- of the LVDS32-2 receive driver, converted back into SPI_MISO signals, and then sent to the second SPI_MISO interface of the left-side board host via the fourth output interface DOUT1.

[0065] In one embodiment, the left-side board-level host controls the SPI_CS signal; when SPI_CS is pulled low, communication begins; when SPI_CS is pulled high, communication ends.

[0066] This invention also proposes a high-speed, long-distance board-level chip-to-chip communication method for aerospace distributed systems, comprising:

[0067] The master chip sends a first signal to the slave chip: The master chip sends a first signal to the intermediate LVDS interface chip, which includes a master-side transmit driver LVDS31-1, a slave-side receive driver LVDS32-1, a slave-side transmit driver LVDS31-2, and a master-side receive driver LVDS32-2. The master-side transmit driver receives the first signal, converts it into a first differential signal group, and then sends it to the slave-side receive driver LVDS32-1. The slave-side receive driver LVDS32-1 converts the first differential signal group into a first signal and sends it to the slave chip.

[0068] The slave chip sends a second signal to the master chip: The slave-side sender LVDS31-2 receives the second signal sent by the slave chip, converts it into a second differential signal, and then sends it to the master-side receiver LVDS32-2. The master-side receiver LVDS32-2 converts the second differential signal into a second signal and sends it to the master chip.

[0069] In one embodiment, such as Figure 3 As shown, it is a flowchart of the master-slave transmission process of the present invention. First, the master chip reads its receive buffer and send buffer to determine whether the master chip has instruction data to send to the slave chip. If no instruction data is sent to the slave chip, it will wait for the next communication cycle.

[0070] If the master chip determines that it has instruction data to send to the slave chip, the master chip generates an SPI_CS signal, as well as SPI_CLK and SPI_MOSI signals, and communication begins. The SPI_CS, SPI_CLK, and SPI_MOSI signals are sent to the master-side transmit driver, which converts them into SPI_CS differential signals, SPI_CLK differential signals, and SPI_MOSI differential signals for inter-board transmission. The slave-side receive driver receives the differential signals and converts them back into SPI_CS, SPI_CLK, and SPI_MOSI signals, which are then sent to the slave chip.

[0071] Simultaneously, the slave chip generates an SPI_MISO signal and sends the SPI_MISO signal to the transmit driver. The SPI_MISO signal is converted into a pair of differential signals by the slave-side transmit driver for inter-board transmission, and the pair of differential signals is converted into corresponding single-ended signals by the host-side receive driver and input to the host.

[0072] Within each SPI_CLK clock cycle, data is transmitted between the master and slave chips.

[0073] The host chip reads the host receive buffer and checks if the host chip's receive check bit is correct. If it is incorrect, the last SPI protocol data packet is resent to the host transmit buffer. If the receive check bit is correct, the received data is stored in the host receive buffer, and the transmitted data is stored in the host transmit buffer for transmission. The protocol packet transmission within one communication cycle of the host ends.

[0074] At the start of communication, the slave device reads the slave receive buffer and checks whether the slave's receive check bit is correct. If it is incorrect, the slave sends the data with the send check bit set to zero. If the receive check bit is correct, the received data is stored in the slave receive buffer, and the sent data is stored in the slave send buffer for transmission. The SPI protocol data packet transmission in one communication cycle of the slave device ends, thus the SPI protocol data packet transmission in one communication cycle of the master and slave devices ends.

[0075] In one embodiment, such as Figure 4 As shown, the protocol packet format for full-duplex data transmission between master and slave includes a header, data bits, and a checksum. The header is a fixed number of bytes, the data bits contain information transmitted between the master and slave, and the checksum is the sum of the data bits.

[0076] This invention is based on the SPI communication protocol and combines it with the LVDS hardware design interface. The master and slave devices can be controllers of different types. The left-side board-level FPGA / DSP / ARM acts as the SPI communication master, and its master control chip can be an FPGA, DSP, or ARM chip. The right-side board-level FPGA / DSP / ARM acts as the SPI communication slave, and its master control chip can also be an FPGA, DSP, or ARM chip. Each SPI channel needs to be configured to use the four common interfaces: SPI_CLK, SPI_MOSI, SPI_CS, and SPI_MISO. Communication begins when the left-side board-level master pulls down the SPI_CS chip select signal and generates the corresponding SPI_CLK signal. The master and slave then engage in full-duplex data communication. Communication ends when the left-side board-level master pulls up the SPI_CS chip select signal, and preparations are made for the next round of communication. This invention, by combining the advantages of the SPI protocol and LVDS, enables high-speed communication over long distances between different controllers. It is highly suitable for communication processes in aerospace distributed systems, and the slave interfaces are consistent, allowing for plug-and-play and equivalent replacement.

[0077] The above description, in conjunction with the accompanying drawings, provides a detailed account of one embodiment of the present invention. However, the present invention is not limited to the specific details described above. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solution of the present invention, and all such equivalent transformations fall within the protection scope of the present invention.

Claims

1. A high-speed, long-distance board-level inter-chip communication system for aerospace distributed systems, characterized in that, include: Master chip, slave chip, intermediate LVDS interface chip, The host chip reads the host transmission buffer to determine whether the host chip has any instruction data to send to the slave chip. If no instruction data is sent to the slave chip, it will wait for the next communication cycle. The intermediate LVDS interface chip includes a host-side transmit driver, a slave-side receive driver, a slave-side transmit driver, and a host-side receive driver. If the master chip determines that instruction data is to be sent to the slave chip, then communication is initiated between the master and slave chips. The master chip generates a first signal, and communication begins. The first signal is sent to the master-side transmit driver, and the first signal is converted into a first differential signal by the master-side transmit driver for inter-board transmission. The slave-side receive driver receives the first differential signal and converts it into a first signal, which is then sent to the slave chip. The slave chip generates a second signal and sends the second signal to the slave-side transmit driver. The second signal is converted into a second differential signal by the slave-side transmit driver for inter-board transmission. The master-side receive driver receives the second differential signal and converts it into a second signal before sending it to the master chip. The host chip includes a first interface and a second interface. The host chip sends a first signal to the host side via the first interface. The host-side receiver driver sends the second signal to the second interface of the host chip; The slave chip includes a third interface and a fourth interface. The slave chip receives a first signal from the driver sent by the intermediate LVDS interface chip via the third interface; the slave chip sends a second signal from the driver sent by the driver to the intermediate LVDS interface chip via the fourth interface. The first interface of the host chip includes a first SPI_CLK sub-interface, a first SPI_MOSI sub-interface, and a first SPI_CS sub-interface; the third interface of the slave chip includes a second SPI_CLK sub-interface, a second SPI_MOSI sub-interface, and a second SPI_CS sub-interface. The host-side transmit driver includes a first input interface, a second input interface, a third input interface, a first differential signal output interface, a second differential signal output interface, and a third differential signal output interface; The host-side receiver driver includes a first differential signal receiving interface, a second differential signal receiving interface, a third differential signal receiving interface, a first output interface, a second output interface, and a third output interface; Based on the SPI communication protocol, the first signal includes the SPI_CLK signal, the SPI_MOSI signal, and the SPI_CS signal. The host chip sends the SPI_CLK signal to the first input interface through the first SPI_CLK sub-interface, the SPI_MOSI signal to the second input interface through the first SPI_MOSI sub-interface, and the SPI_CS signal to the third input interface through the first SPI_CS sub-interface. The host-side transmit driver converts the SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal into a first differential signal group, which includes the SPI_CLK differential signal, SPI_MOSI differential signal, and SPI_CS differential signal. These signals are then output through the first differential signal output interface, the second differential signal output interface, and the third differential signal output interface, respectively. The slave-side receive driver uses the first differential signal receiving interface, the second differential signal receiving interface, and the third differential signal receiving interface to receive the SPI_CLK differential signal, the SPI_MOSI differential signal, and the SPI_CS differential signal from the first differential signal output interface, the second differential signal output interface, and the third differential signal output interface, respectively. After converting them into SPI_CLK signals, SPI_MOSI signals, and SPI_CS signals, they are then output through the first output interface, the second output interface, and the third output interface, respectively. The slave chip receives the SPI_CLK signal output from the first output interface via the second SPI_CLK sub-interface, the SPI_MOSI signal output from the second output interface via the second SPI_MOSI sub-interface, and the SPI_CS signal output from the third output interface via the second SPI_CS sub-interface. The fourth interface of the slave chip is the first SPI_MISO interface, and the second interface of the master chip is the second SPI_MISO interface; The slave-side transmitter driver includes a fourth input interface and a fourth differential signal output interface; The host-side receiver driver includes a fourth differential signal receiving interface and a fourth output interface; Based on the SPI communication protocol, the second signal is the SPI_MISO signal, and the slave chip sends the SPI_MISO signal to the fourth input interface through the first SPI_MISO interface; The slave-side driver converts the SPI_MISO signal into an SPI_MISO differential signal, which is then used as the second differential signal and output through the fourth differential signal output interface. The host-side receiver driver uses the fourth differential signal receiver interface to receive the SPI_MISO differential signal from the fourth differential signal output interface, converts it into an SPI_MISO signal, and then outputs it through the fourth output interface. The second SPI_MISO interface of the host chip receives the SPI_MISO signal output from the fourth output interface; The host chip or slave chip is an FPGA, and the GPIO of the FPGA chip is configured as the SPI_CLK interface, SPI_MOSI interface, SPI_CS interface and SPI_MISO interface of the SPI protocol for communication; or, the host chip or slave chip is a DSP or ARM, and the SPI_CLK interface, SPI_MOSI interface, SPI_CS interface and SPI_MISO interface of the SPI hard core of the DSP or ARM chip are used for communication.

2. The system according to claim 1, characterized in that, The communication between the master and slave chips further includes: The host chip reads the host receive buffer and determines whether the host chip's receive check bit is correct. If it is incorrect, the previous data packet is resent to the host send buffer. If the receive check bit is correct, the received data is stored in the host receive buffer, and the sent data is stored in the host send buffer for transmission. The data packet transmission within one communication cycle of the host ends. At the start of communication, the slave device reads the slave receive buffer and checks whether the slave's receive check bit is correct. If it is incorrect, the slave device sets the send check bit to zero and sends the data. If the receive check bit is correct, the received data is stored in the slave receive buffer, and the sent data is stored in the slave send buffer for transmission. The data packet transmission in one communication cycle of the slave device ends, and thus the communication in one communication cycle of the master and slave devices ends.

3. A method for high-speed, long-distance board-level chip-to-chip communication in aerospace distributed systems, characterized in that, include: The process of the master chip sending the first signal to the slave chip is as follows: the master chip sends the first signal to the intermediate LVDS interface chip. The intermediate LVDS interface chip includes a master-side transmit driver, a slave-side receive driver, a slave-side transmit driver, and a master-side receive driver. The master-side transmit driver receives the first signal and converts it into a first differential signal group before sending it to the slave-side receive driver. The slave-side receive driver converts the first differential signal group into the first signal and sends it to the slave chip. The process of the slave chip sending the second signal to the master chip is as follows: the slave-side transmitting driver receives the second signal sent by the slave chip, converts it into a second differential signal, and then sends it to the master-side receiving driver. The master-side receiving driver converts the second differential signal into a second signal and sends it to the master chip. The sending of the first signal from the host chip to the slave chip further includes: Based on the SPI communication protocol, the first signal includes the SPI_CLK signal, the SPI_MOSI signal, and the SPI_CS signal. The host chip sends the SPI_CLK signal, the SPI_MOSI signal, and the SPI_CS signal to the host-side transmit driver. The host-side transmit driver converts the SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal into a first differential signal group before outputting them. The first differential signal group includes the SPI_CLK differential signal, the SPI_MOSI differential signal, and the SPI_CS differential signal. The slave-side receiver driver receives the SPI_CLK differential signal, SPI_MOSI differential signal, and SPI_CS differential signal, converts them into SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal respectively, and then outputs them respectively. The slave chip receives the SPI_CLK signal, SPI_MOSI signal, and SPI_CS signal. Sending a second signal from the slave chip to the master chip further includes: Based on the SPI communication protocol, the second signal is the SPI_MISO signal, and the slave chip sends the SPI_MISO signal to the slave-side transmit driver; The slave-side transmitter converts SPI_MISO into an SPI_MISO differential signal as the second differential signal output. The host-side receiver driver receives the SPI_MISO differential signal, converts it into an SPI_MISO signal, and then outputs it. The host chip receives the SPI_MISO signal; The host chip or slave chip is an FPGA, and the GPIO of the FPGA chip is configured as the SPI_CLK interface, SPI_MOSI interface, SPI_CS interface and SPI_MISO interface of the SPI protocol for communication; or, the host chip or slave chip is a DSP or ARM, and the SPI_CLK interface, SPI_MOSI interface, SPI_CS interface and SPI_MISO interface of the SPI hard core of the DSP or ARM chip are used for communication.

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