A design method for high-reliability inter-chip communication in flight control computers

Abstract

This invention relates to a high-reliability inter-chip communication design method for flight control computers, belonging to the field of communication. The invention designs a redundant EMIF interface between DSP and FPGA chips. The DSP and FPGA chips can identify transmission errors by comparing the data on the redundant interface. Some transmission errors can be corrected using redundant data. When data errors cannot be corrected, an interrupt is used to return the error to the DSP chip at the EMIF interface master. The DSP chip then retransmits the data based on the interrupt message. This invention features data correctness verification, determining whether data transmission is correct after completion; data error correction for partially erroneous data frames through the redundant EMIF interface; and a communication error interrupt mechanism, notifying the DSP chip to retransmit after an error occurs.

Description

Technical Field

[0001] This invention belongs to the field of communications, specifically relating to a design method for highly reliable inter-chip communication in flight control computers. Background Technology

[0002] This domestically produced multi-core DSP processor is a new generation of high-performance 32-bit multi-core floating-point DSP chip for military use. It operates at a clock speed of 500MHz, with a fixed-point performance of 16 GIPS and a floating-point performance of 12 GFLOPS. The chip contains four DSP cores and more than 8MB of on-chip memory. The four DSP cores can communicate via SDP or a crossbar switch. The chip's total power consumption is less than 5W, making it a key processor in a new flight control computer product for a certain field.

[0003] Currently, the flight control computer motherboard (hereinafter referred to as the computer motherboard) based on this domestically produced quad-core DSP has a "DSP+FPGA" high-speed signal processing and control host architecture. The DSP chip is the main processing chip, used for fixed-point and floating-point operations on high-performance complex models; the FPGA chip is the coprocessor chip, used for communication control, logic operations, and other coprocessing functions. The DSP chip and FPGA chip are the two most important processors on the computer motherboard, implementing more than 99% of the computer motherboard's processing functions. There is a large amount of data information exchange between the DSP chip and the FPGA chip, therefore, the reliability of data communication between the two is very important.

[0004] The current communication function block diagram between the DSP chip and FPGA chip on the computer motherboard is as follows: Figure 1 As shown. Each DSP core of this domestically produced quad-core DSP chip has an EMIF interface peripheral. Currently, computer motherboards typically use two DSP cores, each with its own EMIF bus connected to the FPGA chip, such as... Figure 1 As shown.

[0005] The EMIF interface is a master-slave communication interface, with the DSP always acting as the master. When the DSP1 core accesses data stored internally in the FPGA chip through the EMIF1 interface, a signal is emitted from the DSP and transmitted through the inter-chip printed circuit board signal lines to the configurable I / O interface of the FPGA chip. Upon receiving the signal, the configurable I / O interface of the FPGA chip connects to the user-programmed EMIF interface module via internal signal lines. After synchronization, decoding, and other processing, the EMIF interface module generates an on-chip bus signal for the FPGA, which is then connected to the bus interfaces of other functional logic modules.

[0006] The EMIF interface is a simple parallel bus interface, including clock, chip select, write enable, read enable, address, data, and read / write signals. Currently, the communication between DSP chips and FPGA chips widely used on flight control computer motherboards is based on this simple EMIF interface. This communication method has the following drawbacks:

[0007] 1) Without proper data verification, after data transmission is completed, read and write operations cannot determine whether the data and address are correct;

[0008] 2) Because the EMIF interface lacks a redundant data bit transmission mechanism, it cannot correct data errors in erroneous data frames;

[0009] 3) Since the EMIF interface itself does not have error checking, it cannot retransmit after an error occurs. Summary of the Invention

[0010] (a) Technical problems to be solved

[0011] The technical problem to be solved by this invention is to provide a high-reliability inter-chip communication design method for flight control computers, so as to solve the defects of current communication between DSP chips and FPGA chips on the motherboard of flight control computers, which cannot identify transmission errors, cannot correct transmission errors, and cannot realize error retransmission.

[0012] (II) Technical Solution

[0013] To address the aforementioned technical problems, this invention proposes a high-reliability inter-chip communication design method for flight control computers. This method includes: designing four redundant EMIF interfaces between the DSP chip and the FPGA chip: EMIF1, EMIF2, EMIF3, and EMIF4. The DSP chip includes four cores: DSP core 1, DSP core 2, DSP core 3, and DSP core 4. EMIF1 is connected to the EMIF peripheral of DSP core 1, EMIF2 is connected to the EMIF peripheral of DSP core 2, EMIF3 is connected to the EMIF peripheral of DSP core 3, and EMIF4 is connected to the EMIF peripheral of DSP core 4.

[0014] The EMIF interface function of the FPGA is implemented through two high-reliability inter-chip interface modules designed in the FPGA software. Each high-reliability inter-chip interface module includes three EMIF interface modules and an EMIF data processing and verification / correction module. Each communication between the DSP chip and the FPGA chip is redundantly completed by the three EMIF interface modules. The FPGA designs three EMIF interface modules for each of DSP core 1 and DSP core 2. The three EMIF interface modules in each high-reliability inter-chip interface module work in parallel and independently, and independently complete the three EMIF interface communication processing from the DSP chip for one communication. The EMIF data processing and verification / correction module connects the three EMIF interface modules and the data buffer in the FPGA.

[0015] When DSP core 1 needs to access the FPGA chip, DSP core 1 accesses the FPGA chip through three interfaces: EMIF1, EMIF3, and EMIF4.

[0016] When DSP core 2 needs to access the FPGA chip, DSP core 2 accesses the FPGA chip through three interfaces: EMIF2, EMIF3, and EMIF4.

[0017] DSP core 3 and DSP core 4 are communication coprocessing units that process EMIF access requests from DSP core 1 or DSP core 2 and complete information interaction with the FPGA chip.

[0018] Furthermore, DSP core 1 accesses the FPGA chip through the three interfaces EMIF1, EMIF3, and EMIF4, specifically including: DSP core 1 directly accessing the FPGA chip using the EMIF1 interface; DSP core 1 communicating with DSP core 3 through the inter-core communication function, thereby accessing the FPGA chip through the EMIF peripheral EMIF3 of DSP core 3; and DSP core 1 communicating with DSP core 4 through the inter-core communication function, thereby accessing the FPGA chip through the EMIF peripheral EMIF4 of DSP core 4.

[0019] Furthermore, DSP core 2 accesses the FPGA chip through the three interfaces EMIF2, EMIF3, and EMIF4, specifically including: DSP core 2 directly accessing the FPGA chip using the EMIF2 interface; DSP core 2 communicating with DSP core 3 through the inter-core communication function, thereby accessing the FPGA chip through the EMIF peripheral EMIF3 of DSP core 3; and DSP core 2 communicating with DSP core 4 through the inter-core communication function, thereby accessing the FPGA chip through the EMIF peripheral EMIF4 of DSP core 4.

[0020] Furthermore, the inter-core communication function is implemented through the shared memory pool SDP to control related units and shared memory.

[0021] Furthermore, for the EMIF interface write data request of DSP core 1 or DSP core 2, DSP core 1 or DSP core 2 sends all the data to be written, write data flag, write data start address and write data length information to DSP core 3 and DSP core 4 through the inter-core communication function. After receiving the data, DSP core 3 and DSP core 4 determine that it is an EMIF write operation by the flag, and then write the data to the FPGA chip through their respective EMIF interfaces.

[0022] Furthermore, for the EMIF interface read data request of DSP core 1 or DSP core 2, DSP core 1 or DSP core 2 sends the read data flag, read data start address and read data length information to DSP core 3 and DSP core 4 through the inter-core communication function. After receiving the information, DSP core 3 and DSP core 4 determine that it is an EMIF read operation by the flag, read the data from the FPGA chip through their respective EMIF interfaces, and send the read data back to DSP core 1 or DSP core 2 through the inter-core communication function.

[0023] Furthermore, when DSP core 3 and DSP core 4 are preparing to operate the EMIF interface, they send an inter-core interrupt to DSP core 1 or DSP core 2 that requires information exchange. At the same time, DSP core 1 or DSP core 2 prepares to operate the EMIF, ensuring that the three EMIF interfaces communicate synchronously.

[0024] Furthermore, for EMIF read operations, each EMIF interface module obtains the read access address of the EMIF interface from the EMIF communication; the EMIF data processing and verification module compares the three read access addresses. If the three addresses are the same, the address and read flag are written to the data buffer; the on-chip bus controller determines that the access command is a read based on the read flag in the data buffer, reads the relevant register data according to the address, and returns it to the data buffer; the EMIF data processing and verification module reads the returned register value and sends it to the three EMIF interface modules simultaneously; the three EMIF interface modules feed back the register value to the EMIF data line according to the access timing of their respective buses; the DSP-side EMIF interface completes the EMIF access; if the EMIF data processing and verification module finds that the data is inconsistent when comparing the three read access addresses: if two addresses are the same, the consistent address and read flag are written to the data buffer, and the subsequent operation is the same as when the three addresses are the same; if the three addresses are all different, the EMIF interface processing ends, and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed.

[0025] Furthermore, for EMIF write operations, each EMIF interface module obtains the write access address and write data of the EMIF interface from the EMIF communication; the DSP-side EMIF interface completes the EMIF access; the EMIF data processing and verification module compares the three write access addresses. If the three addresses are the same, it compares the three write access data. If both the address and data are the same, it writes the write flag, write address, and write data into the data buffer; the on-chip bus controller determines that the access command is a write based on the write flag in the data buffer and writes the data to the relevant register according to the address; if the three addresses are the same and the two write access data are the same, the write flag, write address, and the same write data are written into the data buffer, and the subsequent operation is the same as if all are the same; if the three addresses are the same and the three write access data are different, the interface operation is stopped and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed; if any one of the three addresses is different, the interface operation is stopped and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed.

[0026] Furthermore, when DSP core 1 or DSP core 2 receives a communication error interruption, it retransmits the previously transmitted data until the data transmission is successful.

[0027] (III) Beneficial Effects

[0028] This invention proposes a high-reliability inter-chip communication design method for flight control computers. By designing a redundant EMIF interface between DSP and FPGA chips, the DSP and FPGA chips can identify transmission errors by comparing the data on the redundant interface. Some transmission errors can be corrected using redundant data. When data errors cannot be corrected, the error can be returned to the DSP chip at the master end of the EMIF interface via an interrupt. The DSP chip then retransmits the data according to the interrupt message.

[0029] This invention designs a highly reliable communication method between a computer motherboard DSP chip and an FPGA chip. The method has the following advantages: (1) It has data correctness verification. After the data transmission is completed, it can be determined whether the data transmission is correct; (2) Through the redundant EMIF interface, it can correct data errors in some data frames that have errors; (3) It has a communication error interruption mechanism. After an error occurs, it notifies the DSP chip to retransmit through an interrupt. Attached Figure Description

[0030] Figure 1 A block diagram of the existing communication architecture between DSP chips and FPGA chips on a computer motherboard.

[0031] Figure 2 This is a block diagram of the communication architecture between the DSP chip and FPGA chip on the computer motherboard of the present invention. Detailed Implementation

[0032] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0033] This invention patent designs a highly reliable inter-chip communication method. This design method can solve the defects of current communication between DSP chips and FPGA chips on flight control computer motherboards, such as the inability to identify transmission errors, the inability to correct transmission errors, and the inability to retransmit errors.

[0034] The functional block diagram of the present invention is as follows: Figure 2 As shown.

[0035] To address the shortcomings of existing communication methods between DSP chips and FPGA chips on computer motherboards, this invention adds two redundant EMIF interfaces, EMIF3 and EMIF4, between the DSP chip and the FPGA chip. EMIF3 is connected to the EMIF peripheral of DSP core 3, and EMIF4 is connected to the EMIF peripheral of DSP core 4.

[0036] like Figure 2 As shown, four redundant EMIF interfaces are designed between the DSP chip and the FPGA chip: EMIF1, EMIF2, EMIF3 and EMIF4. The DSP chip includes four cores: DSP core 1, DSP core 2, DSP core 3 and DSP core 4. EMIF1 is connected to the EMIF peripheral of DSP core 1, EMIF2 is connected to the EMIF peripheral of DSP core 2, EMIF3 is connected to the EMIF peripheral of DSP core 3 and EMIF4 is connected to the EMIF peripheral of DSP core 4.

[0037] The EMIF interface function of the FPGA is implemented through two high-reliability inter-chip interface modules designed in the FPGA software. Each high-reliability inter-chip interface module includes three EMIF interface modules and an EMIF data processing, verification, and correction module. Each communication between the DSP chip and the FPGA chip is redundantly completed by the three EMIF interface modules. The FPGA is designed with three EMIF interface modules for DSP core 1 and DSP core 2 respectively. Figure 2 As shown. Each high-reliability inter-chip interface module has three EMIF interface modules that operate independently in parallel, each independently handling three EMIF interface communication processes from a single communication with the DSP chip. The EMIF data processing, verification, and correction module connects the three EMIF interface modules to the data buffer in the FPGA.

[0038] When DSP core 1 needs to access the FPGA chip, it accesses the FPGA chip through three interfaces: EMIF1, EMIF3, and EMIF4. The specific communication methods are as follows: DSP core 1 directly accesses the FPGA chip using the EMIF1 interface; DSP core 1 communicates with DSP core 3 through inter-core communication functions (implemented by SDP control related units, shared memory S1, and shared memory S5), thereby accessing the FPGA chip through DSP core 3's EMIF peripheral EMIF3; DSP core 1 communicates with DSP core 4 through inter-core communication functions (implemented by SDP control related units, shared memory S2, and shared memory S7), thereby accessing the FPGA chip through DSP core 4's EMIF peripheral EMIF4.

[0039] SDP is a description in the DSP chip manual. SDP (shared data pool) is a shared memory pool used for fast, fine-grained data exchange between DSP cores.

[0040] SDP control-related units include: SDP indicator lights, buffers, and controllers.

[0041] SDP shared memory includes: S1 to S8 shared memory.

[0042] When DSP core 2 needs to access the FPGA chip, it accesses the FPGA chip through three interfaces: EMIF2, EMIF3, and EMIF4. The specific communication methods are as follows: DSP core 2 directly accesses the FPGA chip using the EMIF2 interface; DSP core 2 communicates with DSP core 3 through inter-core communication functions (implemented by SDP control-related units, shared memory S3, and shared memory S6), thereby accessing the FPGA chip through DSP core 3's EMIF peripheral EMIF3; DSP core 2 communicates with DSP core 4 through inter-core communication functions (implemented by SDP control-related units, shared memory S4, and shared memory S8), thereby accessing the FPGA chip through DSP core 4's EMIF peripheral EMIF4.

[0043] DSP core 3 and DSP core 4 are communication coprocessing units. They handle EMIF access requests from DSP core 1 or DSP core 2 and complete information interaction with the FPGA chip.

[0044] For the EMIF interface write data request of DSP core 1 or DSP core 2, DSP core 1 or DSP core 2 sends all the data to be written, write data flag, write data start address, and write data length information to DSP core 3 and DSP core 4 through the inter-core communication function. After receiving the data, DSP core 3 and DSP core 4 determine that it is an EMIF write operation by the flag, and then write the data to the FPGA chip through their respective EMIF interfaces.

[0045] For data read requests from the EMIF interface of DSP core 1 or DSP core 2, DSP core 1 or DSP core 2 sends the read data flag, read data start address, and read data length information to DSP core 3 and DSP core 4 via inter-core communication. Upon receiving this information, DSP core 3 and DSP core 4 determine that it is an EMIF read operation based on the flag, and then read the data from the FPGA chip through their respective EMIF interfaces. The read data is then sent back to DSP core 1 or DSP core 2 via inter-core communication. The inter-core communication function uses the SDP inter-core transmission method.

[0046] When DSP core 3 and DSP core 4 are preparing to operate the EMIF interface, they send an inter-core interrupt to the core (DSP core 1 or DSP core 2) that requires information exchange. At the same time, DSP core 1 or DSP core 2 prepares to operate the EMIF, ensuring that the three EMIF interfaces communicate synchronously.

[0047] For EMIF read operations, each EMIF interface module obtains the read access address of the EMIF interface from the EMIF communication. The EMIF data processing and verification module compares the three read access addresses. If the three addresses are the same, the address and read flag are written to the data buffer. The on-chip bus controller determines that the access command is a read based on the read flag in the data buffer, reads the relevant register data according to the address, and returns it to the data buffer. The EMIF data processing and verification module reads the returned register value and sends it to the three EMIF interface modules. The three EMIF interface modules feed back the register value to the EMIF data line according to the access timing of their respective buses. The DSP-side EMIF interface completes the EMIF access. If the EMIF data processing and verification module finds that the data is inconsistent when comparing the three read access addresses: if two addresses are the same, the consistent address and read flag are written to the data buffer, and the subsequent operation is the same as if all three addresses are the same; if all three addresses are different, the EMIF interface processing ends, and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed.

[0048] For EMIF write operations, each EMIF interface module obtains the write access address and write data of the EMIF interface from EMIF communication; the DSP-side EMIF interface completes the EMIF access; the EMIF data processing and verification module compares the three write access addresses. If the three addresses are the same, it compares the three write access data. If both the address and data are the same, the write flag, write address, and write data are written to the data buffer; the on-chip bus controller determines that the access command is a write based on the write flag in the data buffer and writes the data to the relevant registers according to the address. If the three addresses are the same and two write access data are the same, the write flag, write address, and the same write data are written to the data buffer, and the subsequent operation is the same as if all are the same. If the three addresses are the same and the three write access data are different, the interface operation is stopped and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed. If any one of the three addresses is different, the interface operation is stopped and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed.

[0049] When DSP core 1 or DSP core 2 receives a communication error interruption, it retransmits the previously transmitted data until the data transmission is successful.

[0050] This invention designs a redundant EMIF interface between DSP and FPGA chips. The DSP chip and FPGA chip can identify transmission errors by comparing whether the data on the redundant interface is consistent. Some transmission errors can be corrected by the redundant data. When the data error cannot be corrected, the error can be returned to the DSP chip at the master end of the EMIF interface through an interrupt. The DSP chip then retransmits the data according to the interrupt prompt.

[0051] This invention designs a highly reliable communication method between a computer motherboard DSP chip and an FPGA chip. The method has the following advantages: (1) It has data correctness verification. After the data transmission is completed, it can be determined whether the data transmission is correct; (2) Through the redundant EMIF interface, it can correct data errors in some data frames that have errors; (3) It has a communication error interruption mechanism. After an error occurs, it notifies the DSP chip to retransmit through an interrupt.

[0052] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-reliability inter-chip communication design method for flight control computers, characterized in that, The method includes: designing four redundant EMIF interfaces between the DSP chip and the FPGA chip: EMIF1, EMIF2, EMIF3 and EMIF4. The DSP chip includes four cores: DSP core 1, DSP core 2, DSP core 3 and DSP core 4. EMIF1 is connected to the EMIF peripheral of DSP core 1, EMIF2 is connected to the EMIF peripheral of DSP core 2, EMIF3 is connected to the EMIF peripheral of DSP core 3 and EMIF4 is connected to the EMIF peripheral of DSP core 4. The EMIF interface function of the FPGA is implemented through two high-reliability inter-chip interface modules designed in the FPGA software. Each high-reliability inter-chip interface module includes three EMIF interface modules and an EMIF data processing and verification / correction module. Each communication between the DSP chip and the FPGA chip is redundantly completed by the three EMIF interface modules. The FPGA designs three EMIF interface modules for each of DSP core 1 and DSP core 2. The three EMIF interface modules in each high-reliability inter-chip interface module work in parallel and independently, and independently complete the three EMIF interface communication processing from the DSP chip for one communication. The EMIF data processing and verification / correction module connects the three EMIF interface modules and the data buffer in the FPGA. When DSP core 1 needs to access the FPGA chip, DSP core 1 accesses the FPGA chip through three interfaces: EMIF1, EMIF3, and EMIF4. When DSP core 2 needs to access the FPGA chip, DSP core 2 accesses the FPGA chip through three interfaces: EMIF2, EMIF3, and EMIF4. DSP core 3 and DSP core 4 are communication coprocessing units that process EMIF access requests from DSP core 1 or DSP core 2 and complete information interaction with the FPGA chip. in, DSP core 1 accesses the FPGA chip through three interfaces: EMIF1, EMIF3, and EMIF4. Specifically, DSP core 1 directly accesses the FPGA chip using the EMIF1 interface; DSP core 1 communicates with DSP core 3 through inter-core communication, thereby accessing the FPGA chip through the EMIF peripheral EMIF3 of DSP core 3; and DSP core 1 communicates with DSP core 4 through inter-core communication, thereby accessing the FPGA chip through the EMIF peripheral EMIF4 of DSP core 4. DSP core 2 accesses the FPGA chip through three interfaces: EMIF2, EMIF3, and EMIF4. Specifically, DSP core 2 directly accesses the FPGA chip using the EMIF2 interface; DSP core 2 communicates with DSP core 3 through inter-core communication, thereby accessing the FPGA chip through the EMIF peripheral EMIF3 of DSP core 3; and DSP core 2 communicates with DSP core 4 through inter-core communication, thereby accessing the FPGA chip through the EMIF peripheral EMIF4 of DSP core 4. For EMIF read operations, each EMIF interface module obtains the read access address of the EMIF interface from the EMIF communication; the EMIF data processing and verification module compares the three read access addresses. If the three addresses are the same, the address and read flag are written to the data buffer; the on-chip bus controller determines that the access command is a read based on the read flag in the data buffer, reads the relevant register data according to the address, and returns it to the data buffer; the EMIF data processing and verification module reads the returned register value and sends it to the three EMIF interface modules simultaneously; the three EMIF interface modules feed back the register value to the EMIF data line according to the access timing of their respective buses; the DSP-side EMIF interface completes the EMIF access; if the EMIF data processing and verification module finds that the data is inconsistent when comparing the three read access addresses: if two addresses are the same, the consistent address and read flag are written to the data buffer, and the subsequent operation is the same as if all three addresses are the same; if all three addresses are different, the EMIF interface processing ends, and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed; For EMIF write operations, each EMIF interface module obtains the write access address and write data of the EMIF interface from the EMIF communication; the DSP-side EMIF interface completes the EMIF access; the EMIF data processing and verification module compares the three write access addresses. If the three addresses are the same, it compares the three write access data. If both the address and data are the same, the write flag, write address, and write data are written to the data buffer; the on-chip bus controller determines that the access command is a write based on the write flag in the data buffer and writes the data to the relevant register according to the address; if the three addresses are the same and the two write access data are the same, the write flag, write address, and the same write data are written to the data buffer, and the subsequent operation is the same as if all are the same; if the three addresses are the same and the three write access data are different, the interface operation is stopped and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed; if any one of the three addresses is different, the interface operation is stopped and an interrupt is sent to the corresponding DSP core to notify that the EMIF interface access has failed.

2. The high-reliability inter-chip communication design method for flight control computers as described in claim 1, characterized in that, Inter-core communication is achieved through the shared memory pool SDP, which controls related units and shared memory.

3. The high-reliability inter-chip communication design method for flight control computers as described in claim 1, characterized in that, For the EMIF interface write data request of DSP core 1 or DSP core 2, DSP core 1 or DSP core 2 sends all the data to be written, write data flag, write data start address and write data length information to DSP core 3 and DSP core 4 through the inter-core communication function. After receiving the data, DSP core 3 and DSP core 4 determine that it is an EMIF write operation by the flag, and then write the data to the FPGA chip through their respective EMIF interfaces.

4. The high-reliability inter-chip communication design method for flight control computers as described in claim 1, characterized in that, For the EMIF interface read data request of DSP core 1 or DSP core 2, DSP core 1 or DSP core 2 sends the read data flag, read data start address and read data length information to DSP core 3 and DSP core 4 through the inter-core communication function. After receiving the information, DSP core 3 and DSP core 4 determine that it is an EMIF read operation by the flag, read the data from the FPGA chip through their respective EMIF interfaces, and send the read data back to DSP core 1 or DSP core 2 through the inter-core communication function.

5. The high-reliability inter-chip communication design method for flight control computers as described in claim 3 or 4, characterized in that, When DSP core 3 and DSP core 4 are preparing to operate the EMIF interface, they send an inter-core interrupt to DSP core 1 or DSP core 2 that requires information exchange. At the same time, DSP core 1 or DSP core 2 prepares to operate the EMIF, ensuring that the three EMIF interfaces communicate synchronously.

6. The high-reliability inter-chip communication design method for flight control computers as described in claim 5, characterized in that, When DSP core 1 or DSP core 2 receives a communication error interruption, it retransmits the previously transmitted data until the data transmission is successful.

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