Display panel and display device

Abstract

The application relates to the technical field of display, and discloses a display panel and a display device, the display panel comprises a first display mode, the first display mode displays a first picture; the display panel further comprises a second display mode, the second display mode displays a second picture, the second display mode comprises a first display stage and a second display stage, when the first display stage, the refresh frequency of the display panel is F1, when the second display stage, the refresh frequency of the display panel is F2, F1>F2; the display panel is switched from the first display mode to the second display stage through the first display stage. The application improves the technical problem that the display image picture is abnormal in the prior art.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Electronic products use different refresh rates for display in different application scenarios. For example, in video or game mode, a higher refresh rate can be used to drive the display of dynamic images to ensure smoothness. Conversely, when displaying slow-motion or still images, a lower refresh rate can be used to reduce power consumption.

[0003] However, the existing display panels have display abnormality issues. Summary of the Invention

[0004] In view of this, the present invention provides a display panel and a display device to improve the technical problem of abnormal image display in the prior art.

[0005] The present invention provides a display panel, the display panel including a first display mode, the first display mode displaying a first image; the display panel also includes a second display mode, the second display mode displaying a second image, the second display mode including a first display stage and a second display stage, in the first display stage the refresh rate of the display panel is F1, in the second display stage the refresh rate of the display panel is F2, F1>F2; the display panel switches from the first display mode to the second display stage via the first display stage.

[0006] This invention provides a display panel, comprising a pixel circuit and a light-emitting element electrically connected thereto. The pixel circuit includes a driving transistor, a data writing module, and a bias compensation module. A first terminal of the data writing module is connected to a data voltage terminal, and a second terminal of the data writing module is electrically connected to the first electrode of the driving transistor. A first terminal of the bias compensation module is connected to a bias compensation voltage terminal, and a second terminal of the bias compensation module is electrically connected to the first electrode of the driving transistor. During one frame of the display panel, the operation of the pixel circuit includes a reset phase and a data writing phase. During the data writing phase, the data writing module is turned on, and the data voltage terminal writes a data voltage signal to the first electrode of the driving transistor. During the reset phase, the bias compensation module is turned on, and the bias compensation voltage terminal writes a bias compensation voltage signal to the first electrode of the driving transistor. The operation of the pixel circuit during a portion of one frame of the display panel is described below. It also includes a second bias stage, in which the bias compensation module is turned on and the bias compensation voltage terminal writes a bias compensation voltage signal to the first terminal of the driving transistor; the display panel includes a first display mode, in which a first image is displayed, and the refresh rate of the display panel is F3 in the first display mode; the display panel also includes a second display mode, in which a second image is displayed, and the refresh rate of the display panel is F4, where F3 > F4; when the display panel switches from the first display mode to the second display mode, a reset stage is set before the data writing stage in the first display mode; a reset stage is set before the data writing stage during the first frame display time of the second display mode; a reset stage is set before the data writing stage during the second frame display time of the second display mode; and a second bias stage is provided between the data writing stage and the holding stage.

[0007] Based on the same idea, the present invention also provides a display device, including the display panel provided by the present invention.

[0008] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0009] The display panel includes a first display mode and a second display mode. In the first display mode, the display panel displays a first image, and in the second display mode, it displays a second image. The second display mode includes a first display stage and a second display stage. In the first display stage, the refresh rate of the display panel is F1, and in the second display stage, the refresh rate is F2, where F1 > F2. That is, the refresh rate of the display panel is lower in the second display stage. When the display panel switches from the first display mode to the second display stage, a first display stage is inserted between the first display mode and the second display stage. In the first display mode, when the refresh rate of the display panel is higher, the first display stage acts as a transition, preventing the display panel from directly switching from a high-frequency refresh rate to a low-frequency refresh rate, effectively improving screen flicker and enhancing the visual experience. When the refresh rate of the display panel is low in the first display mode, the first display stage is inserted between the first display mode and the second display stage. In the first display stage, the refresh rate of the display panel is high. The first display stage can play a transition role, avoiding the display panel from directly switching between high and low level images at a low refresh rate, effectively improving the screen ghosting phenomenon and enhancing the visual experience.

[0010] Of course, any product implementing this invention need not necessarily achieve all of the technical effects described above at the same time.

[0011] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0013] Figure 1 This is a schematic diagram of a driving method for a display panel provided by the present invention;

[0014] Figure 2 This is a partial cross-sectional view of a display panel provided by the present invention;

[0015] Figure 3 This is a circuit diagram of a pixel circuit provided by the present invention;

[0016] Figure 4 This is a driving timing diagram of the pixel circuit provided by the present invention;

[0017] Figure 5This is another driving timing diagram of the pixel circuit provided by the present invention;

[0018] Figure 6 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0019] Figure 7 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0020] Figure 8 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0021] Figure 9 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0022] Figure 10 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0023] Figure 11 This is a circuit diagram of another pixel circuit provided by the present invention;

[0024] Figure 12 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0025] Figure 13 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0026] Figure 14 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0027] Figure 15 This is yet another driving timing diagram for the pixel circuit provided by the present invention;

[0028] Figure 16 This is a plan view of a display device provided by the present invention. Detailed Implementation

[0029] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0030] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0031] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0032] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0033] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0034] Based on the background information described in this application, during the invention process, the inventors discovered that when a display panel using organic self-emissive technology switches directly from a high refresh rate to a low refresh rate, there is a problem of abnormal brightness in the first frame at the low refresh rate, meaning screen flicker occurs, affecting the visual experience. Specifically: when the display panel switches from a high-frequency data refresh rate driving mode to a low-frequency data refresh rate driving mode, because the display panel is driven by the high-frequency data refresh rate driving mode, the number of frames held within a data refresh cycle is zero or very small, and the gate of the driving transistor maintains the input of the data signal. That is, the gate potential of the driving transistor refreshes relatively frequently, thus the driving transistor is mainly biased based on the data voltage signal. When the display panel is driven by the low-frequency data refresh rate driving mode, the number of frames held within a data refresh cycle becomes relatively larger, and the gate potential of the driving transistor remains unchanged for a long time within a data refresh cycle, thus the driving transistor is mainly biased based on the bias compensation voltage signal. Therefore, when the display panel switches from a high-frequency data refresh rate driving mode to a low-frequency data refresh rate driving mode, an abnormal brightness problem will occur, that is, screen flickering will occur, affecting the visual experience.

[0035] In the process of inventing this invention, the inventors also discovered that display panels using organic self-emissive technology exhibit abnormal brightness in the first or first few frames of the switched image when directly switching between high and low grayscale images at a low refresh rate. This results in screen ghosting, affecting the visual experience. Specifically, at a low refresh rate, the gate potential of the driving transistor remains constant for an extended period, causing a shift in the transistor's characteristics. Consequently, when switching between high and low grayscale images at a low refresh rate, this change in transistor characteristics leads to abnormal brightness, resulting in screen ghosting and impacting the visual experience. Specifically, when switching from a low grayscale image to a high grayscale image, the first or first few frames of the high grayscale image will appear too bright; conversely, when switching from a high grayscale image to a low grayscale image, the first or first few frames of the low grayscale image will appear too bright.

[0036] Based on the above research, this application provides a display panel and a display device that effectively improve the display effect. The display panel with the above-mentioned technical effects provided by this application is described in detail below:

[0037] Figure 1 This is a schematic diagram of a driving method for a display panel provided by the present invention, for reference. Figure 1 This embodiment provides a display panel, which includes a first display mode T1, in which a first screen is displayed.

[0038] The display panel also includes a second display mode T2, which displays a second screen. The second display mode T2 includes a first display stage T21 and a second display stage T22. In the first display stage T21, the refresh rate of the display panel is F1, and in the second display stage T22, the refresh rate of the display panel is F2, where F1 > F2.

[0039] The display panel switches from the first display mode T1 to the second display stage T22 via the first display stage T21.

[0040] Specifically, the display panel includes a first display mode T1 and a second display mode T2. In the first display mode T1, the display panel displays a first image; in the second display mode T2, the display panel displays a second image. The second display mode T2 includes a first display stage T21 and a second display stage T22. In the first display stage T21, the refresh rate of the display panel is F1; in the second display stage T22, the refresh rate of the display panel is F2, where F1 > F2. That is, the refresh rate of the display panel is lower in the second display stage T22. When the display panel switches from the first display mode T1 to the second display stage T22, the first display stage T21 is inserted between the first display mode T1 and the second display stage T22; that is, the display panel switches from the first display mode T1 to the second display stage T22 via the first display stage T21.

[0041] When the refresh rate of the display panel is high in the first display mode T1, the first display stage T21 is inserted between the first display mode T1 and the second display stage T22. In the first display stage T21, the refresh rate of the display panel is high. The first display stage T21 can play a transition role, avoiding the display panel from switching directly from a high frequency data refresh rate to a low frequency data refresh rate, effectively improving screen flicker and enhancing the visual experience.

[0042] When the refresh rate of the display panel is low in the first display mode T1, the first display stage T21 is inserted between the first display mode T1 and the second display stage T22. In the first display stage T21, the refresh rate of the display panel is high. The first display stage T21 can play a transition role, avoiding the display panel from directly switching between high and low level images at a low refresh rate, effectively improving the screen ghosting phenomenon and enhancing the visual experience.

[0043] It should be noted that this embodiment exemplarily illustrates the insertion of the first display stage T21 between the first display mode T1 and the second display stage T22. In other embodiments of the present invention, more display stages may be inserted between the first display mode T1 and the second display stage T22. The refresh rate of the display panel between the first display mode T1 and the second display stage T22 is greater than the refresh rate of the display panel when the second display stage T22 is in progress, and gradually decreases. The present invention will not elaborate on these further.

[0044] Figure 2 This is a partial cross-sectional view of a display panel provided by the present invention. Figure 3 This is a circuit diagram of a pixel circuit provided by the present invention. Figure 4 This is a driving timing diagram of the pixel circuit provided by the present invention, for reference. Figures 2-4 In some alternative embodiments, the display panel includes a pixel circuit 10 and a light-emitting element 20 electrically connected thereto. The pixel circuit 10 includes a driving transistor M1 and a data writing module 11. The driving transistor M1 provides a driving current to the light-emitting element 20. The first end of the data writing module 11 is connected to the data voltage terminal Vdata, and the second end of the data writing module 11 is electrically connected to the first electrode of the driving transistor M1.

[0045] During the display time of one frame of the display panel, the working process of the pixel circuit includes a data writing stage t1 and a holding stage t2. The holding stage t2 includes a first biasing stage t21.

[0046] During the data writing stage t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first terminal of the driving transistor M1.

[0047] During the first bias stage t21, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1.

[0048] Specifically, the display panel includes a substrate 30, an array layer 40 and a display layer 50 located on one side of the substrate 30. The array layer 40 includes multiple pixel circuits 10, and the display layer 50 includes multiple light-emitting elements 20. Specifically, the light-emitting elements 20 may include organic light-emitting diodes (OLEDs) or inorganic light-emitting diodes (LEDs). Each light-emitting element 20 includes a first electrode, a light-emitting layer, and a second electrode stacked together. In one embodiment, the first electrode is an anode, and the second electrode is a cathode. Of course, in other embodiments of the present invention, the display panel may also include other structures. For example, an encapsulation layer may be provided on the side of the display layer 50 away from the substrate 30 to encapsulate and protect the light-emitting elements 20. Alternatively, when the display panel also has a touch function, the display panel may also include a touch layer. The display panel of this embodiment includes, but is not limited to, the above structures. The structure of the display panel is not specifically limited here; however, it can be understood by referring to the structures of display panels in related technologies.

[0049] The pixel circuit 10 is electrically connected to the light-emitting element 20, and the pixel circuit 10 is used to drive the light-emitting element 20 to emit light. Specifically, the pixel circuit 10 provides a driving current to the light-emitting element 20, and the light-emitting element 20 displays a certain brightness according to the magnitude of the driving current.

[0050] The pixel circuit 10 includes a driving transistor M1 and a data writing module 11. The driving transistor M1 provides driving current to the light-emitting element 20. The first terminal of the data writing module 11 is connected to the data voltage terminal Vdata, and the second terminal of the data writing module 11 is electrically connected to the first terminal of the driving transistor M1. Specifically, during one frame of display on the display panel, the operation of the pixel circuit includes a data writing stage t1 and a holding stage t2. The holding stage t2 includes a first biasing stage t21.

[0051] During the data writing stage t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first terminal of the driving transistor M1. Subsequently, the driving transistor M1 can form a driving current based on the data voltage signal V1.

[0052] In the first bias stage t21, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1, which can bias the driving transistor M1 with a high voltage, thereby avoiding the characteristic deviation of the driving transistor M1 caused by the driving transistor M1 not performing data writing for a long time in the holding stage t2, so that the electrical properties of the driving transistor M1 are restored and the driving effect of the driving module 31 is improved.

[0053] It should be noted that, Figure 4The example shown is a PMOS type driving transistor M1. In other embodiments of the present invention, the driving transistor M1 may also be an NMOS type driving transistor. The present invention will not elaborate on these embodiments here.

[0054] Optional, continue to refer to Figure 4 and Figure 5 The pixel circuit also includes a first light emission control module 12, a second light emission control module 13, a threshold compensation module 14, a first reset module 15, and a second reset module 16.

[0055] The first light-emitting control module 12 is electrically connected to the control terminal of the light-emitting control signal terminal Emit, the first terminal of the first light-emitting control module 12 is electrically connected to the first power signal terminal PVDD, and the second terminal of the first light-emitting control module 12 is electrically connected to the first electrode of the driving transistor M1. The first light-emitting control module 12 is used to provide the first power signal PVDD to the first electrode of the driving transistor M1.

[0056] The control terminal of the second light-emitting control module 13 is electrically connected to the light-emitting control signal terminal Emit. The first terminal of the second light-emitting control module 13 is electrically connected to the second electrode of the driving transistor M1. The second terminal of the second light-emitting control module 13 is electrically connected to the anode of the light-emitting element 20. The second light-emitting control module 13 is used to control the transmission of the driving current generated by the driving transistor M1 to the light-emitting element 20.

[0057] The threshold compensation module 14 is used to compensate the threshold voltage of the driving transistor M1, the first reset module 15 is used to provide a first reset signal to the gate of the driving transistor M1, and the second reset module 16 is used to provide a second reset signal to the anode of the light-emitting element 20.

[0058] The control terminal of the data writing module 11 is electrically connected to the first scan signal terminal SP. The control terminal of the threshold compensation module 14 is electrically connected to the second scan signal terminal S2. The first terminal of the threshold compensation module 14 is electrically connected to the second electrode of the driving transistor M1, and the second terminal of the threshold compensation module 14 is electrically connected to the gate of the driving transistor M1. The cathode of the light-emitting element 20 is electrically connected to the second power supply signal terminal PVEE. The control terminal of the first reset module 15 is electrically connected to the third scan signal terminal S1. The first terminal of the first reset module 15 is electrically connected to the reset signal terminal Vref, and the second terminal of the first reset module 15 is electrically connected to the gate of the driving transistor M1. The control terminal of the second reset module 16 is electrically connected to the first scan signal terminal SP. The first terminal of the second reset module 16 is electrically connected to the reset signal terminal Vref, and the second terminal of the second reset module 16 is electrically connected to the anode of the light-emitting element 20.

[0059] It should be noted that the embodiments of the present invention do not specifically limit the structure of the reset module, data writing module, threshold compensation module, and light emission control module. Provided that the bias compensation function of the driving transistor threshold voltage can be achieved, each module of the pixel circuit can be designed according to actual needs. For ease of understanding, the specific structures of the reset module, data writing module, threshold compensation module, and light emission control module in the embodiments of the present invention are exemplified below, wherein each module may optionally include a thin-film transistor. (Continue to refer to...) Figure 4 , Figure 4 The example shown illustrates a 7T1C pixel circuit structure in a display panel. Of course, in other embodiments of the present invention, the pixel circuit can have other circuit structures, which will not be elaborated upon here.

[0060] Figure 5 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figures 1-3 and Figure 5 In some alternative embodiments, during the second display stage T22, during the data writing stage t1, the voltage value of the data voltage signal is V11;

[0061] During the first frame display time of the second display phase T22, in the first bias phase t21, the voltage value of the bias compensation voltage signal is V21.

[0062] During the second frame display time of the second display phase T22, in the first bias phase t21, the voltage value of the bias compensation voltage signal is V22.

[0063] V21 is between V11 and V22.

[0064] Specifically, the second display mode T2 includes a first display stage T21 and a second display stage T22. In the first display stage T21, the refresh rate of the display panel is F1, and in the second display stage T22, the refresh rate of the display panel is F2, where F1 > F2. That is, the refresh rate of the display panel is lower in the second display stage T22. When the display panel switches from the first display mode T1 to the second display stage T22, the first display stage T21 is inserted between the first display mode T1 and the second display stage T22; that is, the display panel switches from the first display mode T1 to the second display stage T22 via the first display stage T21.

[0065] During the second display stage T22, the refresh rate of the display panel is lower than that during the first display stage T21. As a result, the duration of holding frame t2 within one frame of the second display stage T22 is longer than that within one frame of the first display stage T21. Consequently, there are more first bias stages t21 within one frame of the second display stage T22. This results in a difference in the bias effect on the driving transistor M1 between the first display stage T21 and the second display stage T22. Consequently, when the display panel switches from the first display stage T21 to the second display stage T22, an abnormal brightness problem occurs, which means screen flickering occurs, affecting the visual experience.

[0066] In the second display stage T22, during the data writing stage t1, the voltage value of the data voltage signal is V11. During the second frame display time of the second display stage T22, during the first bias stage t21, the voltage value of the bias compensation voltage signal is V22. During the first frame display time of the second display stage T22, during the first bias stage t21, the voltage value of the bias compensation voltage signal is V21. V21 is between V11 and V22. Therefore, the bias effect on the driving transistor M1 during the first frame display time of the second display stage T22 is between the bias effect on the driving transistor M1 during the first display stage T21 and the bias effect on the driving transistor M1 during the second frame display time of the second display stage T22. That is, the first frame display of the second display stage T22 plays a transitional role, effectively alleviating the problem of abnormal brightness that occurs when the display panel switches from the first display stage T21 to the second display stage T22, thus effectively alleviating screen flicker and improving the visual experience.

[0067] Similarly, when the refresh rate of the display panel is high in the first display mode T1, and the refresh rate of the display panel in the first display mode T1 is greater than the refresh rate of the display panel in the first display stage T21, a similar transition design can be made in the first frame display of the first display stage T21. That is, during the first frame display time of the first display stage T21, the voltage value of the bias compensation voltage signal in the first bias stage t21 is between the voltage value of the data voltage signal in the first display mode T1 and the voltage value of the bias compensation voltage signal in the first bias stage t21 during the second frame display time of the first display stage T21. This invention will not be elaborated further here.

[0068] Similarly, the voltage value of the bias compensation voltage signal during the second frame display time of the second display stage T22, during the first bias stage t21, can be set to be between the voltage value of the bias compensation voltage signal during the first frame display time of the second display stage T22, during the first bias stage t21, and during the third frame display time of the second display stage T22, during the first bias stage t21. That is, the voltage value of the bias compensation voltage signal during the first bias stage t21 can be gradually changed during which frame display time of the second display stage T22. This will not be elaborated further in this invention.

[0069] Figure 6 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figures 1-3 and Figure 6 In some alternative embodiments, during the first display mode T1, in the data writing stage t1, the voltage value of the data voltage signal is V12.

[0070] In the second display mode T2, during the data writing stage t1, the voltage value of the data voltage signal is V13;

[0071] During the first frame display time of the first display phase T21, in the first bias phase t21, the voltage value of the bias compensation voltage signal t21 is V31.

[0072] During the second frame display time of the first display phase T22, in the first bias phase t21, the voltage value of the bias compensation voltage signal t21 is V32.

[0073] Among them, V12 > V13, and V31 > V32.

[0074] Specifically, in the first display mode T1, during the data writing stage t1, the voltage value of the data voltage signal is V12. In the second display mode T2, during the data writing stage t1, the voltage value of the data voltage signal is V13. V12 > V13. That is, in the first display mode T1, the display panel displays a high grayscale image, and in the second display mode T2, the display panel displays a low grayscale image.

[0075] In existing technology, when the display panel switches from a high grayscale image to a low grayscale image, the brightness may be too high in the first frame or the first few frames of the low grayscale image.

[0076] In this application, during the first frame display time of the first display phase T21, the voltage value of the bias compensation voltage signal t21 is V31 during the first bias phase t21. During the second frame display time of the first display phase T22, the voltage value of the bias compensation voltage signal t21 is V32 during the first bias phase t21, where V31 > V32. That is, during the first frame display time of the first display phase T21, the voltage value of the bias compensation voltage signal t21 is higher during the first bias phase t21, thereby reducing the brightness of the first frame display on the display panel during the first display phase T21, effectively improving the display trailing phenomenon and enhancing the visual experience.

[0077] Similarly, Figure 7 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figures 1-3 and Figure 7 V12 < V13, and V31 < V32.

[0078] In the first display mode T1, during the data writing stage t1, the voltage value of the data voltage signal is V12. In the second display mode T2, during the data writing stage t1, the voltage value of the data voltage signal is V13. V12 < V13. That is, in the first display mode T1, the display panel displays a low grayscale image, and in the second display mode T2, the display panel displays a high grayscale image.

[0079] In existing technology, when the display panel switches from a low grayscale image to a high grayscale image, the brightness may be low in the first frame or the first few frames of the low grayscale image.

[0080] In this application, during the first frame display time of the first display phase T21, the voltage value of the bias compensation voltage signal t21 is V31 during the first bias phase t21. During the second frame display time of the first display phase T22, the voltage value of the bias compensation voltage signal t21 is V32 during the first bias phase t21, where V31 < V32. That is, during the first frame display time of the first display phase T21, the voltage value of the bias compensation voltage signal t21 is lower during the first bias phase t21, thereby increasing the brightness of the first frame display on the display panel during the first display phase T21, effectively improving the display trailing phenomenon and enhancing the visual experience.

[0081] Figure 8 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figures 1-3 and Figure 8 In some alternative embodiments, during the first display mode T1, in the data writing stage t1, the voltage value of the data voltage signal is V12.

[0082] In the second display mode T2, during the data writing stage t1, the voltage value of the data voltage signal is V13;

[0083] During the first frame display time of the first display phase T21, the duration of the first offset phase t21 is h1;

[0084] During the second frame display time of the first display phase T21, the duration of the first offset phase t21 is h2;

[0085] Where V12 > V13, and h1 > h2,

[0086] Specifically, in the first display mode T1, during the data writing stage t1, the voltage value of the data voltage signal is V12. In the second display mode T2, during the data writing stage t1, the voltage value of the data voltage signal is V13. V12 > V13. That is, in the first display mode T1, the display panel displays a high grayscale image, and in the second display mode T2, the display panel displays a low grayscale image.

[0087] In existing technology, when the display panel switches from a high grayscale image to a low grayscale image, the brightness may be too high in the first frame or the first few frames of the low grayscale image.

[0088] In this application, during the first frame display time of the first display phase T21, the duration of the first offset phase t21 is h1, and during the second frame display time of the first display phase T21, the duration of the first offset phase t21 is h2, where h1 > h2. That is, by increasing the duration of the first offset phase t21 during the first frame display time of the first display phase T21, the brightness of the first frame displayed on the display panel during the first display phase T21 can be reduced, effectively improving the display trailing phenomenon and enhancing the visual experience.

[0089] Similarly, Figure 9 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figures 1-3 and Figure 9 V12 < V13, and h1 < h2.

[0090] In the first display mode T1, during the data writing stage t1, the voltage value of the data voltage signal is V12. In the second display mode T2, during the data writing stage t1, the voltage value of the data voltage signal is V13. V12 < V13. That is, in the first display mode T1, the display panel displays a low grayscale image, and in the second display mode T2, the display panel displays a high grayscale image.

[0091] In existing technology, when the display panel switches from a low grayscale image to a high grayscale image, the brightness may be low in the first frame or the first few frames of the low grayscale image.

[0092] In this application, during the first frame display time of the first display phase T21, the duration of the first offset phase t21 is h1, and during the second frame display time of the first display phase T21, the duration of the first offset phase t21 is h2, where h1 < h2. That is, by reducing the duration of the first offset phase t21 during the first frame display time of the first display phase T21, the brightness of the first frame displayed on the display panel during the first display phase T21 can be increased, effectively improving the display trailing phenomenon and enhancing the visual experience.

[0093] Figure 10 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figures 1-3 and Figure 10 In some optional embodiments, during the display frame time of the display panel, the operation of the pixel circuit 10 also includes a reset phase t3. During the reset phase t3, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first pole of the driving transistor M1.

[0094] During the first frame display time of the first display phase T21, the reset phase t3 is set before the data writing phase t1.

[0095] Specifically, during the first frame display time of the first display stage T21, a reset stage t3 is set before the data writing stage t1, which can reset the driving transistor M1 once, thereby reducing the influence of the first screen in the first display mode T1 on the second screen in the first display stage T21, and helping to improve the display trailing phenomenon when switching from the first display mode T1 to the first display stage T21.

[0096] Figure 11 This is a circuit diagram of another pixel circuit provided by the present invention. Figure 12 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figure 2 , Figure 11 and Figure 12 In some optional embodiments, the display panel includes a pixel circuit 10 and a light-emitting element 20 electrically connected thereto. The pixel circuit 10 includes a driving transistor M1, a data writing module 11 and a bias compensation module 17. The first end of the data writing module 11 is connected to the data voltage terminal Vdata, and the second end of the data writing module 11 is electrically connected to the first electrode of the driving transistor M1. The first end of the bias compensation module 17 is connected to the bias compensation voltage terminal DVH, and the second end of the bias compensation module 17 is electrically connected to the first electrode of the driving transistor M1.

[0097] During the display time of one frame of the display panel, the working process of the pixel circuit 10 includes a data writing stage t1 and a holding stage t2. The holding stage t2 includes a first bias stage t21.

[0098] During the data writing stage t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first terminal of the driving transistor M1.

[0099] During the first bias stage t21, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1.

[0100] Specifically, the display panel includes a pixel circuit 10 and a light-emitting element 20 electrically connected thereto. The pixel circuit 10 is used to drive the light-emitting element 20 to emit light. Specifically, the pixel circuit 10 provides a driving current to the light-emitting element 20, and the light-emitting element 20 displays a certain brightness according to the magnitude of the driving current.

[0101] The pixel circuit 10 includes a driving transistor M1, a data writing module 11, and a bias compensation module 17. The first terminal of the data writing module 11 is connected to the data voltage terminal Vdata, and the second terminal of the data writing module 11 is electrically connected to the first electrode of the driving transistor M1. The first terminal of the bias compensation module 17 is connected to the bias compensation voltage terminal DVH, and the second terminal of the bias compensation module 17 is electrically connected to the first electrode of the driving transistor M1. Specifically, during one frame of display on the display panel, the operation of the pixel circuit 10 includes a data writing phase t1 and a holding phase t2. The holding phase t2 includes a first bias phase t21.

[0102] During the data writing stage t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first terminal of the driving transistor M1. Subsequently, the driving transistor M1 can form a driving current based on the data voltage signal V1.

[0103] In the first bias stage t21, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1, which can bias the driving transistor M1 with a high voltage, thereby avoiding the characteristic deviation of the driving transistor M1 caused by the driving transistor M1 not writing data for a long time in the holding stage t2, so that the electrical properties of the driving transistor M1 are restored and the driving effect of the driving module 31 is improved.

[0104] Simultaneously, during the data writing phase t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first electrode of the driving transistor M1. During the first bias phase t21, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first electrode of the driving transistor M1. Therefore, regardless of whether the display panel uses a high-frequency or low-frequency data refresh rate driving method, the bias compensation voltage signal V2 is written to the first electrode of the driving transistor M1 based on the bias compensation voltage terminal DVH. This effectively improves the screen flicker phenomenon when the display panel switches from a high-frequency to a low-frequency data refresh rate, enhancing the visual experience.

[0105] It should be noted that, Figure 11 The example shown is a PMOS type driving transistor M1. In other embodiments of the present invention, the driving transistor M1 may also be an NMOS type driving transistor. The present invention will not elaborate on these embodiments here.

[0106] Optional, continue to refer to Figure 11 and Figure 12 The pixel circuit also includes a first light emission control module 12, a second light emission control module 13, a threshold compensation module 14, a first reset module 15, and a second reset module 16.

[0107] The first light-emitting control module 12 is electrically connected to the control terminal of the light-emitting control signal terminal Emit, the first terminal of the first light-emitting control module 12 is electrically connected to the first power signal terminal PVDD, and the second terminal of the first light-emitting control module 12 is electrically connected to the first electrode of the driving transistor M1. The first light-emitting control module 12 is used to provide the first power signal PVDD to the first electrode of the driving transistor M1.

[0108] The control terminal of the second light-emitting control module 13 is electrically connected to the light-emitting control signal terminal Emit. The first terminal of the second light-emitting control module 13 is electrically connected to the second electrode of the driving transistor M1. The second terminal of the second light-emitting control module 13 is electrically connected to the anode of the light-emitting element 20. The second light-emitting control module 13 is used to control the transmission of the driving current generated by the driving transistor M1 to the light-emitting element 20.

[0109] The threshold compensation module 14 is used to compensate the threshold voltage of the driving transistor M1, the first reset module 15 is used to provide a first reset signal to the gate of the driving transistor M1, and the second reset module 16 is used to provide a second reset signal to the anode of the light-emitting element 20.

[0110] The control terminal of the data writing module 11 is electrically connected to the first scan signal terminal SP. The control terminal of the threshold compensation module 14 is electrically connected to the second scan signal terminal S2. The first terminal of the threshold compensation module 14 is electrically connected to the second electrode of the driving transistor M1, and the second terminal of the threshold compensation module 14 is electrically connected to the gate of the driving transistor M1. The cathode of the light-emitting element 20 is electrically connected to the second power supply signal terminal PVEE. The control terminal of the first reset module 15 is electrically connected to the third scan signal terminal S1. The first terminal of the first reset module 15 is electrically connected to the reset signal terminal Vref, and the second terminal of the first reset module 15 is electrically connected to the gate of the driving transistor M1. The control terminal of the second reset module 16 is electrically connected to the first scan signal terminal SP. The first terminal of the second reset module 16 is electrically connected to the reset signal terminal Vref, and the second terminal of the second reset module 16 is electrically connected to the anode of the light-emitting element 20.

[0111] It should be noted that the embodiments of the present invention do not specifically limit the structure of the reset module, data writing module, threshold compensation module, and light emission control module. Provided that the bias compensation function of the driving transistor threshold voltage can be achieved, each module of the pixel circuit can be designed according to actual needs. For ease of understanding, the specific structures of the reset module, data writing module, threshold compensation module, and light emission control module in the embodiments of the present invention are exemplified below, wherein each module may optionally include a thin-film transistor. (Continue to refer to...) Figure 11 , Figure 11 The example shown illustrates a pixel circuit structure of an 8T1C in a display panel. Of course, in other embodiments of the present invention, the pixel circuit may have other circuit structures, which will not be elaborated upon here.

[0112] Figure 13 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figure 1 , Figure 2 , Figure 11 and Figure 13 In some optional embodiments, during the display panel's one-frame display time, the pixel circuit's operation process also includes a reset phase t3. During the reset phase t3, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1.

[0113] In the first display mode T1, the refresh rate of the display panel is F3, where F3 < F2;

[0114] During the first display stage T21, a reset stage t3 is set before the data writing stage t1;

[0115] During the display of a frame of the display panel, the operation of the pixel circuit 10 also includes a second bias stage t4. During the second bias stage t4, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1.

[0116] In the second display stage T22, a reset stage t3 is set before the data writing stage, and a second bias stage t4 is set between the data writing stage t1 and the holding stage t2.

[0117] Specifically, during the display frame time of the display panel, the working process of the pixel circuit also includes a reset phase t3. During the reset phase t3, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1, which can reset the driving transistor M1 once and reduce the trailing phenomenon when the display panel screen switches.

[0118] In the first display mode T1, the refresh rate of the display panel is F3; in the first display stage T21, the refresh rate of the display panel is F1; and in the second display stage T22, the refresh rate of the display panel is F2, where F3 < F2 and F1 > F2. That is, in the first display mode T1 and the second display stage T22, the refresh rate of the display panel is lower, while in the first display stage T21, the refresh rate of the display panel is higher.

[0119] In existing technologies, when a display panel uses a high-frequency data refresh rate driving method, the number of frames held within a data refresh cycle is zero or very small, and the gate of the driving transistor maintains the input of the data signal. In other words, the gate potential of the driving transistor refreshes relatively frequently. When a display panel uses a low-frequency data refresh rate driving method, the number of frames held within a data refresh cycle becomes relatively larger, and the gate potential of the driving transistor remains unchanged for a long time within a data refresh cycle. However, during the light-emitting phase of the pixel circuit in the display panel, the driving transistor may operate in a non-saturated state. For PMOS driving transistors, there may be a situation where the gate potential is higher than the drain potential when the driving transistor is turned on; for NMOS driving transistors, there may be a situation where the gate potential is lower than the drain potential when the driving transistor is turned on. Maintaining this situation for a long time will lead to ion polarization inside the driving transistor, thereby forming a built-in electric field inside the driving transistor, causing the threshold voltage of the driving transistor to continuously shift. When a display panel uses a low-frequency data refresh rate driving method, abnormal brightness may occur, which means screen flickering will occur and affect the visual experience.

[0120] In this application, since the refresh rate of the display panel is high during the first display stage T21, the pixel circuit can operate without the second bias stage t4 during the display panel's one-frame display time during the first display stage T21. Since the refresh rate of the display panel is low in the second display mode T1 and the second display stage T22, a second bias stage t4 is provided between the data writing stage t1 and the holding stage t2 within one frame display time of the display panel in the first display mode T1 and the second display stage T22. In the second bias stage t4, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1, which can bias the driving transistor M1 with a high voltage, thereby avoiding the characteristic deviation of the driving transistor M1 caused by the driving transistor M1 not performing data writing for a long time in the first display mode T1 and the second display stage T22. This allows the electrical properties of the driving transistor M1 to recover, improves the driving effect of the driving module 31, effectively reduces the screen flicker phenomenon of the display panel in the first display mode T1 and the second display stage T22, and effectively improves the visual experience.

[0121] Figure 14 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figure 2 , Figure 11 and Figure 14 This embodiment provides a display panel, which includes a pixel circuit 10 and a light-emitting element 20 electrically connected thereto. The pixel circuit 10 includes a driving transistor M1, a data writing module 11 and a bias compensation module 17. The first end of the data writing module 11 is connected to the data voltage terminal Vdata, and the second end of the data writing module 11 is electrically connected to the first electrode of the driving transistor M1. The first end of the bias compensation module 17 is connected to the bias compensation voltage terminal DVH, and the second end of the bias compensation module 17 is electrically connected to the first electrode of the driving transistor M1.

[0122] During the display time of one frame of the display panel, the working process of the pixel circuit 10 includes a reset phase t3 and a data writing phase t1.

[0123] During the data writing stage t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first terminal of the driving transistor M1.

[0124] During the reset phase t3, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1.

[0125] During the display of a frame of the display panel, the operation of the pixel circuit 10 also includes a second bias stage t4. During the second bias stage t4, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first pole of the driving transistor M1.

[0126] The display panel includes a first display mode T1, in which a first image is displayed. In the first display mode T1, the refresh rate of the display panel is F3.

[0127] The display panel also includes a second display mode T2, in which a second screen is displayed. In the second display mode T2, the refresh rate of the display panel is F4, where F3 > F4.

[0128] When the display panel switches from the first display mode T1 to the second display mode T2, a reset stage t3 is set before the data writing stage t1 in the first display mode T1.

[0129] During the first frame display time of the second display mode T2, a reset phase t3 is set before the data writing phase t1.

[0130] During the second frame display time of the second display mode T2, a reset stage t3 is set before the data writing stage t1, and a second bias stage t4 is set between the data writing stage t1 and the holding stage t2.

[0131] Specifically, the display panel includes a pixel circuit 10 and a light-emitting element 20 electrically connected thereto. The pixel circuit 10 is used to drive the light-emitting element 20 to emit light. Specifically, the pixel circuit 10 provides a driving current to the light-emitting element 20, and the light-emitting element 20 displays a certain brightness according to the magnitude of the driving current.

[0132] The pixel circuit 10 includes a driving transistor M1, a data writing module 11, and a bias compensation module 17. The first terminal of the data writing module 11 is connected to the data voltage terminal Vdata, and the second terminal of the data writing module 11 is electrically connected to the first electrode of the driving transistor M1. The first terminal of the bias compensation module 17 is connected to the bias compensation voltage terminal DVH, and the second terminal of the bias compensation module 17 is electrically connected to the first electrode of the driving transistor M1. Specifically, during one frame of display on the display panel, the operation of the pixel circuit 10 includes a data writing phase t1 and a holding phase t2. The holding phase t2 includes a first bias phase t21.

[0133] During the data writing stage t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first terminal of the driving transistor M1. Subsequently, the driving transistor M1 can form a driving current based on the data voltage signal V1.

[0134] In the first bias stage t21, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1, which can bias the driving transistor M1 with a high voltage, thereby avoiding the characteristic deviation of the driving transistor M1 caused by the driving transistor M1 not writing data for a long time in the holding stage t2, so that the electrical properties of the driving transistor M1 are restored and the driving effect of the driving module 31 is improved.

[0135] Simultaneously, during the data writing phase t1, the data writing module 11 is turned on, and the data voltage terminal Vdata writes the data voltage signal V1 to the first electrode of the driving transistor M1. During the first bias phase t21, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first electrode of the driving transistor M1. Therefore, regardless of whether the display panel uses a high-frequency or low-frequency data refresh rate driving method, the bias compensation voltage signal V2 is written to the first electrode of the driving transistor M1 based on the bias compensation voltage terminal DVH. This effectively improves the screen flicker phenomenon when the display panel switches from a high-frequency to a low-frequency data refresh rate, enhancing the visual experience.

[0136] It should be noted that, Figure 11 The example shown is a PMOS type driving transistor M1. In other embodiments of the present invention, the driving transistor M1 may also be an NMOS type driving transistor. The present invention will not elaborate on these embodiments here.

[0137] During the display frame time of the display panel, the pixel circuit operation also includes a reset phase t3. In the reset phase t3, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1, which can reset the driving transistor M1 once and reduce the trailing phenomenon when the display panel screen switches. In the first display mode T1 and the second display mode T2, a reset phase t3 is set before the data writing phase t1, which can reset the driving transistor M1 once and reduce the trailing phenomenon when the display panel screen switches.

[0138] The display panel includes a first display mode T1, which displays a first image. In the first display mode T1, the refresh rate of the display panel is F3. The display panel also includes a second display mode T2, which displays a second image. In the second display mode T2, the refresh rate of the display panel is F4, where F3 > F4. That is, in the first display mode T1, the refresh rate of the display panel is higher, and in the second display mode T2, the refresh rate of the display panel is lower.

[0139] Since the refresh rate of the display panel is higher in the first display mode T1, there is no need to set the second bias stage t4. Furthermore, the setting of the second bias stage t4 and the setting of the reset stage t3 have a canceling effect; that is, the setting of the second bias stage t4 will affect the reset effect of the drive transistor M1 by the reset stage t3. Therefore, in the first display mode T1, not setting the second bias stage t4 helps the reset stage t3 eliminate the influence of the previous displayed image, reducing the trailing phenomenon during display panel image switching.

[0140] When the display panel switches from the first display mode T1 to the second display mode T2, that is, when the display panel switches from a high-frequency data refresh rate to a low-frequency data refresh rate, a reset stage t3 is set before the data writing stage t1 during the first frame display time of the second display mode T2. This resets the driving transistor M1 once, which can reduce the trailing phenomenon when the display panel screen switches. Furthermore, no second bias stage t4 is set between the data writing stage t1 and the holding stage t2, which helps the reset stage t3 eliminate the influence of the previous display screen. In other words, the influence of the second display mode T2 display screen is effectively eliminated during the first frame display of the second display mode T2, further reducing the trailing phenomenon when the display panel screen switches.

[0141] During the second frame display time of the second display mode T2, a reset stage t3 is set before the data writing stage t1, and a second bias stage t4 is set between the data writing stage t1 and the holding stage t2. In the second bias stage t4, the bias compensation module 17 is turned on, and the bias compensation voltage terminal DVH writes the bias compensation voltage signal V2 to the first terminal of the driving transistor M1, which can bias the driving transistor M1 with a high voltage. This avoids the characteristic deviation of the driving transistor M1 caused by the driving transistor M1 not performing data writing for a long time in the second display mode T2, so that the electrical characteristics of the driving transistor M1 are restored, the driving effect of the driving module 31 is improved, and the screen flicker phenomenon of the display panel in the second display mode T1 is effectively reduced, thus improving the visual experience. At the same time, since the display screen is the same in the second display mode T2, there is no trailing phenomenon in the second frame display screen and subsequent frames in the second display mode T2. Therefore, the second bias stage t4 can be set during the second frame display time of the second display mode T2.

[0142] It should be noted that this embodiment only exemplifies that during the second frame display time of the second display mode T2, a reset stage t3 is set before the data writing stage t1, and a second bias stage t4 is provided between the data writing stage t1 and the holding stage t2. In other embodiments of the present invention, during the third frame and subsequent frames display time of the second display mode T2, the timing settings of the second frame display time of the second display mode T2 in this embodiment can be referred to. The present invention will not elaborate on them one by one here.

[0143] Figure 15 This is another driving timing diagram of the pixel circuit provided by the present invention, see reference. Figure 2 , Figure 11 and Figure 15 In some optional embodiments, during the first frame display time of the second display stage T2, the voltage value of the bias compensation voltage signal is V41;

[0144] During the second frame display time of the second display phase T2, the voltage value of the bias compensation voltage signal is V42;

[0145] V42 > V41.

[0146] Specifically, when the display panel switches from the first display mode T1 to the second display mode T2, that is, when the display panel switches from a high-frequency data refresh rate to a low-frequency data refresh rate, a reset stage t3 is set before the data writing stage t1 during the first frame display time of the second display mode T2. This resets the driving transistor M1 once, reducing the trailing phenomenon during display panel frame switching. The setting of the first bias stage t21 affects the reset stage t3's elimination of the influence on the previous display frame, thereby reducing the bias compensation voltage signal value during the first frame display of the second display mode T2. This effectively eliminates the influence of the display screen of the first display mode T1 on the display screen of the second display mode T2, reducing the trailing phenomenon during display panel frame switching.

[0147] During the second frame display time of the second display mode T2, the second bias stage t4 between the data writing stage t1 and the holding stage t2 can bias the driving transistor M1 with a high voltage. This avoids the characteristic shift of the driving transistor M1 caused by prolonged data inactivity during the second display mode T2, allowing the electrical properties of the driving transistor M1 to recover, improving the driving effect of the driving module 31, and effectively reducing screen flickering on the display panel during the second display mode T2, thus improving the visual experience. Increasing the voltage value of the bias compensation voltage signal during the second frame display time of the second display mode T2 can improve the biasing effect of the driving transistor M1 during the first bias stage t21 and the second bias stage t4, further improving screen flickering on the display panel during the second display mode T2, and effectively improving the visual experience.

[0148] It should be noted that this embodiment only exemplifies that the voltage value of the bias compensation voltage signal is greater than the voltage value of the bias compensation voltage signal during the second frame display time of the second display mode T2. In other embodiments of the present invention, the voltage value of the bias compensation voltage signal during the third and subsequent frames display time of the second display mode T2 can be the same as the voltage value of the bias compensation voltage signal during the second frame display time of the second display mode T2. The voltage value of the bias compensation voltage signal during the third and subsequent frames display time of the second display mode T2 can also be set according to the actual required bias effect. The present invention will not elaborate on these points here.

[0149] In some alternative embodiments, please refer to Figure 16 , Figure 16 This is a plan view of a display device provided by the present invention. The display device 1000 provided in this embodiment includes the display panel 100 provided in the above embodiment of the present invention. Figure 16 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device 1000 provided in this embodiment can also be other display devices 1000 with display functions, such as computers, televisions, and in-vehicle display devices. This invention does not impose specific limitations on these. The display device 1000 provided in this embodiment has the beneficial effects of the display panel 100 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these will not be repeated here.

[0150] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0151] The display panel includes a first display mode and a second display mode. In the first display mode, the display panel displays a first image, and in the second display mode, it displays a second image. The second display mode includes a first display stage and a second display stage. In the first display stage, the refresh rate of the display panel is F1, and in the second display stage, the refresh rate is F2, where F1 > F2. That is, the refresh rate of the display panel is lower in the second display stage. When the display panel switches from the first display mode to the second display stage, a first display stage is inserted between the first display mode and the second display stage. In the first display mode, when the refresh rate of the display panel is higher, the first display stage acts as a transition, preventing the display panel from directly switching from a high-frequency refresh rate to a low-frequency refresh rate, effectively improving screen flicker and enhancing the visual experience. When the refresh rate of the display panel is low in the first display mode, the first display stage is inserted between the first display mode and the second display stage. In the first display stage, the refresh rate of the display panel is high. The first display stage can play a transition role, avoiding the display panel from directly switching between high and low level images at a low refresh rate, effectively improving the screen ghosting phenomenon and enhancing the visual experience.

[0152] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a first display mode, wherein the first display mode displays a first image; The display panel further includes a second display mode, which displays a second image. The second display mode includes a first display stage and a second display stage. In the first display stage, the refresh rate of the display panel is F1, and in the second display stage, the refresh rate of the display panel is F2, where F1 > F2. The display panel switches from the first display mode to the second display stage via the first display stage; The display panel includes a pixel circuit and a light-emitting element electrically connected thereto. The pixel circuit includes a driving transistor and a data writing module. The driving transistor provides a driving current to the light-emitting element. The first terminal of the data writing module is connected to a data voltage terminal, and the second terminal of the data writing module is electrically connected to the first terminal of the driving transistor. During the display time of one frame of the display panel, the operation of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes a first bias stage. During the data writing phase, the data writing module is turned on, and the data voltage terminal writes a data voltage signal to the first terminal of the driving transistor. During the first bias stage, the data writing module is turned on, and the data voltage terminal writes a bias compensation voltage signal to the first terminal of the driving transistor. In the first display mode, during the data writing phase, the voltage value of the data voltage signal is V12; In the second display mode, during the data writing phase, the voltage value of the data voltage signal is V13; During the first frame display time of the first display phase, during the first bias phase, the voltage value of the bias compensation voltage signal is V31; During the second frame display time of the first display phase, during the first bias phase, the voltage value of the bias compensation voltage signal is V32; Where V12 > V13 and V31 > V32, or V12 < V13 and V31 < V32.

2. The display panel according to claim 1, characterized in that, During the second display phase, during the data writing phase, the voltage value of the data voltage signal is V11; During the first frame display time of the second display phase, during the first bias phase, the voltage value of the bias compensation voltage signal is V21; During the second frame display time of the second display phase, during the first bias phase, the voltage value of the bias compensation voltage signal is V22; V21 is between V11 and V22.

3. The display panel according to claim 1, characterized in that, During the first frame display time of the first display phase, the duration of the first offset phase is h1; During the second frame display time of the first display phase, the duration of the first offset phase is h2; Wherein, when V12 > V13, h1 > h2, or when V12 < V13, h1 < h2.

4. The display panel according to claim 1, characterized in that, During the display time of one frame of the display panel, the operation of the pixel circuit also includes a reset phase. During the reset phase, the data writing module is turned on, and the data voltage terminal writes the bias compensation voltage signal to the first pole of the driving transistor. During the first frame display time of the first display phase, the reset phase is set before the data writing phase.

5. A display panel, characterized in that, The display panel includes a first display mode, wherein the first display mode displays a first image; The display panel further includes a second display mode, which displays a second image. The second display mode includes a first display stage and a second display stage. In the first display stage, the refresh rate of the display panel is F1, and in the second display stage, the refresh rate of the display panel is F2, where F1 > F2. The display panel switches from the first display mode to the second display stage via the first display stage; The display panel includes a pixel circuit and a light-emitting element electrically connected thereto. The pixel circuit includes a driving transistor, a data writing module, and a bias compensation module. The first end of the data writing module is connected to a data voltage terminal, and the second end of the data writing module is electrically connected to the first electrode of the driving transistor. The first end of the bias compensation module is connected to a bias compensation voltage terminal, and the second end of the bias compensation module is electrically connected to the first electrode of the driving transistor. During the display time of one frame of the display panel, the operation of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes a first bias stage. During the data writing phase, the data writing module is turned on, and the data voltage terminal writes a data voltage signal to the first terminal of the driving transistor. During the first bias stage, the bias compensation module is turned on, and the bias compensation voltage terminal writes a bias compensation voltage signal to the first terminal of the driving transistor. During the display time of one frame of the display panel, the operation of the pixel circuit also includes a reset phase. During the reset phase, the bias compensation module is turned on, and the bias compensation voltage terminal writes the bias compensation voltage signal to the first pole of the driving transistor. In the first display mode, the refresh rate of the display panel is F3, where F3 < F2; During the first display phase, the reset phase is set before the data writing phase; During a portion of the display panel's one-frame display time, the operation of the pixel circuit further includes a second bias stage. In the second bias stage, the bias compensation module is turned on, and the bias compensation voltage terminal writes the bias compensation voltage signal to the first pole of the driving transistor. In the second display stage, a reset stage is provided before the data writing stage, and a second bias stage is provided between the data writing stage and the holding stage.

6. A display panel, characterized in that, The display panel includes a pixel circuit and a light-emitting element electrically connected thereto. The pixel circuit includes a driving transistor, a data writing module, and a bias compensation module. The first end of the data writing module is connected to a data voltage terminal, and the second end of the data writing module is electrically connected to the first electrode of the driving transistor. The first end of the bias compensation module is connected to a bias compensation voltage terminal, and the second end of the bias compensation module is electrically connected to the first electrode of the driving transistor. During the display time of one frame of the display panel, the operation of the pixel circuit includes a reset phase and a data writing phase. During the data writing phase, the data writing module is turned on, and the data voltage terminal writes a data voltage signal to the first terminal of the driving transistor. During the reset phase, the bias compensation module is turned on, and the bias compensation voltage terminal writes a bias compensation voltage signal to the first terminal of the driving transistor. During a portion of the display panel's one-frame display time, the operation of the pixel circuit further includes a second bias stage. In the second bias stage, the bias compensation module is turned on, and the bias compensation voltage terminal writes the bias compensation voltage signal to the first pole of the driving transistor. The display panel includes a first display mode, in which a first image is displayed, and in the first display mode, the refresh rate of the display panel is F3; The display panel also includes a second display mode, which displays a second screen. In the second display mode, the refresh rate of the display panel is F4, where F3 > F4. When the display panel switches from the first display mode to the second display mode, a reset stage is provided before the data writing stage in the first display mode; During the first frame display time of the second display mode, a reset phase is set before the data writing phase; During the second frame display time of the second display mode, a reset phase is provided before the data writing phase, and a second bias phase is provided between the data writing phase and the holding phase.

7. The display panel according to claim 6, characterized in that, During the first frame display time of the second display mode, the voltage value of the bias compensation voltage signal is V41; During the second frame display time of the second display mode, the voltage value of the bias compensation voltage signal is V42; V42 > V41.

8. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-7.

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