memory elements

Abstract

The present application provides a memory element, which includes a memory structure, a controller chip, and a processor chip. The memory structure includes a first memory chip and a stack of a plurality of second memory chips, wherein each of the second memory chips has a higher memory density than the first memory chip. The controller chip is electrically connected to the first memory chip and the second memory chips. The processor chip is electrically connected to the controller chip.

Description

Technical Field

[0001] This disclosure relates to a memory structure. Background Technology

[0002] In recent years, the structure of semiconductor devices has been constantly changing, and their storage capacity has been continuously increasing. Memory devices are used as storage elements in many products. With the increase in these applications, the demand for memory devices is focusing on small size and large storage capacity. To meet this requirement, memory devices with high component density and small size are needed. Summary of the Invention

[0003] According to some embodiments of this disclosure, a memory element includes a memory structure, a controller chip, and a processor chip. The memory structure includes a first memory chip and a stack of multiple second memory chips, wherein each of the second memory chips has a higher memory density than the first memory chip. The controller chip is electrically connected to the first and second memory chips. The processor chip is electrically connected to the controller chip.

[0004] In some embodiments, the second memory chips are arranged in a stepped manner.

[0005] In some embodiments, the number of second memory chips is greater than or equal to four.

[0006] In some embodiments, the first memory chip includes a volatile memory, while each of the second memory chips includes a memory different from the volatile memory.

[0007] In some embodiments, the memory density of the second memory chip is greater than or equal to eight times the memory density of the first memory chip.

[0008] In some embodiments, the first memory chip has an input / output quantity of 10. D A data transmission rate f D Each of the second memory chips has one input / output quantity (I / O). N A data transmission rate f N The number of the second memory chips is N. s The first memory chip and the second memory chip satisfy I / O. D *f D >= IO N *f N *N s .

[0009] In some embodiments, the number of inputs and outputs of the first memory chip is greater than the number of inputs and outputs of each of the second memory chips.

[0010] In some embodiments, the first memory chip is located between the stack formed by the second memory chip and the controller chip.

[0011] In some embodiments, the memory element further includes a plurality of first bumps contacting the lower surface of the first memory chip and the upper surface of the controller chip. A plurality of conductive posts respectively contact the lower surface of the second memory chip. Second bumps respectively connect the conductive posts to the upper surface of the controller chip.

[0012] In some embodiments, the memory element further includes a plurality of bumps contacting the lower surface of the first memory chip and the upper surface of the controller chip. A plurality of wires connect the upper surface of the second memory chip to the upper surface of the controller chip, respectively. Attached Figure Description

[0013] Several embodiments of this disclosure can be understood by reading the following detailed description and accompanying drawings. It should be noted that, in accordance with standard practice in the art, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of discussion.

[0014] Figure 1 This is a schematic diagram of a deep learning neural network according to some embodiments of the present disclosure.

[0015] Figure 2 This is a circuit diagram of a NAND architecture memory according to some embodiments of the present disclosure.

[0016] Figure 3 This is a schematic diagram of a memory element according to some embodiments of the present disclosure.

[0017] Figure 4 This is a schematic diagram of a memory element according to some embodiments of the present disclosure.

[0018] Figure 5 This is a schematic diagram of a memory element according to some embodiments of the present disclosure.

[0019] Figure 6 This is a schematic diagram of a memory element according to some embodiments of the present disclosure.

[0020] Explanation of reference numerals in the attached figures

[0021] 30: Memory unit

[0022] 31, 32: NAND strings

[0023] 35: Common source line 35

[0024] 36: Serial select transistor 36

[0025] 37: Ground selection transistor 37

[0026] 100: Memory element

[0027] 102: Input Layer

[0028] 106, 108, 110: Hidden layers

[0029] 104: Output Layer

[0030] 112, 114, 116, 118: Synaptic layer

[0031] 122, 124, 126, 128: Neurons

[0032] 132, 134, 136: Weights

[0033] 200, 201, 300, 301: Memory elements

[0034] 202: Memory Structure

[0035] 202A, 202B, 302B: Memory chips

[0036] 203: Dielectric materials

[0037] 210: Processor chip

[0038] 215: Intermediary Layer

[0039] 216: Packaging substrate

[0040] 225: Controller chip

[0041] 235: Conductive post

[0042] 240A, 240B, 245, 246, 250, 251: Bumps Detailed Implementation

[0043] The following disclosure provides numerous different embodiments or examples for implementing various features of the main content provided by the present invention. The components and configurations of a particular example are described below to simplify the disclosure. Of course, this example is merely illustrative and is not intended to be limiting. For example, the description below of "a first feature formed above or on a second feature" may, in an embodiment, include direct contact between the first and second features, or may include the formation of an additional feature between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. This repetition is for simplification and clarification and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0044] Furthermore, spatial relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” etc., are used herein to simplify the description of the relationship between one element or feature and another, as illustrated in the accompanying drawings. In addition to depicting the orientation shown in the drawings, spatial relative terms also encompass different orientations of the element in use or operation. This device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used in this invention will be interpreted accordingly.

[0045] Figure 1 This is a schematic diagram of a deep learning neural network according to some embodiments of the present disclosure. Neural networks are information processing paradigms inspired by how biological nervous systems process information. With the availability of large training datasets and complex learning algorithms, neural networks have facilitated significant advancements in numerous fields such as computer vision, speech recognition, and natural language processing.

[0046] The basic computational unit in a neural network is the neuron. A neuron receives input from other neurons or from external sources and calculates the output. Figure 1Draw an example neural network 100. The neural network 100 contains multiple neurons arranged in layers. The neural network 100 includes an input layer 102 (i.e., neurons that provide input data), three hidden layers 106, 108, and 110 (i.e., neurons that perform computations and transmit information from the input neurons to the output neurons), and an output layer 104 (i.e., neurons that provide output data). Neurons in adjacent layers have synaptic layers connecting them. For example, synaptic layer 112 connects neurons in the input layer 102 and hidden layer 106, synaptic layer 114 connects neurons in hidden layers 106 and 108, synaptic layer 116 connects neurons in hidden layers 108 and 110, and synaptic layer 118 connects neurons in hidden layer 110 and output layer 104. All these connections have weights associated with them. For example, neurons 122, 124, and 126 in hidden layer 106 are connected via weights w1 132, w2 134, and w3 134, respectively. Connection 136 is connected to neuron 128 in hidden layer 108. The output of neuron 128 in hidden layer 108 can be computed as a function based on the inputs (x1, x2, and x3) from neurons 122, 124, and 126 in hidden layer 106 and the weights w1 132, w2 134, and w3 136 in the connections. This function can be expressed as follows:

[0047]

[0048] In the sum-of-products expression above, each product term is a variable input x. i and weight w i The product of the weights w. i These terms can vary, for example, the coefficients corresponding to the variable input xi. Similarly, the outputs of other neurons in the hidden layer can also be calculated. The outputs of the two neurons in hidden layer 110 are used as inputs to the output neurons in output layer 104.

[0049] Neural networks can be used to learn patterns that best represent large amounts of data. Hidden layers closer to the input layer learn high-level general patterns, while hidden layers closer to the output layer learn more data-specific patterns. Training is the stage where the neural network learns from training data. During training, weights are assigned to connections in the synaptic layers based on the results of the training period. Inference is the stage where the trained neural network infers / predicts input data and produces output data based on the predictions.

[0050] exist Figure 1In a neural network 100, every point and every line is data and needs to be stored in memory. Figure 1 The X direction can be considered as the model depth, the Y direction as the model width, and the Z direction (not shown) as the batch size for parallel processing. Therefore, XYZ can be considered as the memory requirement.

[0051] The purpose of training a neural network is to improve its learning ability. More specifically, a neural network calculates a prediction for an input through forward calculation and compares this prediction with the standard answer. The difference between the prediction and the standard answer is then propagated back into the neural network via backward propagation. The weights in the neural network are then updated based on this difference. Generally speaking, forward calculation can be viewed as moving along... Figure 1 In the X direction, multiplication and addition are performed layer by layer. On the other hand, reverse propagation can be viewed as proceeding in reverse. Figure 1 In the X direction, relatively complex differential calculations are performed layer by layer.

[0052] The completion of the above operations will change the memory data once or twice. For example, in forward computation, a small amount of memory data will change once. In reverse computation, a large amount of memory data will change once.

[0053] Once training is complete, the trained neural network can follow... Figure 1 The X direction is used for the actual situation. That is, reasoning can be performed. In this case, the neural network will calculate a reasonable prediction result based on the input features through forward computation.

[0054] Taking forward computation as an example, the data for each neuron in each layer is calculated through three stages: stage a is the reading and writing of neuron data, stage b is the reading and writing of weight data, and stage three is the computation stage. Using neuron 128 as an example, in stage a, the memory reads the data from neurons 122, 124, and 126 in hidden layer 106. In stage b, the memory reads the data from weights w1 132, w2 134, and w3 136 in synaptic layer 114. In stage c, the processor calculates the aforementioned product and expression.

[0055] The three stages described above can be considered as one computation cycle. In some embodiments, the number of layers in the neural network 100 is equal to the number of computation cycles. For example, if the neural network 100 has 100 layers, then 100 computation cycles are required in the forward computation.

[0056] Similar operations occur during backpropagation. For example, backpropagation involves reading and writing neuron data (stage 1a), modifying / writing weight data (stage 2b), and computation (stage 3c). As mentioned earlier, backpropagation involves complex differential computation and requires modifying / writing a large amount of weight data. Therefore, the overall operation time for backpropagation is greater than that for forward computation. In some embodiments, inference operations only involve forward computation and are relatively fast. Training operations, however, involve both forward computation and backpropagation, resulting in a longer operation time, with most of the time spent on backpropagation.

[0057] In the computation cycle, the first stage a and the second stage b are related to memory read and write operations, during which the memory needs to be operated at high speed. However, the third stage c does not require memory operation; instead, the processor performs calculations on the data. In some embodiments, the processor may be a GPU, TPU, ultra-small CPU, DPU, APU, FPGA, etc.

[0058] Traditional high-bandwidth memory (HBM) is frequently used in artificial intelligence computations. HBM features multiple stacked DRAM chips. As mentioned earlier, the memory operates at full speed between the first stage a and the second stage b, but no operation is required in the third stage c. Some experiments show that the full-speed operation time of DRAM in traditional HBM accounts for only an average of 3.2% of the total computation time per computation cycle.

[0059] To address the aforementioned issues, this disclosure proposes a memory element having multiple stacked memory chips, where only a small portion of the memory (e.g., DRAM) requires high-speed operation, while the remaining portion of the memory can be copied from the high-speed memory to the NAND architecture memory via the aforementioned third stage c by configuring several high-density NAND architecture memory chips. This not only significantly reduces the memory speed specification requirements but also facilitates increased memory density.

[0060] Figure 2This is a circuit diagram of a NAND architecture memory according to some embodiments of the present disclosure. In some embodiments, this NAND architecture memory includes NAND strings 31 and 32, each containing a plurality of memory cells 30 connected in series. In some embodiments, each memory cell has a transistor-like structure. The memory cell may contain a core storage material. In some embodiments, the core storage material may be a charge-trapping material, such as silicon nitride (SiN), or other suitable materials. In other embodiments, the core storage material may be a conductor or a doped semiconductor, such as a floating gate element.

[0061] This NAND architecture memory also includes multiple word lines (WL). Each word line (WL) is electrically connected to a memory cell 30. In some embodiments, each word line (WL) is electrically connected to the gate of the corresponding memory cell 30.

[0062] NAND strings 31 and 32 are coupled to their respective bit lines BL-1 and BL-2 via string select transistor 36, and to common source line 35 via ground select transistor 37.

[0063] In general, non-volatile NAND flash memory typically has a large capacity due to its small storage cells. However, non-volatile NAND flash memory generally has extremely high data retention, poor latency, and poor endurance. Therefore, non-volatile NAND flash memory has historically been used in storage devices such as hard drives.

[0064] The NAND architecture memory used in this disclosure achieves high endurance by, for example, adjusting the thickness or material of the charge-capturing material, changing the charge-capturing material, and altering the programming / erasing method. In some embodiments, the endurance of this NAND architecture memory can reach 10⁶ to approximately 10¹⁰ cycles. In some embodiments, the data retention of the NAND architecture memory is lower than that of conventional non-volatile NAND memory. For example, conventional non-volatile NAND memory may have a data retention period of 10 years, while the data retention of the NAND architecture memory of this disclosure may be approximately 1 second to approximately 1 year. In some embodiments, the NAND architecture memory of this disclosure has volatile characteristics, requiring a refresh mechanism to maintain the data in the memory. Therefore, the NAND architecture memory of this disclosure may also be referred to as volatile NAND memory. In this document, the term "endurance" can be considered as the maximum number of times the memory can be programmed / erased. The term "data retention" can be considered as the maximum time the stored state is maintained within the memory cell.

[0065] Based on the above, the NAND architecture memory used in this disclosure retains the high density advantage of common non-volatile NAND memory, and also has high durability, making it suitable for the computing needs of big data and artificial intelligence. Although NAND architecture memory has the problem of poor latency, the latency requirements of big data and artificial intelligence computing are relatively low. In conclusion, this "volatile" NAND architecture memory is helpful for future big data and artificial intelligence computing.

[0066] Figure 3 This is a schematic diagram of a memory element according to some embodiments of the present disclosure. The diagram illustrates a memory element 200 for artificial intelligence, wherein the memory element 200 can be used to perform, for example... Figure 1 The training of the neural network under discussion. Memory element 200 includes memory structure 202, a controller chip 225, a processor chip 210, an interposer 215, and a package substrate 216.

[0067] The memory structure 202 can be viewed as a three-dimensional memory array. For example, the memory structure 202 may include a memory chip 202A and a plurality of memory chips 202B stacked in a stepped manner. In some embodiments, the memory chip 202A is located between the stack of memory chips 202B and the controller chip 225.

[0068] Memory chips 202A and 202B are electrically connected to controller chip 225, respectively. In some embodiments, controller chip 225 may serve as a memory control element for memory chips 202A and 202B, used to access memory cells of memory chips 202A and 202B. For example, controller chip 225 may include a row decoder, a column decoder, word lines, bit lines, other components, or combinations thereof. In some embodiments, controller chip 225 may be used to input and / or output data to memory chips 202A and 202B. In some embodiments, controller chip 225 has a signal transmission interface for transmitting data from memory chips 202A and 202B to intermediate board 215.

[0069] In some embodiments, the memory element 200 further includes a dielectric material 203 covering a stack of memory chips 202B. In some embodiments, the dielectric material 203 covers at least the lower surface of the bottommost memory chip 202B and the upper surface of the topmost memory chip 202B. In some embodiments, the lower surface of the bottommost memory chip 202B is separated from the memory 202A by the dielectric material 203.

[0070] The memory element 200 also includes a plurality of conductive posts 235 in the dielectric material 203. In some embodiments, each conductive post 235 contacts and is electrically connected to the lower surface of a corresponding memory chip 202B. In some embodiments, each conductive post 235 extends downward from the lower surface of the corresponding memory chip 202B and is exposed from the lower surface of the dielectric material 203. In some embodiments, the memory chip 202A also contacts the lower surface of the dielectric material 203. In some embodiments, the conductive post 235 may be referred to as a through dielectric via (TDV).

[0071] The memory element 200 further includes bumps 240A and 240B. Bump 240A is disposed between the memory chip 202A and the controller chip 225, electrically connecting the memory chip 202A to the controller chip 225. Bump 240B is disposed between the lower surface of the dielectric material 203 and the controller chip 225. In some embodiments, bumps 240B contact corresponding conductive posts 235 to electrically connect the memory chip 202B to the controller chip 225. In some embodiments, bumps 240A and 240B have different dimensions. For example, the height (thickness) of bump 240A is less than the height of bump 240B. In other embodiments, bump 240A may be omitted, and the memory chip 202A may be connected to the controller chip 225 via copper-copper bonding.

[0072] In some embodiments, memory chips 202A and 202B are both electrically connected to controller chip 225 via their lower surfaces. In other words, memory chips 202A and 202B are electrically connected to controller chip 225 via the same side. In some embodiments, memory chips 202A and 202B have signal transmission interfaces only on their lower surfaces, and neither has a signal transmission interface on its upper surface. In some embodiments, memory chips 202A and 202B have signal transmission interfaces on both their upper and lower surfaces; however, memory chips 202A and 202B are only electrically connected to controller chip 225 via their lower surfaces.

[0073] In some embodiments, memory chip 202A and memory chip 202B are different types of memory. Memory chip 202B may include components such as... Figure 2 The NAND architecture memory under discussion. In some embodiments, this NAND architecture memory may have high endurance and be "volatile". On the other hand, memory chip 202A may include other volatile memories, such as DRAM or SRAM. That is, memory structure 202 is a hybrid memory structure that includes at least two different types of memory.

[0074] In some embodiments, memory chip 202A may be DRAM, while each memory chip 202B is a NAND architecture memory with volatile characteristics as described above. In some embodiments, the number of inputs / outputs of memory chip 202A is 10. D The input / output data transfer rate of memory chip 202A is f. D The memory density of the 202A memory chip is D. D On the other hand, the 202B memory chip has 10 I / O pins. NThe input / output data transfer rate of the memory chip 202B is f. N The memory density of the 202B memory chip is D. N And the number of stacked layers of memory chip 202B is N. S .

[0075] The stacking of memory chips 202A and 202B can satisfy the following conditions. For example, IO... D *f D >= IO N *f N *N s In other words, the total transfer rate of a single memory chip 202A is greater than or equal to the total transfer rate of the stack of memory chips 202B. In some embodiments, 32 >= N S >=4. In some embodiments, D N >=8*D D In other words, the memory density of each memory chip 202B is greater than or equal to eight times the memory density of the memory chip 202A. In some embodiments, IO D >= 32 (e.g., 64 / 128 / 256 / 1024 or more), and IO N =8 or 16. That is, the number of inputs / outputs of each memory chip 202A will be more than the number of inputs / outputs of each memory chip 202B. In some embodiments, there are no more than 2 memory chips 202A.

[0076] For example, if memory chip 202A is DRAM, it includes 8Gb capacity, 1024 inputs / outputs, and an access rate of 2Gb / s. On the other hand, if each memory chip 202B is the aforementioned volatile NAND architecture memory, it includes 64Gb capacity, 8 inputs / outputs, and an access rate of 2Gb / s. Figure 3 In one embodiment, a stack of eight memory chips 202B is drawn, thus having a total capacity of 512Gb and 64 inputs / outputs.

[0077] In some embodiments, the memory chip 202B does not necessarily have to be as described above. Figure 2 The NAND architecture memory under discussion. In other embodiments, memory chip 202B has a higher memory density than memory chip 202A. That is, memory chip 202B has more memory cells and a higher memory capacity per unit area than memory chip 202A. For example, memory chip 202B may also be phase change memory (PCM) or other suitable memory.

[0078] Processor chip 210 may include a large number of small cores. For example, processor chip 210 may include graphics devices, such as graphics processing units (GPUs). In other embodiments, processor chip 210 may include TPUs, mini CPUs, DPUs, APUs, etc. In yet another embodiment, processor chip 210 may include central processing units (CPUs). Processor chip 210 may be electrically connected to intermediate plate 215 via bump 245. Controller chip 225 may be electrically connected to intermediate plate 215 via bump 246. Intermediate plate 215 may be used to connect different components, such as memory structure 202, processor chip 210, and / or the underlying package substrate 216. In some embodiments, intermediate plate 215 may be electrically connected to the underlying package substrate 216 via bump 250. In some embodiments, package substrate 216 and bump 250 may not be present.

[0079] Figure 4 This is a schematic diagram of a memory element according to some embodiments of the present disclosure. Figure 4 Some components and Figure 3 The descriptions are similar, therefore these components will use the same component symbols, and the relevant details will not be repeated.

[0080] Figure 4 memory element 201 and Figure 3 The difference between memory element 200 and memory element 200 is that... Figure 4 The processor chip 210 is configured on the other side of the interposer 215 opposite to the memory structure 202. That is, in Figure 3 In one embodiment, the memory structure 202 and the processor chip 210 are configured on the same side of the interposer 215. However, in Figure 4 In one embodiment, the memory structure 202 and the processor chip 210 are configured on opposite sides of the interposer 215.

[0081] In more detail, Figure 4 The processor chip 210 is electrically connected via bumps 251 and the lower surface of the interposer 215. Therefore, the processor chip 210 can be electrically connected to the controller chip 225 via the interposer 215. In some embodiments, the interposer 215 may be omitted. That is, the processor chip 210 can be electrically connected to the controller chip 225 solely via bumps, without needing to go through other chips. This configuration can reduce the overall area occupied by the memory element 201.

[0082] Figure 5This is a schematic diagram of a memory element according to some embodiments of the present disclosure. Figure 5 Some components and Figure 3 The descriptions are similar, therefore these components will use the same component symbols, and the relevant details will not be repeated.

[0083] Figure 5 The memory element 302 includes a stack of memory chips 202A and multiple memory chips 302B, wherein Figure 5 The memory chip 302B is stacked in a stepped manner. Figure 5 The structure of the memory chip 302B is similar to Figure 3 The memory chip 202B. The relationship between memory chip 202A and memory chip 302B is similar to... Figure 3 The relationship between memory chip 202A and memory chip 202B discussed will not be elaborated further.

[0084] Figure 5 Unlike Figure 3 The key difference lies in the fact that the memory chip 302B is electrically connected to the controller chip 225 via wire bonding. In some embodiments, the memory element 302 includes a plurality of wires 335, each wire 335 contacting and electrically connecting to the upper surface of a corresponding memory chip 302B. In some embodiments, each wire 335 connects from the upper surface of the corresponding memory chip 302B to the upper surface of the controller chip 225. Therefore, compared to... Figure 3 The memory chip 202B, Figure 5 Each memory chip 302B only needs to be electrically connected to the controller chip 225 via wire 335, without needing to go through bumps.

[0085] In some embodiments, memory chip 202A is electrically connected to controller chip 225 via its lower surface. However, memory chip 302B is electrically connected to controller chip 225 via its upper surface. In other words, memory chips 202A and 302B are electrically connected to controller chip 225 via different sides. In some embodiments, memory chip 202A has a signal transmission interface only on its lower surface and no signal transmission interface on its upper surface. Memory chip 302B has a signal transmission interface only on its upper surface and no signal transmission interface on its lower surface. In some embodiments, memory chips 202A and 302B have signal transmission interfaces on both their upper and lower surfaces; however, memory chip 202A is electrically connected to controller chip 225 only via its lower surface, while memory chip 302B is electrically connected to controller chip 225 only via its upper surface.

[0086] Figure 6 This is a schematic diagram of a memory element according to some embodiments of the present disclosure. Figure 6 Some components and Figure 5 The descriptions are similar, therefore these components will use the same component symbols, and the relevant details will not be repeated.

[0087] Figure 6 memory element 301 and Figure 5 The difference between memory element 300 and memory element 300 is that... Figure 6 The processor chip 210 is configured on the other side of the interposer 215 opposite to the memory structure 302. That is, in Figure 5 In one embodiment, the memory structure 302 and the processor chip 210 are configured on the same side of the interposer 215. However, in Figure 6 In one embodiment, the memory structure 302 and the processor chip 210 are configured on opposite sides of the interposer 215.

[0088] More specifically, the processor chip 210 is electrically connected via bumps 251 and the lower surface of the interposer 215. Therefore, the processor chip 210 can be electrically connected to the controller chip 225 via the interposer 215. In some embodiments, the interposer 215 may be omitted. That is, the processor chip 210 can be electrically connected to the controller chip 225 solely via bumps, without needing to pass through other chips. This configuration reduces the overall area occupied by the memory element 301.

[0089] This disclosure proposes a memory element suitable for artificial intelligence computing, which requires only a small number of first memory chips with high-speed operation needs (e.g., Figures 3 to 6 The memory chip 202A under discussion. Furthermore, the memory element can be configured with several high-density second memory chips (e.g., Figures 3 to 6 The memory chips discussed are 202B and 302B. Figure 1 During the write operation, the control chip (e.g. Figures 3 to 6 The controller chip 225 under discussion can write data to a first memory chip (e.g., memory chip 202A) in a first time period (e.g., first stage a and second stage b), and copy data from the first memory chip to a second memory chip (e.g., memory chip 202B or 302B) in a second time period (e.g., third stage). Similarly, in Figure 1In the read operation, the control chip can copy data from the second memory chip (e.g., memory chip 202B or 302B) to the first memory chip (e.g., memory chip 202A) in the first time (e.g., the first stage a and the second stage b), and transfer the data from the first memory chip to the processor chip (e.g., processor chip 210) in the second time (e.g., the third stage).

[0090] Based on the above discussion, it is clear that this disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed in this disclosure, nor do all embodiments possess specific advantages. In big data or artificial intelligence computing, highly parallel and deep learning methods are often used to process problems. Therefore, large, deep structures, in addition to requiring large amounts of memory, also extend memory data retention time and reduce the number of read / write operations. One advantage of this disclosure is that using NAND-based non-volatile memory in big data or artificial intelligence computing can not only significantly reduce the requirements for memory speed specifications but also increase memory density.

[0091] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the embodiments of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures to achieve the same purpose and / or realize the same advantages. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the present invention.

Claims

1. A memory element, characterized in that, Include: A memory structure, comprising: A first memory chip; and A stack of multiple second memory chips, wherein the memory density of each of the second memory chips is higher than the memory density of the first memory chip; A controller chip, electrically connected to the first memory chip and these second memory chips; and A processor chip is electrically connected to the controller chip; The first memory chip has an input / output quantity of 10. D A data transmission rate f D Each of these second memory chips has one input / output number (I / O). N A data transmission rate f N The number of these second memory chips is N. s The first memory chip and these second memory chips satisfy IO D *f D >=IO N *f N *N s .

2. The memory element according to claim 1, characterized in that, These second memory chips are arranged in a stepped pattern.

3. The memory element according to claim 1, characterized in that, The number of these second memory chips is greater than or equal to four.

4. The memory element according to claim 1, characterized in that, The first memory chip includes a volatile memory, while each of the second memory chips includes a memory different from the volatile memory.

5. The memory element according to claim 1, characterized in that, The memory density of these second memory chips is greater than or equal to eight times the memory density of the first memory chip.

6. The memory element according to claim 1, characterized in that, The number of inputs and outputs of the first memory chip is greater than the number of inputs and outputs of each of the second memory chips.

7. The memory element according to claim 1, characterized in that, The first memory chip is located between the stack formed by these second memory chips and the controller chip.

8. The memory element according to claim 1, characterized in that, Also includes: Multiple first bumps contact a lower surface of the first memory chip and an upper surface of the controller chip; Multiple conductive pillars contact multiple lower surfaces of these second memory chips, respectively; as well as Multiple second bumps connect these conductive posts to the upper surface of the controller chip.

9. The memory element according to claim 1, characterized in that, Also includes: Multiple bumps contact a lower surface of the first memory chip and an upper surface of the controller chip; and Multiple wires connect the upper surfaces of these second memory chips to the upper surface of the controller chip, respectively.

Images