A voltage withstanding power device and a manufacturing method thereof

Abstract

The present application relates to the field of semiconductor device manufacturing, and particularly relates to a voltage withstanding power device and a manufacturing method thereof, the method comprising the following steps: providing a semiconductor layer; forming a trench on the semiconductor layer; measuring the depth of the trench; forming a field oxide layer on the upper surface of the semiconductor layer and the sidewall of the trench; forming a shield gate structure in the trench; performing a heat treatment process; etching part of the field oxide layer until the height of the upper surface thereof is lower than the height of the upper surface of the shield gate structure; generating a gate-source dielectric layer above the shield gate structure; generating a gate oxide layer on at least the upper surface of the semiconductor layer and the exposed sidewall of the trench; and generating a gate structure above the gate-source dielectric layer. Compared with the prior art, the present application can keep the diffusion partition boundary line close to the bottom of the trench, maintain the balance of the electric field distribution, and has significant beneficial effects.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and in particular to a voltage-resistant power device and its manufacturing method. Background Technology

[0002] Currently, semiconductor trench etching is an essential step in existing power devices. However, in deep trench etching processes, the depth of the etched trenches may vary due to process errors. This difference in trench depth can significantly affect the breakdown voltage performance of the manufactured power devices, increasing the uncertainty of the breakdown voltage performance.

[0003] Therefore, existing technologies still need improvement. Summary of the Invention

[0004] The purpose of this invention is to solve the problem of unstable voltage withstand performance of power devices in the prior art.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: This invention provides a method for manufacturing a voltage-resistant power device, comprising the following steps: Provides a semiconductor layer; A trench is formed on the semiconductor layer; the semiconductor layer includes a first partition and a second partition with different epitaxial concentrations distributed along the depth direction of the trench. Measure the depth of the trench; A field oxide layer is formed on the upper surface of the semiconductor layer and the sidewalls of the trench; A shielding gate structure is formed within the trench; A heat treatment process is performed so that the boundary line between the first and second partitions is close to the bottom of the trench; Etch a portion of the field oxide layer until the height of its upper surface is lower than the height of the upper surface of the shielding gate structure; A gate-source dielectric layer is generated above the shielded gate structure; A gate oxide layer is formed at least on the upper surface of the semiconductor layer and on the exposed trench sidewalls; A gate structure is generated above the gate-source dielectric layer.

[0006] Furthermore, forming trenches within the semiconductor layer includes: A patterned mask layer is formed on the upper surface of the semiconductor layer, and the patterned mask layer has an opening pattern defined as the shape and position of the trench; The semiconductor layer is etched based on the patterned mask layer to form the trench within the semiconductor layer.

[0007] Furthermore, the depth of the trench is between a minimum threshold and a maximum threshold.

[0008] Furthermore, a shielding gate structure is formed within the trench, including: Deposit polysilicon shielding gates within the trenches; The shielding gate polysilicon is etched to a first height to form a shielding gate structure, the first height being lower than the height of the upper surface of the semiconductor layer.

[0009] Furthermore, the heat treatment process includes: Obtain the depth of the trench; If the depth of the trench is between the minimum threshold and the first depth, then perform heat treatment at 1000℃ for 60 minutes. If the depth of the trench is between the first depth and the second depth, then perform heat treatment at 1000℃ for 30 minutes. If the depth of the trench is between the second depth and the maximum threshold, no heat treatment is performed; Where the minimum threshold is less than the first depth, the second depth, and the maximum threshold. Further, forming a gate-source dielectric layer above the shielded gate structure includes: Perform gate-source dielectric oxide deposition; The upper surface of the gate-source dielectric oxide is subjected to chemical mechanical polishing; The gate source dielectric oxide is etched to a second height, which is lower than the height of the upper surface of the semiconductor layer but higher than the first height.

[0010] Furthermore, a gate structure is formed above the gate-source dielectric layer, including: Deposit gate polysilicon above the gate-source dielectric layer within the trench; The gate polysilicon is etched back to the third height, which is lower than the height of the upper surface of the gate oxide layer.

[0011] The present invention also provides a voltage-resistant power device, which is prepared by the above-described method for preparing a voltage-resistant power device.

[0012] The beneficial effects of this invention are: it can perform corresponding heat treatment according to different trench depths, thereby controlling the diffusion of trench partitions in a targeted manner, keeping the boundary area at the bottom of the trench as much as possible, so as to balance the electric field distribution and improve the withstand voltage performance of the device. Attached Figure Description

[0013] Figure 1 This is a flowchart of the preparation method provided by the present invention; Figure 2 This is a schematic cross-sectional view of the structure obtained in step S10 of the fabrication method of the voltage-resistant power device provided in one embodiment; Figure 3 This is a schematic cross-sectional view of the structure obtained in step S20 of the fabrication method of the withstand voltage power device provided in one embodiment; Figure 4 This is a schematic cross-sectional view of the structure obtained in step S40 of the fabrication method of the voltage-resistant power device provided in one embodiment; Figure 5 This is a schematic cross-sectional view of the structure obtained in step S50 of the fabrication method of the withstand voltage power device provided in one embodiment; Figure 6 This is a schematic cross-sectional view of the structure obtained in step S70 of the fabrication method of the voltage-resistant power device provided in one embodiment; Figure 7 This is a schematic cross-sectional view of the structure obtained in step S80 of the fabrication method of the withstand voltage power device provided in one embodiment; Figure 8 This is a schematic cross-sectional view of the structure obtained in step S90 of the fabrication method of the withstand voltage power device provided in one embodiment; Figure 9 This is a schematic cross-sectional view of the structure obtained in step S100 of the fabrication method of the withstand voltage power device provided in one embodiment; Figure 10 This is a schematic diagram of the semiconductor layer partitioning structure of a voltage-resistant power device provided in one embodiment at a first trench depth; Figure 11 This is a schematic diagram of the semiconductor layer partitioning structure of a voltage-resistant power device provided in one embodiment when the trench depth is second. Figure 12 This is a schematic diagram of the semiconductor layer partitioning structure of a voltage-resistant power device provided in one embodiment at the third trench depth. Detailed Implementation

[0014] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0015] In the description of this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0016] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0017] In the description of this embodiment, the terms "upper," "lower," "right," etc., refer to the orientation or positional relationship shown in the accompanying drawings. They are used only for ease of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first" and "second" are used only for distinction in description and have no special meaning.

[0018] In step S10, please refer to Figure 1 Step S10 in the middle and Figure 2 , providing semiconductor layer 1.

[0019] In step S20, please refer to Figure 1 Step S20 in the middle and Figure 3 A trench 11 is formed within the semiconductor layer 1.

[0020] As an example, step S20 may include the following steps: S201: A patterned mask layer 10 is formed on the upper surface of the semiconductor layer 1. The patterned mask layer 10 has an opening pattern (not shown), and the opening pattern is defined as the shape and position of the trench 11. S202: Based on the patterned mask layer 10, the semiconductor layer 1 is etched to form the trench 11 within the semiconductor layer 1, such as... Figure 3 As shown.

[0021] In step S30, please refer to Figure 1 In step S30, the depth of the etched trench 11 needs to be measured. In this embodiment, the manufactured device is a device that is applied to a voltage of 100V. The target etching depth of the trench is 60,000 angstroms. Due to the etching process, it may cause a deviation of ±3,000 angstroms.

[0022] In semiconductor trench structures, please refer to Figures 10-12Based on the distribution of epitaxial concentration after trench etching, the semiconductor structure can be divided into two partitions, EPI1 and EPI2. The boundary between these partitions is roughly located at the preset depth (bottom of the trench), which ensures the balance of the electric field distribution and improves the withstand voltage performance.

[0023] However, as Figures 10-12 As shown, the trench depth varies in different wafers, resulting in differences in the partitioning distribution. Under certain operating conditions, the boundary between EPI1 and EPI2 partitions is not located at the bottom of the trench, such as... Figure 10 The trenches in the middle are too deep, and the dividing lines of the zones are higher than the bottom of the trenches; while Figure 12 If the trenches are too shallow and the dividing lines of the partitions are much lower than the bottom of the trenches, this will lead to uneven electric field distribution and affect the withstand voltage performance of the device.

[0024] In step 40, please refer to Figure 1 Step S40 in the middle and Figure 4 A field oxide layer 12 is formed on the upper surface of the semiconductor layer 1 and the sidewalls of the trench 11.

[0025] In step 50, please refer to Figure 1 S50 steps and Figure 5 A shielding gate structure 13 is formed within the trench 11.

[0026] As an example, step 50 may include the following steps: S501: Deposit polysilicon shielding gate within the trench; S502: Etch the shielding gate polysilicon to a first height to form a shielding gate structure, the first height being lower than the height of the upper surface of the semiconductor layer.

[0027] In step 60, please refer to Figure 1 In step S60, a heat treatment process is performed to move the boundary line between the EPI1 and EPI2 partitions to the bottom of the trench 11. As an example, this embodiment selects a device suitable for 100V voltage, with a trench depth range of 60,000 angstroms ± 3,000 angstroms. Taking the manufacturing method of this device as an example, step 60 is performed according to the following strategy: S601: Obtain the depth of trench 11 measured in S30; S602: Perform a judgment: If the depth of trench 11 is 57,000 to 59,000 angstroms, it is determined that the boundary line between EPI1 and EPI2 is far from the bottom of trench 11, and a heat treatment at 1000°C for 60 minutes is required to make the boundary line move significantly to the bottom of the trench. If the depth of trench 11 is between 59,000 and 61,000 angstroms, it is determined that the boundary line between EPI1 and EPI2 is close to the bottom of trench 11, and a heat treatment at 1000°C for 30 minutes is required to slightly move the boundary line to the bottom of trench 11. If the depth of trench 11 is between 61,000 and 63,000 angstroms, it is determined that the boundary between EPI1 and EPI2 partitions is at or even beyond the bottom of trench 11, and heat treatment is no longer performed.

[0028] It should be noted that the devices and trench depth ranges selected here are exemplary. When the applicable voltage of the manufactured devices is different, the trench depth will also change accordingly, which is understandable to those skilled in the art. For example, the trench depth of a device with an operating voltage of 60V will be about 35,000 angstroms. The trench depth and applicable voltage of the devices mentioned in this embodiment should not be construed as limitations on the present invention.

[0029] In step 70, please refer to Figure 1 The S70 step and Figure 6 Partial etching of the oxide layer 12 is performed so that the height of its upper surface is lower than that of the shielding gate 13 structure.

[0030] In step 80, please refer to Figure 1 S80 steps and Figure 7 A gate-source dielectric layer is generated above the shielded gate structure.

[0031] As an example, step 80 may include the following steps: S801: Perform gate-source dielectric oxide deposition; S802: Perform chemical mechanical polishing on the upper surface of the gate-source dielectric oxide; S803: Etch the gate source dielectric oxide to a second height, which is lower than the height of the upper surface of the semiconductor layer 1 but higher than the height of the upper surface of the shield gate 13, to form the gate source dielectric layer 14.

[0032] In step 90, please refer to Figure 1 S90 steps and Figure 8 A gate oxide layer 15 is formed on the upper surface of the semiconductor layer 1 and on the exposed sidewalls of the trench 11.

[0033] In step 100, please refer to Figure 1 Step S100 in and Figure 9 A gate structure 16 is formed above the gate-source dielectric layer 14.

[0034] As an example, step 100 may include the following steps: Gate polysilicon is deposited above the gate-source dielectric layer 14 within the trench 11; The gate polysilicon is etched back to a third height, which is lower than the height of the upper surface of the gate oxide layer 15, to generate the gate structure 16.

[0035] In addition, subsequent processes include conventional processes such as interlayer dielectric deposition, contact hole etching, metal layer deposition and photolithography, and passivation layer deposition and photolithography. These are all conventional processes in the existing technical field and can be understood by those skilled in the art, so they will not be described in detail here.

[0036] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for manufacturing a voltage-resistant power device, characterized in that, Includes the following steps: Provides a semiconductor layer; A trench is formed on the semiconductor layer, the semiconductor layer comprising a first partition and a second partition with different epitaxial concentrations distributed along the trench depth direction; Measure the depth of the trench; A field oxide layer is formed on the upper surface of the semiconductor layer and the sidewalls of the trench; A shielding gate structure is formed within the trench; A heat treatment process is performed so that the boundary line between the first and second partitions is close to the bottom of the trench; Etch a portion of the field oxide layer until the height of its upper surface is lower than the height of the upper surface of the shielding gate structure; A gate-source dielectric layer is generated above the shielded gate structure; A gate oxide layer is formed at least on the upper surface of the semiconductor layer and on the exposed trench sidewalls; A gate structure is generated above the gate-source dielectric layer.

2. The method for manufacturing a voltage-resistant power device according to claim 1, characterized in that, Forming trenches within the semiconductor layer includes: A patterned mask layer is formed on the upper surface of the semiconductor layer, the patterned mask layer having an opening pattern, the opening pattern being defined as the shape and position of the trench; The semiconductor layer is etched based on the patterned mask layer to form the trench within the semiconductor layer.

3. The method for manufacturing a voltage-resistant power device according to claim 2, characterized in that, The depth of the trench is between the minimum threshold and the maximum threshold.

4. The method for manufacturing a voltage-resistant power device according to claim 1, characterized in that, A shielding gate structure is formed within the trench, including: Deposit polysilicon shielding gates within the trenches; The shielding gate polysilicon is etched to a first height to form a shielding gate structure, the first height being lower than the height of the upper surface of the semiconductor layer.

5. The method for manufacturing a voltage-resistant power device according to claim 3, characterized in that, The heat treatment process includes: Obtain the depth of the trench; If the depth of the trench is between the minimum threshold and the first depth, then perform heat treatment at 1000℃ for 60 minutes. If the depth of the trench is between the first depth and the second depth, then perform a heat treatment at 1000℃ for 30 minutes. If the depth of the trench is between the second depth and the maximum threshold, no heat treatment is performed; The minimum threshold is less than the first depth, which is less than the second depth and the maximum threshold.

6. The method for manufacturing a voltage-resistant power device according to claim 4, characterized in that, The generation of a gate-source dielectric layer above the shielded gate structure includes: Perform gate-source dielectric oxide deposition; The upper surface of the gate-source dielectric oxide is subjected to chemical mechanical polishing; The gate source dielectric oxide is etched to a second height, which is lower than the height of the upper surface of the semiconductor layer but higher than the first height.

7. The method for manufacturing a voltage-resistant power device according to claim 1, characterized in that, A gate structure is formed above the gate-source dielectric layer, including: Gate polysilicon is deposited above the gate-source dielectric layer within the trench; The gate polysilicon is etched back to the third height, which is lower than the height of the upper surface of the gate oxide layer.

8. A voltage-resistant power device, characterized in that, The voltage-resistant power device is prepared by the method for preparing a voltage-resistant power device as described in any one of claims 1 to 7.

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