Semiconductor structure, method of manufacturing a semiconductor structure and manufacturing apparatus
By constructing a sidewall structure in the semiconductor structure and employing step-by-step etching technology, the damage problem of the mandrel structure when removing the spacer wall was solved, achieving higher etching accuracy and improved semiconductor manufacturing yield, thus ensuring product reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-07-10
- Publication Date
- 2026-06-16
AI Technical Summary
In traditional reverse self-aligned dual patterning processes, the mandrel structure is easily damaged when the gap walls are removed, resulting in poor line profiles of the underlying material layer exposed by etching from the gaps, which affects the production yield and reliability of semiconductor manufacturing processes.
After forming a mask material layer and a spaced sacrificial pattern on the substrate, a sidewall structure is constructed, including a portion conformally covering the sidewall of the sacrificial pattern and the surface of the mask material layer, and a filling dielectric layer is formed on it. Unnecessary parts of the sidewall structure are removed by step etching, while parts with good morphology are retained. The etching process is controlled by using etching gas with high selectivity and process temperature to ensure the accuracy and morphology of the target pattern.
By preserving the good morphology of the sidewall structure and mask material layer, line wobble defects are avoided, improving the production yield and product reliability of semiconductor manufacturing processes, and enhancing the accuracy and efficiency of the etching process.
Smart Images
Figure CN116864390B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, and an apparatus for preparing the semiconductor structure. Background Technology
[0002] Reverse self-aligned doubled patterning (Reverse SADP) is currently the mainstream technology used in semiconductor manufacturing to create dense array patterns. The characteristic of reverse self-aligned doubled patterning is that after the first patterning process creates the mandrel structure, gap walls are formed on both sides of the mandrel structure, and another material layer is formed to fill the remaining gaps between the mandrel structures. Subsequently, the gaps created by removing the gap walls serve as etching channels to etch the underlying material layer exposed by the gaps.
[0003] However, in the traditional reverse self-aligned dual patterning process, the mandrel structure is easily damaged when removing the gap wall to form the gap, resulting in poor line profiles formed by etching the underlying material layer exposed from the gap, which in turn causes line wiggling, affecting the production yield of semiconductor manufacturing and the reliability of semiconductor structures. Summary of the Invention
[0004] Based on this, this application provides a semiconductor structure, a method for preparing the semiconductor structure, and an apparatus for preparing the semiconductor structure according to some embodiments, so as to avoid line wobble defects in the semiconductor structure, improve the production yield of the preparation method, and enhance the reliability of the semiconductor structure in use.
[0005] On one hand, this application provides a method for fabricating a semiconductor structure, comprising:
[0006] A substrate is provided; a mask material layer and a patterned sacrificial layer are sequentially formed on the substrate in a direction perpendicular to the substrate, the patterned sacrificial layer including a plurality of sacrificial patterns spaced apart; a sidewall structure is formed, the sidewall structure including a first portion conformally covering the sidewall of the sacrificial pattern and a second portion conformally covering the exposed surface of the mask material layer; a filling dielectric layer is formed on the second portion, the filling dielectric layer filling the gap between adjacent first portions;
[0007] Remove the first portion of the sidewall structure and retain the second portion;
[0008] The second portion of the sidewall structure and the mask material layer are etched based on the sacrificial pattern and the filling medium layer. The sacrificial pattern, the filling medium layer, the retained second portion of the sidewall structure, and the retained mask material layer together constitute the target pattern.
[0009] In some embodiments, removing the first portion of the sidewall structure while retaining the second portion includes:
[0010] The first portion of the sidewall structure is removed using a free radical etching process with an etching gas having a high selectivity.
[0011] In some embodiments, the free radical etching process includes:
[0012] The etching gas dissociates to obtain fluorine-containing free radicals, and at least one of silicon-containing free radicals, carbon-containing free radicals, and hydrogen-containing free radicals.
[0013] In some embodiments, the process temperature of the free radical etching process is less than 20°C.
[0014] In some embodiments, forming the sidewall structure includes:
[0015] A sidewall material layer is conformally covered on the sidewalls and top of the sacrifice pattern and on the exposed surface of the mask material layer; a filling medium material layer is formed covering the sidewall material layer;
[0016] Remove the sidewall material layer located on top of the sacrificial pattern and on the exposed surface of the mask material layer; remove a portion of the height of the filler medium material layer so that the top surface of the remaining filler medium material layer is flush with or approximately flush with the top surface of the sacrificial pattern; the remaining sidewall material layer serves as the sidewall structure, and the remaining filler medium material layer serves as the filler medium layer.
[0017] In some embodiments, a free radical etching process is used to etch back the sidewall material layer located on top of the sacrificial pattern and on the exposed surface of the mask material layer, as well as the filler medium material layer of the specified height, to remove the sidewall material layer located on top of the sacrificial pattern and on the exposed surface of the mask material layer, and to remove the filler medium material layer of the specified height.
[0018] In some embodiments, after forming the target pattern, the method for fabricating the semiconductor structure further includes:
[0019] The substrate is etched based on the sacrifice pattern, the filling dielectric layer, the second portion of the retained sidewall structure, and the retained mask material layer to transfer the target pattern to the substrate.
[0020] In some embodiments, a plasma etching process is used to etch the second portion of the sidewall structure and the mask material layer based on the sacrificial pattern and the filling dielectric layer.
[0021] On the other hand, this application also provides a semiconductor structure fabrication apparatus for performing the semiconductor structure fabrication method provided in the foregoing embodiments; the semiconductor structure fabrication apparatus includes: a free radical etching reaction chamber and a plasma etching reaction chamber; the free radical etching reaction chamber and the plasma etching reaction chamber are connected to the same platform.
[0022] In another aspect, this application also provides a semiconductor structure, which is prepared using the preparation method provided in the foregoing embodiments.
[0023] The semiconductor structure, its fabrication method, and fabrication apparatus provided in this application have at least the following beneficial effects:
[0024] In this embodiment, a sidewall structure is formed after a mask material layer and multiple spaced sacrificial patterns are formed on a substrate. The sidewall structure includes a first portion conformally covering the sidewall of the sacrificial pattern and a second portion conformally covering the exposed surface of the mask material layer. A filling dielectric layer is formed on the second portion, and the filling dielectric layer also fills the gap between adjacent first portions. A step-by-step etching method is used. The first etching removes the first portion of the sidewall structure, retaining the second portion, so that the filling dielectric layer can maintain a good morphology in subsequent etching processes. Then, based on the sacrificial pattern and the filling dielectric layer, the second etching of the second portion of the sidewall structure and the mask material layer is performed a second time. Since both the sacrificial pattern and the filling dielectric layer maintain a good morphology, the second etching process can achieve high precision. Therefore, the second portion of the sidewall structure and the retained mask material layer after the second etching have a good morphology, and thus the target pattern formed by the sacrificial pattern, the filling dielectric layer, the retained second portion of the sidewall structure, and the retained mask material layer also has a good morphology.
[0025] Furthermore, the gaps between adjacent target patterns can serve as etching channels in subsequent processes. Since the target patterns have good morphology, the line profiles formed by the underlying layer structure exposed by etching from the gaps between adjacent target patterns are also good, thereby avoiding defects such as line wobble in the resulting structure, which helps to improve the production yield of semiconductor processes and the reliability of product use. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1A schematic flowchart illustrating the method for fabricating semiconductor structures provided in some embodiments of this application;
[0028] Figure 2 A schematic flowchart of step S100 in the method for fabricating a semiconductor structure provided in some embodiments of this application;
[0029] Figure 3 A schematic cross-sectional view of the structure obtained after forming a sidewall material layer and a filling dielectric material layer in the method for fabricating a semiconductor structure provided in some embodiments of this application;
[0030] Figure 4 A schematic cross-sectional view of the structure obtained after forming the sidewall structure and the filling dielectric layer in the method for fabricating the semiconductor structure provided in some embodiments of this application;
[0031] Figure 5 A schematic cross-sectional view of the structure obtained after removing the first part of the sidewall structure in the method for fabricating a semiconductor structure provided in some embodiments of this application;
[0032] Figure 6 A schematic cross-sectional view of the structure obtained after etching the second part of the sidewall structure and the mask material layer in the semiconductor structure fabrication method provided in some embodiments of this application; Figure 6 This is also a schematic cross-sectional view of the semiconductor structure provided in some embodiments of this application;
[0033] Figure 7 A schematic cross-sectional view of the structure obtained after transferring the target pattern to the substrate in the semiconductor structure fabrication method provided in some embodiments of this application;
[0034] Figure 8 This is a schematic diagram of the structure of a semiconductor structure fabrication apparatus provided in some embodiments of this application.
[0035] Explanation of reference numerals in the attached figures:
[0036] 1. Substrate; 11. Base; 12. Target layer; 2. Mask material layer; 3. Sacrificial pattern; 4. Sidewall structure; 4'. Sidewall material layer; 41. First part; 42. Second part; 5. Filling dielectric layer; 5'. Filling dielectric material layer; 6. Hard mask layer; P. Target pattern; 10. Radical etching reaction chamber; 20. Plasma etching reaction chamber; 301. Vacuum transport chamber; 302. Vacuum manipulator. Detailed Implementation
[0037] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms "first" and "second" may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first portion of a sidewall structure may be referred to as a second portion, and similarly, a second portion may be referred to as a first portion; the first portion and the second portion are different portions of the sidewall structure.
[0040] Spatial relation terms such as “above” can be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the element or feature described as “above” will be oriented “below” other elements or features. Therefore, the exemplary term “above” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0042] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.
[0043] In the traditional Reverse Self-Aligned Doubled Patterning (Reverse SADP) process, the mandrel structure is easily damaged when removing the gap wall to form a gap. This results in poor line profiles formed by etching the underlying material layer exposed by the gap, leading to line wiggling and affecting the production yield of semiconductor manufacturing processes and the reliability of semiconductor structures.
[0044] In view of the shortcomings of the prior art, this application provides a semiconductor structure, a method for fabricating the semiconductor structure, and an apparatus for fabrication, so as to avoid line wobble defects in the semiconductor structure, improve the production yield of the fabrication method, and enhance the reliability of the semiconductor structure in use. Details will be described in subsequent embodiments.
[0045] On one hand, this application provides a method for fabricating a semiconductor structure according to some embodiments. As an example, the method for fabricating the semiconductor structure can be applied to various semiconductor processes, such as word line processes, contact hole structure processes, and metal interconnect structure processes, etc., and is not limited thereto. It is particularly suitable for the reverse self-aligned double patterning process in semiconductor manufacturing.
[0046] Please see Figure 1 In some embodiments, the method for fabricating the semiconductor structure may specifically include the following steps:
[0047] S100: Provide a substrate; sequentially form a mask material layer and a patterned sacrificial layer on the substrate along a direction perpendicular to the substrate, the patterned sacrificial layer including a plurality of sacrificial patterns spaced apart; form a sidewall structure, the sidewall structure including a first portion conformally covering the sidewall of the sacrificial pattern and a second portion conformally covering the exposed surface of the mask material layer; a filling dielectric layer is formed on the second portion, the filling dielectric layer filling the gap between adjacent first portions.
[0048] S200: Remove the first part of the sidewall structure and retain the second part.
[0049] S300: The second part of the sidewall structure and the mask material layer are etched based on the sacrificial pattern and the filling dielectric layer. The sacrificial pattern, the filling dielectric layer, the second part of the retained sidewall structure and the retained mask material layer together constitute the target pattern.
[0050] In the fabrication method provided in the above embodiments, a sidewall structure is formed after a mask material layer and multiple spaced sacrificial patterns are formed on a substrate. The sidewall structure includes a first portion conformally covering the sidewall of the sacrificial pattern and a second portion conformally covering the exposed surface of the mask material layer. A filling dielectric layer is formed on the second portion, and the filling dielectric layer also fills the gap between adjacent first portions. A step-by-step etching method is used. The first etching removes the first portion of the sidewall structure, retaining the second portion, so that the filling dielectric layer can maintain a good morphology in subsequent etching processes. Then, based on the sacrificial pattern and the filling dielectric layer, the second etching of the second portion of the sidewall structure and the mask material layer is performed a second time. Since both the sacrificial pattern and the filling dielectric layer maintain a good morphology, the second etching process can achieve high precision. Therefore, the second portion of the sidewall structure and the retained mask material layer after the second etching have a good morphology, and thus the target pattern formed by the sacrificial pattern, the filling dielectric layer, the retained second portion of the sidewall structure, and the retained mask material layer also has a good morphology.
[0051] Furthermore, the gaps between adjacent target patterns can serve as etching channels in subsequent processes. Since the target patterns have good morphology, the line profiles formed by the underlying layer structure exposed by etching from the gaps between adjacent target patterns are also good, thereby avoiding defects such as line wobble in the resulting structure, which helps to improve the production yield of semiconductor processes and the reliability of product use.
[0052] Please see Figure 2 In some embodiments, step S100 forms the sidewall structure, which may specifically include the following steps:
[0053] S110: Conformally cover the sidewall material layer on the sidewalls and top of the sacrifice pattern and the exposed mask material layer surface; form a filling medium material layer covering the sidewall material layer.
[0054] S120: Remove the sidewall material layer located on top of the sacrificial pattern and on the surface of the exposed mask material layer; remove part of the height of the fill medium material layer so that the top surface of the retained fill medium material layer is flush with or approximately flush with the top surface of the sacrificial pattern; the retained sidewall material layer serves as the sidewall structure, and the retained fill medium material layer serves as the fill medium layer.
[0055] It should be understood that, although Figures 1 to 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1 to 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0056] To more clearly illustrate the preparation methods in some of the above embodiments, please refer to the following... Figures 3 to 7 Understand some embodiments of this application.
[0057] Please see Figure 3 In step S100, substrate 1 is provided.
[0058] As an example, substrate 1 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. Substrate 1 can be a single-layer structure or a multilayer structure. For example, substrate 1 can be a silicon (Si) substrate, silicon dioxide (SiO2) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0059] In some embodiments, such as Figure 3 As shown, substrate 1 may include a base 11 and a target layer 12 formed on the surface of the base 11. As an example, the constituent material of the base 11 may include, but is not limited to, silicon dioxide; the constituent material of the target layer 12 may include, but is not limited to, an amorphous carbon layer (ACL).
[0060] Please continue reading. Figure 3 After providing a substrate 1, a mask material layer 2 and a patterned sacrificial layer are sequentially formed on the substrate 1 along a direction perpendicular to the substrate 1. The patterned sacrificial layer may include a plurality of sacrificial patterns 3 spaced apart.
[0061] As an example, the constituent material of mask material layer 2 may include, but is not limited to, silicon carbide (SiON). As an example, the sacrificial pattern 3 may include, but is not limited to, a spin-on hard mask (SOH) layer.
[0062] After forming the mask material layer 2 and the patterned sacrificial layer, the sidewall structure 4 is formed. For example... Figure 3 As shown, the sidewall structure 4 may include a first portion 41 conformally covering the sidewall of the sacrificial pattern 3 and a second portion 42 conformally covering the surface of the exposed mask material layer 2. A filling medium layer 5 may be formed on the second portion 42, and the filling medium layer 5 also fills the gap between adjacent first portions 41.
[0063] As an example, the constituent material of the sidewall structure 4 may include, but is not limited to, metal oxides. Metal oxides may include, for example, any one of vanadium (V), niobium (Nb), zirconium (Zr), and tantalum (Ta), as well as oxygen (O). In some embodiments, the constituent material of the sidewall structure 4 may include VO X ; where x is a positive real number and x is not equal to zero.
[0064] As an example, the filling dielectric layer 5 can be made of the same or similar materials as the sacrificial pattern 3. This allows the filling dielectric layer 5 and the sacrificial pattern 3 to have similar chemical reactivity, mechanical properties, and coefficients of thermal expansion, thus reducing variability in the fabrication process. Using the same or similar materials also helps reduce interface effects, thereby improving the consistency of the fabrication process and further increasing the production yield of semiconductor manufacturing.
[0065] Please combine Figure 2 And see Figures 3 to 4 In some embodiments, the process of forming the sidewall structure 4 in step S100 can be specifically represented by the following steps S110 to S120.
[0066] In step S110, as Figure 3 As shown, the sidewall material layer 4' is conformally covered on the sidewalls and top of the sacrificial pattern 3 and on the exposed surface of the mask material layer 2. Furthermore, in step S110, a filling medium material layer 5' covering the sidewall material layer 4' is also formed.
[0067] In step S120, as Figure 4As shown, the sidewall material layer 4' located on top of the sacrificial pattern 3 and on the exposed surface of the mask material layer 2 is removed, and a portion of the height of the filler medium material layer 5' is also removed, so that the top surface of the retained filler medium material layer 5' is flush with or approximately flush with the top surface of the sacrificial pattern 3. The retained sidewall material layer 4' serves as the sidewall structure 4, and the retained filler medium material layer 5' serves as the filler medium layer 5.
[0068] For step S120, in some embodiments, a free radical etching process can be used to etch back the sidewall material layer 4' located on top of the sacrificial pattern 3 and the exposed mask material layer surface, as well as the fill medium material layer 5' of a certain height, to remove the sidewall material layer 4' located on top of the sacrificial pattern 3 and the exposed mask material layer surface, and to remove the fill medium material layer 5' of a certain height.
[0069] Please see Figure 5 In step S200, the first part 41 of the side wall structure 4 is removed, while the second part 42 is retained.
[0070] In some embodiments, for step S200 above, an etching gas with a high selectivity (also known as an etching selectivity) can be used to remove the first part 41 of the sidewall structure 4 using a free radical etching process.
[0071] As an example, in the aforementioned free radical etching process, an etching gas with an etching selectivity greater than 5 for the first part 41 of the sidewall structure 4, the sacrificial pattern 3, and the filling dielectric layer 5 can be used. For instance, the etching selectivity of the etching gas for the first part 41 of the sidewall structure 4, the sacrificial pattern 3, and the filling dielectric layer 5 can be 5, 10, 20, 30, or 50, etc.
[0072] In the fabrication method provided in the above example, thanks to the high etching selectivity of the etching gas, the first portion 41 can be precisely removed during the radical etching process, while avoiding damage to the second portion 42. This allows the remaining second portion 42 to have a better morphology, which is beneficial for further improving the production yield of semiconductor processes and the reliability of products. Furthermore, the high selectivity means that the etching gas etches the first portion 41 at a faster rate, making the radical etching process more efficient and allowing it to be completed in a relatively short time, thereby improving the production efficiency of semiconductor processes.
[0073] In some embodiments, the free radical etching process may specifically include the following steps: obtaining fluorine-containing free radicals based on the dissociation of etching gas, and obtaining at least one of silicon-containing free radicals, carbon-containing free radicals, and hydrogen-containing free radicals.
[0074] In the preparation method provided in the above embodiments, the etching gas dissociation can obtain at least one of silicon-containing free radicals, carbon-containing free radicals, and hydrogen-containing free radicals. The silicon-containing free radicals, carbon-containing free radicals, and / or hydrogen-containing free radicals can protect the retained second part 42, avoid damage to the second part 42 during the free radical etching process, ensure that the second part 42 can be retained with a better morphology, and further improve the production yield of semiconductor process and the reliability of product use.
[0075] It is understood that in the preparation method provided in the above embodiments, the first part 41 of the sidewall structure 4 is mainly etched by free radicals obtained by the dissociation of etching gas.
[0076] As an example, the process of dissociating etching gas may specifically include:
[0077] A process gas containing fluorine (F) and at least one of silicon, carbon (C) and hydrogen (H) is provided; an inert gas, such as nitrogen (N2), argon (Ar) or helium (He), is provided and mixed with the aforementioned process gas; the mixed process gas and inert gas are excited, dissociated and / or ionized by a remotely controlled plasma source to generate fluorine-containing free radicals, and at least one of silicon-containing free radicals, carbon-containing free radicals and hydrogen-containing free radicals are generated.
[0078] For example, the process gases mentioned above may include, but are not limited to, any one or more of nitrogen trifluoride (NF3), trifluoromethane (CHF3), carbon tetrafluoride (CF4), and sulfur hexafluoride (SF6).
[0079] In some embodiments, the process temperature of the free radical etching process is less than 20°C. For example, the process temperature of the free radical etching process can be 12°C, 14°C, 16°C, 18°C, or 20°C, etc.
[0080] It is understood that the etching selectivity is related to the process temperature during the radical etching process; the lower the process temperature, the higher the etching selectivity. Therefore, lowering the process temperature is beneficial to improving the etching selectivity. In the preparation method provided in the above embodiments, the process temperature of the radical etching process is less than 20°C, thereby ensuring that the etching gas can have a high etching selectivity for the first part 41 of the sidewall structure 4, the sacrificial pattern 3, and the filling dielectric layer 5.
[0081] Please see Figure 6 In step S300, the second part 42 of the sidewall structure 4 and the mask material layer 2 are etched based on the sacrificial pattern 3 and the filling medium layer 5.
[0082] like Figure 6As shown, the sacrificial pattern 3, the filling medium layer 5, the second part 42 of the retained sidewall structure 4, and the retained mask material layer 2 together constitute the target pattern P.
[0083] This application embodiment does not specifically limit the method of etching the second part 42 of the sidewall structure 4 and the mask material layer 2 based on the sacrificial pattern 3 and the filling dielectric layer 5 in step S300. In some embodiments, a plasma etching process can be used to etch the second part 42 of the sidewall structure 4 and the mask material layer 2 based on the sacrificial pattern 3 and the filling dielectric layer 5.
[0084] As an example, plasma etching processes may include, but are not limited to, inductively coupled plasma (ICP) etching, capacitively coupled plasma (CCP) etching, or electron cyclotron resonance (ECR) plasma etching, etc.
[0085] In some embodiments, inductively coupled plasma etching (ICP) can be used to etch the second portion 42 of the sidewall structure 4 and the mask material layer 2 based on the sacrificial pattern 3 and the filling dielectric layer 5. ICP etching uses a high-frequency electric field to excite gas to generate plasma, which has very high energy and can achieve a high etching rate. Compared to other plasma etching processes, ICP etching has a faster etching rate, which is beneficial for improving the production efficiency of semiconductor manufacturing processes. Furthermore, since the high-frequency electric field used in ICP etching can provide uniform plasma density and energy distribution, using ICP etching also helps to improve the uniformity of the etching process, thereby further improving the production yield of semiconductor manufacturing processes and the reliability of products.
[0086] Please see Figure 7 In some embodiments, after forming the target pattern P, the method for fabricating the semiconductor structure may further include the following steps:
[0087] The substrate 1 is etched based on the sacrifice pattern 3, the filling dielectric layer 5, the second part 42 of the retained sidewall structure 4, and the retained mask material layer 2 to transfer the target pattern P to the substrate 1.
[0088] Specifically, in some embodiments, the target pattern P is transferred to the target layer 12 in the substrate 1 by etching the substrate 1 based on the sacrifice pattern 3, the filling dielectric layer 5, the second portion 42 of the retained sidewall structure 4 and the retained mask material layer 2.
[0089] In addition, please continue to refer to Figure 3In some embodiments, the method for forming the sacrifice pattern 3 can specifically manifest as the following steps:
[0090] A sacrificial material layer and a hard mask material layer are sequentially formed on a substrate 1; the hard mask material layer is patterned based on a photomask to form a hard mask layer 6; the sacrificial material layer is etched based on the hard mask layer 6 to form a plurality of sacrificial patterns 3 spaced apart.
[0091] In the preparation method provided in the above embodiments, the sidewall material layer 4' formed in step S110 can also conformally cover the sidewalls and top of the hard mask layer 6; that is, at this time, the hard mask layer 6 is located between the sidewall material layer 4' and the sacrificial pattern 3. In step S120, as Figure 4 As shown, the hard mask layer 6 can be removed during the process of removing the sidewall material layer 4' located on top of the sacrificial pattern 3 and the exposed surface of the mask material layer 2, and removing a portion of the height of the filling medium material layer 5'.
[0092] The preparation method provided in the above embodiments can remove the hard mask layer 6 simultaneously during step S120, thus eliminating the need for additional removal steps. Therefore, it can simplify the process steps of the preparation method and help reduce the process difficulty and cost of the preparation method.
[0093] This application does not specifically limit the constituent material of the hard mask layer 6. As an example, the constituent material of the hard mask layer 6 may include, but is not limited to, silicon oxynitride.
[0094] On the other hand, according to some embodiments, this application also provides an apparatus for fabricating a semiconductor structure. The fabrication apparatus can be used to perform the semiconductor structure fabrication method provided in the foregoing embodiments.
[0095] Please see Figure 8 In some embodiments, the semiconductor structure fabrication apparatus includes a radical etching chamber 10 and a plasma etching chamber 20. The radical etching chamber 10 and the plasma etching chamber 20 can be connected to the same platform.
[0096] The semiconductor structure fabrication apparatus provided in the above embodiments can perform the semiconductor structure fabrication methods provided in some of the foregoing embodiments. Therefore, the technical effects achievable by the aforementioned semiconductor structure fabrication methods can also be achieved by the semiconductor structure fabrication apparatus provided in the above embodiments, and will not be described in detail here. Furthermore, by adopting the above structure, the semiconductor structure fabrication apparatus can also leverage the advantages of different equipment in different steps of the fabrication method.
[0097] It is understood that the technical features between the device embodiments and the method embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can understand the technical content of this application.
[0098] In this embodiment of the application, the free radical etching reaction chamber 10 and the plasma etching reaction chamber 20 are connected to the same platform, which means that the free radical etching reaction chamber 10 and the plasma etching reaction chamber 20 can be integrated on the same platform.
[0099] Please continue reading. Figure 8 In some embodiments, the plasma etching reaction chamber 20 includes an inductively coupled plasma etching reaction chamber (ICP Etch Chamber).
[0100] In some embodiments, the platform further includes a transport system. The transport system may specifically include a vacuum transport module (VTM) and a loading platform.
[0101] like Figure 8 As shown, the vacuum transmission module may include a vacuum transmission chamber 301 and a vacuum manipulator 302 disposed within the vacuum transmission chamber 301. The free radical etching reaction chamber 10 and the plasma etching reaction chamber 20 may be arranged circumferentially between the vacuum transmission chamber 301 and connected to the vacuum transmission chamber 301.
[0102] In the process of performing the semiconductor structure fabrication method using the above-described semiconductor structure fabrication apparatus, the semiconductor structure transfer process on the transfer platform may include: the process of transferring the semiconductor structure to the free radical etching reaction chamber 10 via the vacuum manipulator 302 in the vacuum transfer chamber 301 to perform the corresponding steps, the process of transferring the semiconductor structure from the free radical etching reaction chamber 10 to the plasma etching reaction chamber 20 via the vacuum manipulator 302 to perform the corresponding steps, and the process of returning to the loading stage after the aforementioned steps are completed.
[0103] On the other hand, this application also provides a semiconductor structure according to some embodiments. Please continue reading. Figure 6 The semiconductor structure is prepared using the preparation method provided in the foregoing embodiments. By using the preparation method provided in the foregoing embodiments, the obtained semiconductor structure is closer to the predetermined shape.
[0104] The semiconductor structures provided in the above embodiments can be prepared using the methods described in the foregoing embodiments. Therefore, the technical effects achievable by the aforementioned semiconductor structure preparation methods can also be achieved by the semiconductor structures provided in the foregoing embodiments, and will not be detailed here. Furthermore, the technical features between the structural embodiments and the method embodiments can be substituted for and supplemented each other without conflict, so that those skilled in the art can understand the technical content of this application.
[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0106] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A mask material layer and a patterned sacrificial layer are sequentially formed on the substrate along a direction perpendicular to the substrate. The patterned sacrificial layer includes a plurality of sacrificial patterns spaced apart. A sidewall structure is formed, the sidewall structure comprising a first portion conformally covering the sidewall of the sacrificial pattern and a second portion conformally covering the exposed surface of the mask material layer; A filling medium layer is formed on the second portion, the filling medium layer filling the gap between adjacent first portions; Remove the first portion of the sidewall structure and retain the second portion; Based on the sacrificial pattern and the filling medium layer, the second part of the sidewall structure and the mask material layer are etched, and the sacrificial pattern, the filling medium layer, the retained second part of the sidewall structure and the retained mask material layer together constitute the target pattern; The formation of the sidewall structure includes: A sidewall material layer is conformally covered on the sidewalls and top of the sacrifice pattern and on the exposed surface of the mask material layer; a filling medium material layer is formed covering the sidewall material layer; Remove the sidewall material layer located on top of the sacrificial pattern and on the exposed surface of the mask material layer; remove a portion of the height of the filler medium material layer so that the top surface of the remaining filler medium material layer is flush with or approximately flush with the top surface of the sacrificial pattern; the remaining sidewall material layer serves as the sidewall structure, and the remaining filler medium material layer serves as the filler medium layer.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Removing the first portion of the sidewall structure while retaining the second portion includes: The first portion of the sidewall structure is removed using a free radical etching process with an etching gas having a high selectivity.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The free radical etching process includes: The etching gas dissociates to obtain fluorine-containing free radicals, and at least one of silicon-containing free radicals, carbon-containing free radicals, and hydrogen-containing free radicals.
4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The process temperature of the free radical etching process is less than 20°C.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that, A free radical etching process is used to etch back the sidewall material layer located on top of the sacrificial pattern and on the exposed surface of the mask material layer, as well as the filler medium material layer of the specified height, to remove the sidewall material layer located on top of the sacrificial pattern and on the exposed surface of the mask material layer, and to remove the filler medium material layer of the specified height.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the target pattern, the method for fabricating the semiconductor structure further includes: The substrate is etched based on the sacrifice pattern, the filling dielectric layer, the second portion of the retained sidewall structure, and the retained mask material layer to transfer the target pattern to the substrate.
7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that, The second part of the sidewall structure and the mask material layer are etched using a plasma etching process based on the sacrificial pattern and the filling dielectric layer.
8. An apparatus for fabricating a semiconductor structure, characterized in that, The apparatus is used to perform the method for fabricating a semiconductor structure as described in claim 7; the semiconductor structure fabrication apparatus includes: a free radical etching reaction chamber and a plasma etching reaction chamber; the free radical etching reaction chamber and the plasma etching reaction chamber are connected to the same platform.
9. A semiconductor structure, characterized in that, The semiconductor structure is prepared using the preparation method described in any one of claims 1 to 7.